Patent application number | Description | Published |
20080205023 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 08-28-2008 |
20080205024 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 08-28-2008 |
20080218990 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 09-11-2008 |
20080225488 | PUMP STRUCTURES INTEGRAL TO A FLUID FILLED HEAT TRANSFER APPARATUS - Presented is a heat sink arrangement, incorporating a fluid media, which transfers heat between stationary and movable objects. Included are pump structures which are designed to be or operate integrally with the fluid-filled heat transfer apparatus, and are adapted to provide optimum and unique cooling flow paths for implementing the cooling of electronic devices, such as computer chips or the like, that require active cooling action. The pumps and heat sink arrangements selectively possess either rotating or stationary shafts, various types of impeller and fluid or cooling media circulation structures, which maximize both the convective and conductive cooling of the various components of the electronic devices or equipment by means of the circulating fluid. | 09-18-2008 |
20080226875 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 09-18-2008 |
20080313879 | METHOD AND STRUCTURE FOR A PULL TEST FOR CONTROLLED COLLAPSE CHIP CONNECTIONS AND BALL LIMITING METALLURGY - A tensile strength testing structure for controlled collapse chip connections (C | 12-25-2008 |
20090085161 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints. | 04-02-2009 |
20090114429 | PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS - A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished. | 05-07-2009 |
20090169886 | NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION - Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods. | 07-02-2009 |
20090265028 | Organic Substrate with Asymmetric Thickness for Warp Mitigation - A process for large scale production of a laminated organic substrate having reduced thermal warp. | 10-22-2009 |
20100218364 | PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS - A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished. | 09-02-2010 |
20110123318 | HEAT TRANSFER DEVICE IN A ROTATING STRUCTURE - A cooling system includes a moving rotor system which in turn includes: a rotating disk on which a plurality of heat conducting structures are distributed, the heat conducting structures including an inner arrangement of spiral blades; an air flow generating fan element; and an outer arrangement of heat transfer pins distributed along a perimeter of the rotating disk, the heat transfer pins having a high aspect ratio that maximizes a surface area to footprint area; wherein the spiral blades generate a mass fluid flow of ambient fluid toward the heat transfer pins such that the heat transfer pins are persistently cooled. | 05-26-2011 |
20120121906 | NEGATIVE COEFFICIENT THERMAL EXPANSION ENGINEERED PARTICLES FOR COMPOSITE FABRICATION - Methods for the fabrication of negative coefficient thermal expansion engineered elements, and particularly, wherein such elements provide for fillers possessing a low or even potentially zero coefficient thermal expansion and which are employable as fillers for polymers possessing high coefficients of thermal expansion. Further, disclosed are novel structures, which are obtained by the inventive methods. | 05-17-2012 |
20120309187 | Conformal Coining of Solder Joints in Electronic Packages - Thermal deformation of a substrate and the substrate's warp at room temperature are used to determine the expected profile of the substrate at reflow. A contact surface profile of a coining pressure plate is selected based on the expected substrate profile. A solder surface is shaped on the substrate or a die to be joined to the substrate by the coining pressure plate, thereby facilitating the chip-joining process. | 12-06-2012 |
20130260534 | STRESS REDUCTION MEANS FOR WARP CONTROL OF SUBSTRATES THROUGH CLAMPING - A method is provided for bonding a semiconductor chip to a packaging substrate while minimizing the variation in the solder ball heights and controlling the stress in the solder balls and the stress in the packaging substrate. During the solder reflow, the warp of the packaging substrate, including the absolute warp, thermal warp, and substrate to substrate variations of the warp, is constrained at a minimal level by providing a clamping constraint to the packaging substrate. During cool down of the solder balls, the stresses and strains of the solder joints are maintained at levels that do not cause tear of the solder joints or breakage of the packaging substrate by removing the clamping constraint. Thus, the bonding process provides both uniform solder height with minimized solder non-wets and stress minimization of the solder balls and the packaging substrate. | 10-03-2013 |
20140151849 | ELECTRONIC COMPONENTS ON TRENCHED SUBSTRATES AND METHOD OF FORMING SAME - An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate. | 06-05-2014 |
20140359995 | CONSTRAINED DIE ADHESION CURE PROCESS - A clamping apparatus applies a force to a workpeice during processing. The clamping apparatus includes a base defining a work area configured to receive a joined structure having multiple elements. The base defines a recess in the work area. An adjustable mechanism is configured to releasably couple to the base and apply a adjustable downward force to the joined structure to bend the joined structure downwardly into the recess during a process. A resilient plunger is part of the adjustable mechanism. The resilient plunger extends downwardly from a top plate of the adjustable mechanism, and the resilient plunger is configured to contact a top of a first element of the joined structure to apply the downward force. | 12-11-2014 |
20150024549 | ALIGNMENT OF INTEGRATED CIRCUIT CHIP STACK - The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. | 01-22-2015 |
20150041524 | VACUUM CARRIERS FOR SUBSTRATE BONDING - A vacuum carrier can be employed to provide a partial vacuum on a back side surface of a substrate thereby holding the substrate flat against a rigid surface of the carrier throughout the duration of a bonding process. The magnitude of vacuum can be optimized to limit the warping of the substrate during and after bonding with another substrate, and to limit the mechanical stress induced in the solder balls during cooling. The vacuum carrier can include a base plate, a seal plate with at least one opening configured to accommodate at least one substrate, and vacuum seal elements configured to create a vacuum environment that pushes the substrate against the base plate when the vacuum carrier is under vacuum. The configuration of the vacuum carrier is chosen to avoid distortion of the substrate due to the vacuum seal elements, while allowing adjustment of the magnitude of the partial vacuum. | 02-12-2015 |