Patent application number | Description | Published |
20080224735 | Frequency Synthesis Rational Division - A system and method are provided for synthesizing signal frequencies using rational division. The method accepts a reference frequency value and a synthesized frequency value. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (dp) and an integer value denominator (dq) are determined. The method reduces the ratio of dp/dq to an integer N and a ratio of p/q (dp/dq=N(p/q)), where p/q<1 (decimal). The numerator (p) and the denominator (q) are supplied to a flexible accumulator module, and a divisor is generated as a result. N is summed with a k-bit quotient to create the divisor. In a phase-locked loop (PLL), the divisor and the reference signal are used to generate a synthesized signal having a frequency equal to the synthesized frequency value. | 09-18-2008 |
20080225989 | High speed multi-modulus prescalar divider - A system and method are provided for multi-modulus division. The method accepts an input first signal having a first frequency and divides the first frequency by an integral number. A second signal is generated with a plurality of phase outputs, each having a second frequency. Using a daisy-chain register controller, phase outputs are selected and supplied as a third signal with a frequency. Selecting phase outputs using the daisy-chain register controller includes supplying the third signal as a clock signal to registers having outputs connected in a daisy-chain. Then, a sequence of register output pulses is generated in response to the clock signals, and register output pulses are chosen from the sequence to select second signal phase outputs. By using 8-second signal phase outputs, a third signal is obtained with a frequency equal to the second frequency multiplied by one of the following numbers: 0.75, 0.875, 1, 1.125, or 1.25. | 09-18-2008 |
20080304610 | Frequency Reacquisition in a Clock and Data Recovery Device - A system and method are provided for reacquiring a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous communication signal having an input data frequency. In response to acquiring the phase of the input data frequency, a synthesized signal is generated having an output frequency. Also as a result of acquiring the input data frequency, a frequency ratio value is selected. The output frequency is divided by the selected frequency ratio value, creating a divisor signal having a divisor frequency, which is compared to a reference signal frequency. In response to the comparison, the frequency ratio value is saved in a tangible memory medium. In response to losing phase-lock with the communication signal, the frequency ratio value is retrieved from memory. After acquiring the input data frequency, the phase of the communication signal is reacquired. | 12-11-2008 |
20090092213 | Frequency Hold Mechanism in a Clock and Data Recovery Device - A system and method are provided for holding the frequency of a non-synchronous communication signal in a clock and data recovery (CDR) device frequency synthesizer. The method initially acquires the phase of a non-synchronous first communication signal having a first frequency, and divides a first synthesized signal by a selected frequency ratio value, creating a frequency detection signal having a frequency equal to a reference signal frequency. In response to losing the first communication signal and subsequently receiving a second communication signal with a non-predetermined second frequency, the frequency ratio value is retrieved from memory based upon the assumption that the second frequency is the same, or close to the first frequency. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a second synthesized signal is generated having an output frequency equal to first frequency. Using a rotational frequency detector (RFD), the second communication signal, and the second synthesized signal, a second synthesized signal is generated having an output frequency equal to second frequency. | 04-09-2009 |
20090122935 | False frequency lock detector - A system and method are provided for detecting a false clock frequency lock in a clock and data recovery (CDR) device. The method accepts a digital raw data signal at a first rate and counts edge transitions in the raw data signal, creating a raw count. A clock signal is also accepted at a second rate. The clock signal is a timing reference recovered from the raw data signal. The raw data signal is sampled at a rate responsive to the clock signal, generating a sampled signal. Edge transitions are counted in the sampled signal, creating a sampled count. Then, the raw count is compared to the sampled count, to determine if the first rate is equal to the second rate. The method is used to determine if the second rate is less than the first rateāto detect if the clock signal is incorrectly locked to the first rate. | 05-14-2009 |
20090147901 | Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device - A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired. | 06-11-2009 |
20090147904 | Frequency Lock Stability in Device Using Overlapping VCO Bands - A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO is selected. Using a phase-locked loop (PLL) and the initial VCO, the frequency of the input communication signal is acquired and the acquired signal tuning voltage of the initial VCO is measured. Then, the initial VCO is disengaged and a plurality of adjacent band VCOs is sequentially engaged. The acquired signal tuning voltage of each VCO is measured and a final VCO is selected that is able to generate the input communication signal frequency using an acquired signal tuning voltage closest to a midpoint of a predetermined tuning voltage range. | 06-11-2009 |
20090157791 | FLEXIBLE ACCUMULATOR FOR RATIONAL DIVISION - A system and method are provided for rational division. The method accepts accepting a binary numerator and a binary denominator. A binary first sum is created of the numerator and a binary first count from a previous cycle. A binary first difference is created between the first sum and the denominator. In response to comparing the first sum with the denominator, and first carry bit is generated and added to a first binary sequence. The first binary sequence is used to generate a k-bit quotient. Typically, the denominator value is larger than the numerator value. In one aspect, the numerator and denominator form a rational number. Alternately, the numerator may be an n-bit bit value formed as either a repeating or non-repeating sequence, and the denominator is an (n+1)-bit number with a decimal value of 2 | 06-18-2009 |
20090172070 | Single Clock Cycle First Order Limited Accumulator for Supplying Weighted Corrections - A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle. | 07-02-2009 |
20090201066 | Digitally Clock with Selectable Frequency and Duty Cycle - A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern. | 08-13-2009 |
20090279653 | Clock and Data Recovery Loop with ISI Pattern-Weighted Early-Late Phase Detection - An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated, where the Q clock has a fixed phase delay with respect to the I clock. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I and Q clocks, creating digital I-bit and Q-bit values, respectively. The I-bit values and Q-bit values are segmented into n-bit digital words. In response to analyzing the I-bit and Q-bit values, I clock phase corrections are identified. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. A phase error signal is generated by averaging the weighted I-bit values for each n-bit digital word, and I clock is modified in phase. | 11-12-2009 |
20090296867 | ISI Pattern-Weighted Early-Late Phase Detector with Jitter Correction - An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing Q-bit values sampled by the varied delay Q clock. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signal are generated. | 12-03-2009 |