Patent application number | Description | Published |
20100246249 | CHARGE CARRIER STREAM GENERATING ELECTRONIC DEVICE AND METHOD - The present invention discloses an electronic device comprising a generator for generating a stream ( | 09-30-2010 |
20110121364 | HETEROJUNCTION BIPOLAR TRANSISTOR - According to an example embodiment, a heterostructure bipolar transistor, HBT, includes shallow trench isolation, STI, structures around a buried collector drift region in contact with a buried collector. A gate stack including a gate oxide and a gate is deposited and etched to define a base window over the buried collector drift region and overlapping the STI structures. The etching process is continued to selectively etch the buried collector drift region between the STI structures to form a base well. SiGeC may be selectively deposited to form epitaxial silicon-germanium in the base well in contact with the buried collector drift region and poly silicon-germanium on the side walls of the base well and base window. Spacers are then formed as well as an emitter. | 05-26-2011 |
20110198591 | METHOD OF MANUFACTURING HETEROJUNCTION BIPOLAR TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer ( | 08-18-2011 |
20110215841 | DEVICE FOR AND A METHOD OF GENERATING SIGNALS | 09-08-2011 |
20120037914 | HETEROJUNCTION BIOPOLAR TRANSISTOR AND MANUFACTURING METHOD - A method of manufacturing a heterojunction bipolar transistor, including providing a substrate comprising an active region bordered by shallow trench insulation regions; depositing a stack of a dielectric layer and a polysilicon layer over the substrate; forming a base window in the stack, the base window extending over the active region and part of the shallow trench insulation regions, the base window having a trench extending vertically between the active region and one of the shallow trench insulation regions; growing an epitaxial base material inside the base window; forming a spacer on the exposed side walls of the base material; and filling the base window with an emitter material. A HBT manufactured in this manner and an IC including such an HBT. | 02-16-2012 |
20120038002 | IC AND IC MANUFACTURING METHOD - Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate ( | 02-16-2012 |
20120038415 | METHOD AND APPARATUS FOR MAINTAINING CIRCUIT STABILITY - A control circuit for a transistor arrangement comprises a monitoring arrangement ( | 02-16-2012 |
20120132961 | HETEROJUNCTION BIPOLAR TRANSISTOR MANUFACTURING METHOD AND INTEGRATED CIRCUIT COMPRISING A HETEROJUNCTION BIPOLAR TRANSISTOR - Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed. | 05-31-2012 |
20120132999 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR AND BIPOLAR TRANSISTOR - Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method. | 05-31-2012 |
20120168908 | SPACER FORMATION IN THE FABRICATION OF PLANAR BIPOLAR TRANSISTORS - A bipolar transistor is fabricated having a collector ( | 07-05-2012 |
20120213466 | Optocoupler Circuit - An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits. | 08-23-2012 |
20130032891 | METHOD OF MANUFACTURING AN IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS AND IC COMPRISING A PLURALITY OF BIPOLAR TRANSISTORS - A method of manufacturing an integrated circuit comprising bipolar transistors including first and second type bipolar transistors, the method comprising providing a substrate comprising first isolation regions each separated from a second isolation region by an active region comprising a collector impurity of one of the bipolar transistors; forming a base layer stack over the substrate; forming a first emitter cap layer of a first effective thickness over the base layer stack in the areas of the first type bipolar transistor; forming a second emitter cap layer of a second effective thickness different from the first effective thickness over the base layer stack in the areas of the second type bipolar transistor; and forming an emitter over the emitter cap layer of each of the bipolar transistors. An IC in accordance with this method. | 02-07-2013 |
20130056855 | METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC - Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. | 03-07-2013 |
20130087799 | BIPOLAR TRANSISTOR MANUFACTURING METHOD, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT - Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate ( | 04-11-2013 |
20130178037 | METHOD OF MANUFACTURING HETEROJUNCTION BIPOLAR TRANSISTOR AND HETEROJUNCTION BIPOLAR TRANSISTOR - A method of forming a heterojunction bipolar transistor by depositing a first stack comprising an polysilicon layer and a sacrificial layer on a mono-crystalline silicon substrate surface; patterning that stack to form a trench extending to the substrate; depositing a silicon layer over the resultant structure; depositing a silicon-germanium-carbon layer over the resultant structure; selectively removing the silicon-germanium-carbon layer from the sidewalls of the trench; depositing a boron-doped silicon-germanium-carbon layer over the resultant structure; depositing a further silicon-germanium-carbon layer over the resultant structure; | 07-11-2013 |
20140162426 | Bipolar transistor manufacturing method, bipolar transistor and integrated circuit - Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate ( | 06-12-2014 |
20140167055 | METHOD OF PROCESSING A SILICON WAFER AND A SILICON INTEGRATED CIRCUIT - Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor. | 06-19-2014 |
20140312356 | Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base. | 10-23-2014 |
20140327110 | METHOD OF MANUFACTURING A BIPOLAR TRANSISTOR, BIPOLAR TRANSISTOR AND INTEGRATED CIRCUIT - Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material. | 11-06-2014 |
20140347131 | SEMICONDUCTOR DEVICE AND CIRCUIT WITH DYNAMIC CONTROL OF ELECTRIC FIELD - A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit. | 11-27-2014 |
20140347135 | BIPOLAR TRANSISTORS WITH CONTROL OF ELECTRIC FIELD - The invention provides a bipolar transistor circuit and a method of controlling a bipolar transistor, in which the bipolar transistor has a gate terminal for controlling the electric field in a collector region of the transistor. The bias voltage applied to the gate terminal is controlled to achieve different transistor characteristics. | 11-27-2014 |
20150028847 | PUF METHOD USING AND CIRCUIT HAVING AN ARRAY OF BIPOLAR TRANSISTORS - A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed. | 01-29-2015 |
20150041862 | METHOD OF MANUFACTURING IC COMPRISING A BIPOLAR TRANSISTOR AND IC - Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate ( | 02-12-2015 |
20150145005 | TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT - Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed. | 05-28-2015 |
Patent application number | Description | Published |
20100121704 | Activating Content Distribution - A computer-implemented method for advertisement distribution includes receiving, in a computer system, an input from an advertiser that has previously registered an advertisement for on-demand activation. The input is generated based on the advertiser having an immediate availability and directs the computer system to initiate the on-demand activation substantially in real time with receiving the input. The method includes determining, using the computer system, a geographic location of the advertiser that corresponds to the immediate availability. The method includes defining, using the computer system, a target group to which the advertisement is to be presented, the target group identified based on at least the geographic location and the immediate availability. The method includes initiating the on-demand activation using the computer system, for receipt of the advertisement by at least part of the target group, the on-demand activation initiated substantially in real time with receiving the input. | 05-13-2010 |
20130336520 | SYSTEM AND METHOD FOR DISPLAYING CONTEXTUAL SUPPLEMENTAL CONTENT BASED ON IMAGE CONTENT - An image-based content item is analyzed to determine one or more interests of a viewer of the content item. The analysis may include performing image analysis on the content item to determine geographic information that is relevant to an image of the content item. The one or more interests may be determined based on an assumption or probabilistic conclusion about a subject of the content item. Further, the one or more interests may be determined by applying one or more rules that utilize the geographic information. For some embodiments, a supplemental content item may be provided to the viewer based on the one or more interests. | 12-19-2013 |
20140369626 | SYSTEM AND METHOD FOR PROVIDING OBJECTIFIED IMAGE RENDERINGS USING RECOGNITION INFORMATION FROM IMAGES - An embodiment provides for enabling retrieval of a collection of captured images that form at least a portion of a library of images. For each image in the collection, a captured image may be analyzed to recognize information from image data contained in the captured image, and an index may be generated, where the index data is based on the recognized information. Using the index, functionality such as search and retrieval is enabled. Various recognition techniques, including those that use the face, clothing, apparel, and combinations of characteristics may be utilized. Recognition may be performed on, among other things, persons and text carried on objects. | 12-18-2014 |