Van Der Goes
Franciscus Van Der Goes, Den Haag NL
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20150214946 | LOW-POWER LEVEL-SHIFT CIRCUIT FOR DATA-DEPENDENT SIGNALS - A low-power level-shift circuit for data-dependent signals includes a buffer circuit, a coupling capacitor, and a biasing circuit. The buffer circuit is biased by a low-voltage domain voltage supply and configured to receive a data-dependent signal. The coupling capacitor is coupled, at a first node, to an output node of the buffer circuit. The biasing circuit is coupled to a second node of the coupling capacitor and a switch. The level-shift circuit can translate a voltage level of the received data-dependent signal to a high-voltage domain that is suitable for proper operation of the switch. | 07-30-2015 |
Franciscus Maria Leonardus Van Der Goes, Den Haag NL
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20150117508 | Broadband amplifier linearization using captured histogram data - A transmitter's operation is characterized using components having relatively low cost and low complexity. A device includes comparator(s) that compare a transmitter's analog output to predetermined level(s) to generate count(s) associated with analog output range bin(s). Each of the predetermined levels is associated with a corresponding one of the analog output range bins. A transfer function of the transmitter is generated using the comparison count values associated with the analog output range bin(s). A histogram may be generated from the comparison count values associated with the various analog output range bins. An equalizer is implemented to process data that will be transmitted by the transmitter. The equalizer uses equalizer parameter(s) that are selected based on the characterization of the transmitter (e.g., its transfer function, its histogram, etc.). The equalizer may use default or start up parameters until the transmitter's operation is characterized. | 04-30-2015 |
Franciscus Maria Leonardus Van Der Goes, The Hague NL
Patent application number | Description | Published |
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20150149654 | Modular Analog Frontend - A system may include a first stage comprising first signaling components for a first protocol, and a second stage comprising second signaling components for the first protocol and a second protocol. The system may further include logic configured to receive an incoming data stream, and determine a stream protocol for the data stream. The logic may be further configured to, responsive to the determination, activate the at least a portion of the first stage when the stream protocol is compliant with the first protocol, and when the stream protocol is compliant with the second protocol, deactivate the first stage. | 05-28-2015 |
Frank Maria Leonardus Van Der Goes, Den Haag NL
Patent application number | Description | Published |
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20150054668 | Switched Capacitance Converter - A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit. | 02-26-2015 |