Patent application number | Description | Published |
20090061543 | METHOD FOR CALIBRATING AN INSPECTION TOOL - Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point. | 03-05-2009 |
20120137396 | Characterizing Dimensions of Structures Via Scanning Probe Microscopy - A method comprising characterizing the dimensions of structures on a semiconductor device having dimensions less than approximately 100 nanometers (nm) using one of scanning probe microscopy (SPM) or profilometry. | 05-31-2012 |
20140143912 | SYSTEM AND METHOD FOR NON-CONTACT MICROSCOPY FOR THREE-DIMENSIONAL PRE-CHARACTERIZATION OF A SAMPLE FOR FAST AND NON-DESTRUCTIVE ON SAMPLE NAVIGATION DURING NANOPROBING - A system for performing sample probing. The system including an topography microscope configured to receive three-dimensional coordinates for a sample based on at least three fiducial marks; receive the sample mounted in a holder; and navigate to at least a location on the sample based on the at least three fiducial marks and the three-dimensional coordinates. | 05-22-2014 |
20140380531 | PROBE-BASED DATA COLLECTION SYSTEM WITH ADAPTIVE MODE OF PROBING CONTROLLED BY LOCAL SAMPLE PROPERTIES - A method for testing an integrated circuit (IC) using a nanoprobe, by using a scanning electron microscope (SEM) to register the nanoprobe to an identified feature on the IC; navigating the nanoprobe to a region of interest; scanning the nanoprobe over the surface of the IC while reading data from the nanoprobe; when the data from the nanoprobe indicates that the nanoprobe traverse a feature of interest, decelerating the scanning speed of the nanoprobe and performing testing of the IC. The scanning can be done at a prescribed nanoprobe tip force, and during the step of decelerating the scanning speed, the method further includes increasing the nanoprobe tip force. | 12-25-2014 |
Patent application number | Description | Published |
20090053834 | USE OF SCATTEROMETRY FOR IN-LINE DETECTION OF POLY-SI STRINGS LEFT IN STI DIVOT AFTER GATE ETCH - One embodiment of the present invention relates to a method of forming an integrated circuit, comprising forming an STI structure in a semiconductor body, the STI structure having a divot characteristic, performing scatterometry on the STI structure and obtaining signature spectra associated therewith, and continuing fabrication of the integrated circuit when the obtained signature spectra satisfies a predetermined performance specification. | 02-26-2009 |
20090100917 | ROCKING Y-SHAPED PROBE FOR CRITICAL DIMENSION ATOMIC FORCE MICROSCOPY - Measuring surface profiles of structures on integrated circuits is difficult when feature sizes are less than 100 nanometers. Atomic force microscopy provides surface profile measurement capability on flat horizontal surfaces, but has difficulty with three-dimensional structures such as MOS transistor gates, contact and via holes, interconnect trenches and photoresist patterns. An atomic force microscopy probe with two atomically sharp tips configured to facilitate measurements of three-dimensional structures is disclosed. A method of making such measurements using the disclosed probe and a method of fabricating an IC encompassing the method are also claimed. | 04-23-2009 |
20090159937 | Simple Scatterometry Structure for Si Recess Etch Control - Dimensions of structures in integrated circuits are shrinking with each new fabrication technology generation. Maintaining control of profiles of structures in transistors and interconnects is becoming more important to sustaining profitable integrated circuit production facilities. Measuring profiles of structures with many elements in integrated circuits, such as MOS transistor gates with recessed regions for Si—Ge epitaxial layers, is not cost effective for the commonly used metrology techniques: SEM, TEM and AFM. Scatterometry is technically unfeasible due to the number of elements and optical constants. The instant invention is a simplified scatterometry structure which reproduces the profiles of a structure to be profiled in a simpler structure that is compatible with conventional scatterometric techniques. A method of fabricating a transistor and an integrated circuit using the inventive simplified scatterometry structure are also disclosed. | 06-25-2009 |
20090262335 | HOLOGRAPHIC SCATTEROMETER - Exemplary embodiments provide a system and method for holographic scatterometry by using holography in a scatterometry system to record amplitude and phase of scattered light from a featured object in order to measure geometries and/or feature dimensions of the object. The amplitude and phase information can be obtained simultaneously and instantaneously in a single tool with incident and azymuthal angular resolution. Specifically, the holographic scatterometry can include a splitter for producing two coherent beams including a test beam and a reference beam. The test beam can be focused on and scattered, diffracted and/or reflected from the featured object and interfered with the reference beam on an image sensor (e.g., a charge-coupled device (CCD) camera). The resulting holographic information on the camera plane can include all angular amplitude and phase information of the scattered light from the measured object. The holographic scatterometry can thus include a combined power of angular reflectometry and ellipsometry. | 10-22-2009 |