Tu, TW
Chao-Chou Tu, Longtan Township TW
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20090065345 | METHOD AND DEVICE FOR PURIFYING 1,4-BIS (BROMODIFLUOROMETHYL) BENZENE - A method and a device for purifying 1,4-bis (bromodifluoromethyl) benzene are disclosed. In order to solve the problem of hard to purify and separate 1,4-bis (bromodifluoromethyl) benzene crude products, diphenylmethane that has a higher boiling point and does not interact with 1,4-bis (bromodifluoromethyl) benzene is mixed with the 1,4-bis (bromodifluoromethyl) benzene crude products for evaporation. Afterwards, the purity of the vaporized product is detected and only that reaching an expected purity is collected to obtain high-purity 1,4-bis (bromodifluoromethyl) benzene. | 03-12-2009 |
Cheng-Hsin Tu, Tainan TW
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20100116341 | Copper-gallium allay sputtering target, method for fabricating the same and related applications - A method for fabricating a copper-gallium alloy sputtering target comprises forming a raw target; treating the raw target with at least one thermal treatment between 500° C.˜850° C. being mechanical treatment, thermal annealing treatment for 0.5˜5 hours or a combination thereof to form a treated target; and cooling the treated target to a room temperature to obtain the copper-gallium alloy sputtering target that has 71 atomic % to 78 atomic % of Cu and 22 atomic % to 29 atomic % of Ga and having a compound phase not more than 25% on its metallographic microstructure. Therefore, the copper-gallium alloy sputtering target does not induce micro arcing during sputtering so a sputtering rate is consistent and forms a uniform copper-gallium thin film. Accordingly, the copper-gallium thin film possesses improved quality and properties. | 05-13-2010 |
20100288631 | CERAMIC SPUTTERING TARGET ASSEMBLY AND A METHOD FOR PRODUCING THE SAME - A method for producing a ceramic sputtering target assembly has steps of providing a backing plate and forming a solder layer on a surface of the backing plate; providing a ceramic target and forming an interface layer on a surface of the ceramic target; annealing the ceramic target with the interface layer; and solder-bonding the solder layer of the backing plate and the interface layer of the ceramic target to obtain the ceramic sputtering target assembly. By annealing the interface layer made of chromium or chromium-containing alloy, the interface layer provides excellent adhesive ability to solder-bonding the solder layer and allows the ceramic target and the backing plate to be combined securely. | 11-18-2010 |
Cheng-Ta Tu, Taoyuan TW
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20090175713 | BOARD INVERTER - The present invention relates to a board inverter and a boarding inverting system. The board inverter includes a support, a first board picking device, an second board picking device and a controller. Each of the first board picking device and the second board picking device includes a driving mechanism and a first board picking device. The driving mechanism comprises a first linear driving means mounted on the support, a second linear driving means mechanically coupled to the first linear driving means, and a rotary driving means attached to the second linear driving means. The controller is connected to all the power supply members. The controller controls the motion of the first board picking device and the second board picking device such that the first board picking device and the second board picking device cooperatively inverting workpieces transmitted on a production line. The board inverter can be installed on a production line without altering the arrangement of existing production line. | 07-09-2009 |
Cheng-Ti Tu, Tainan Hsien TW
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20090032543 | Drinking cup cover - A drinking cup cover includes a cover body and a closure member. The cover body has a cover wall with top and bottom surfaces, a peripheral portion, and a beverage hole formed through the top and bottom surfaces of the cover wall adjacent to the peripheral portion. The cover wall further has a hole-defining periphery that defines the beverage hole. The closure member includes a tab part, a depressible part, and an engaging part. The tab part is connected to the hole-defining periphery such that the closure member is movable relative to the cover body between a sipping position and a non-sipping position. The depressible part protrudes upwardly from the tab part and is operable to move the tab part downwardly from the non-sipping position to the sipping position. The engaging part is formed on one end of the depressible part opposite to tab part to engage the hole-defining periphery. | 02-05-2009 |
Chen-Sheng Tu, Sanchong City TW
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20100253757 | KEYBOARD, PRINTING METHOD OF PATTERN ON KEY CAP, AND PRINTING METHOD OF PATTERN ON KEYBOARD - A keyboard which includes a plurality of key caps is provided. Each of the key caps includes a surface respectively and the surfaces of the key caps are coplanar substantially. Therein a pattern which includes a plurality of ink dots is formed on each surface of the key caps. The pattern formed by the ink dots could be a symbol, a character, a graph, or a combination thereof and several patterns could form a combination pattern. Additionally, the patterns could be covered with a protection layer. | 10-07-2010 |
Chia-Chen Tu, Taichung County TW
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20100212735 | SOLAR CELL AND METHOD FOR FABRICATING THE SAME - This invention discloses a high-efficiency solar cell structure which enables high throughput manufacturing process thereof. The solar cell is accomplished by forming a plurality of first emitter regions in a front surface of a substrate, a plurality of second emitter regions in the front surface, and a plurality of fingers. Each of the fingers is formed over a least a portion of the second emitter region and a portion of the first emitter region. The first emitter regions and the second emitter regions have a depth not less than 0.2 μm. | 08-26-2010 |
Chia Chin Tu, Kaohsiung City TW
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20110049219 | WIRE-BONDING MACHINE WITH COVER-GAS SUPPLY DEVICE - A wire-bonding machine includes a main body, a fixture block, a mounting block, a gas supply tube, a cover-gas supply device, a capillary tool and an electrode. The fixture block is provided with a chamber defined therein and a central bore formed at one side wall of the fixture block communicating the chamber. The mounting block has a fixture member extending upwards for being mounted to the main body and an electrode clamping member extending downwards into the chamber of the fixture block. The cover-gas supply device has a continuous gas passage and an orifice defined therein. The protection gas flows in a steady flow field around the orifice in the continuous gas passage of the cover-gas supply device so as to result in better ball formation during the ball formation and ball-bonding process. | 03-03-2011 |
Chia-Hsun Tu, Taichung City TW
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20110095971 | ELECTROPHORESIS DISPLAY PIXEL AND DISPLAY APPARATUS - An electrophoresis display pixel including an electrophoresis display film, a substrate, a first active device, a second active device, a first electrode, and a second electrode is provided. The substrate is disposed on the electrophoresis display film, and the substrate has a transparent region and a non-transparent region. The first active device and the second active device are disposed on the substrate and located in the non-transparent region. The first electrode is disposed on the substrate, located in the transparent region, and electrically connected to the first active device. The second electrode is disposed on the substrate, located in the non-transparent region, and electrically connected to the second active device. A light passes through the transparent region and enters the electrophoresis display film to be displayed. A display apparatus including the abovementioned electrophoresis display pixel is also provided. | 04-28-2011 |
Chieh-Huang Tu, Hsinchu Hsien TW
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20100188382 | Apparatus for Generating Over-drive Values Applied to LCD Display and Method Thereof - An over-drive value generating apparatus applied to an LCD display includes a pixel value converting unit, a gain generating unit and a calculation unit. The pixel value converting unit generates a converted pixel according to a current pixel of a current image and a corresponding pixel of a previous image. The gain generating unit generates a gain according to a position of the current pixel. The calculation unit generates an output pixel according to the current pixel, the converted pixel and the gain. | 07-29-2010 |
20100207939 | Image Adjusting Apparatus and Associated Method - An image adjusting method for extending vertical blanking intervals of an image signal is provided. Using the image adjusting method, an adjusted image signal is synchronized with an image signal before the adjustment to prevent image delay. The image adjusting method comprises providing a first image signal having a first data enable signal, wherein the first data enable signal has a first data enable duration; and generating a second data enable signal having a second data enable duration. The first and second data enable durations correspond to a same image frame of an image signal, and the second data enable duration substantially overlaps the first data enable duration. | 08-19-2010 |
20110292187 | 3D Display Control Device and Method Thereof - A three-dimensional (3D) display control device generates a suitable and fixed output timing signal for a 3D display panel. Regardless of input 3D video format, the 3D display control device maintains a stable 3D display quality. The 3D display control device includes a receiving unit, for receiving 3D video data and a corresponding input timing signal from a 3D video source; and a timing control unit, for generating a group of output timing signals for displaying the 3D video data to the 3D display panel according to the input timing signal. The group of output timing signals corresponds to a group of output timing parameters for the 3D display panel, and the group of output timing parameters is independent from a 3D video format of the 3D video data. | 12-01-2011 |
20120161928 | Display Apparatus, Remote Controller and Associated Display System - A display apparatus, remote controller and associated display system are provided. A plurality of peripheral apparatuses is controlled by a universal remote controller according to a remote control signal from the remote controller. The display apparatus displays a remote control menu respectively corresponding to the different peripheral apparatuses, so as to offer the universal remote control with a rich, intuitive and user-friendly user interface. | 06-28-2012 |
20130235151 | Image Adjusting Apparatus and Associated Method - An image adjusting method for extending vertical blanking intervals of an image signal is provided. Using the image adjusting method, an adjusted image signal is synchronized with an image signal before the adjustment to prevent image delay. The image adjusting method comprises providing a first image signal having a first data enable signal, wherein the first data enable signal has a first data enable duration; and generating a second data enable signal having a second data enable duration. The first and second data enable durations correspond to a same image frame of an image signal, and the second data enable duration substantially overlaps the first data enable duration. | 09-12-2013 |
Chih-Chiang Tu, Tauyen TW
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20080263501 | System, Method, and Computer-Readable Medium for Performing Data Preparation for a Mask Design - A method, computer-readable medium, and system for performing data preparation are provided. An integrated circuit design is received, and a plurality of pre-optical proximity correction processes are invoked such that the plurality of pre-optical proximity correction processes are performed in parallel. An optical proximity correction process is invoked in response to a determination that each of the plurality of pre-optical proximity correction processes have completed. A post-optical proximity correction process is invoked in response to a determination that the optical proximity correction process has completed | 10-23-2008 |
20090232384 | Mask Making Decision for Manufacturing (DFM) on Mask Quality Control - The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features. | 09-17-2009 |
20110091797 | SUPERIMPOSE PHOTOMASK AND METHOD OF PATTERNING - Provided is a photomask that includes a substrate having a first region and a second region, a first pattern disposed in the first region of the substrate, and a second pattern disposed in the second region of the substrate. The first and second patterns are a decomposition of a design pattern to be transferred onto a wafer in a lithography process. | 04-21-2011 |
20110159410 | COST-EFFECTIVE METHOD FOR EXTREME ULTRAVIOLET (EUV) MASK PRODUCTION - The present disclosure provides for many different embodiments. An exemplary method can include providing a blank mask and a design layout to be patterned on the blank mask, the design layout including a critical area; inspecting the blank mask for defects and generating a defect distribution map associated with the blank mask; mapping the defect distribution map to the design layout; performing a mask making process; and performing a mask defect repair process based on the mapping. | 06-30-2011 |
20110161893 | LITHOGRAPHIC PLANE CHECK FOR MASK PROCESSING - The present disclosure provides for many different embodiments. An exemplary method can include providing a mask fabricated according to a design pattern; extracting a mask pattern from the mask; converting the mask pattern into a rendered mask pattern, wherein the simulated design pattern includes the design pattern and any defects in the mask; simulating a lithography process using the rendered mask pattern to create a virtual wafer pattern; and determining whether any defects in the mask are critical based on the virtual wafer pattern. The critical defects in the mask can be repaired. | 06-30-2011 |
20110318863 | PHOTOVOLTAIC DEVICE MANUFACTURE - A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit. | 12-29-2011 |
20120003780 | PHOTOVOLTAIC CELL MANUFACTURE - A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout. | 01-05-2012 |
20120021555 | PHOTOVOLTAIC CELL TEXTURIZATION - A photovoltaic cell texturization method is disclosed. The method includes providing a photovoltaic cell substrate; and texturizing a surface of the photovoltaic cell substrate. The texturizing implements a nanoimprint lithography process to expose a portion of the surface of the photovoltaic cell substrate. An etching process is performed on the exposed portion of the exposed portion of the surface of the photovoltaic cell substrate. | 01-26-2012 |
20120207381 | Systems and Methods Eliminating False Defect Detections - A method for inspecting a manufactured product includes applying a first test regimen to the manufactured product to identify product defects. The first test regimen produces a first set of defect candidates. The method further includes applying a second test regimen to the manufactured product to identify product defects. The second test regimen produces a second set of defect candidates, and the second test regimen is different from the first test regimen. The method also includes generating a first filtered defect set by eliminating ones of the first set of defect candidates that are not indentified in the second set of defect candidates. | 08-16-2012 |
20120211675 | MASK MAKING DECISION FOR MANUFACTURING (DFM) ON MASK QUALITY CONTROL - The present disclosure provide a method for making a mask. The method includes assigning a plurality of pattern features to different data types; writing the plurality of pattern features on a mask; inspecting the plurality of pattern features with different inspection sensitivities according to assigned data types; and repairing the plurality of pattern features on the mask according to the inspecting of the plurality of pattern features. | 08-23-2012 |
20120261563 | CONTAMINATION INSPECTION - A method of forming a standard mask for an inspection system is provided, the method comprising providing a substrate within a chamber, and providing a tetraethylorthosilicate (TEOS) precursor within the chamber. The method further includes reacting the TEOS precursor with an electron beam to form silicon oxide particles of controlled size at one or more controlled locations on the substrate, the silicon oxide particles disposed as simulated contamination defects. | 10-18-2012 |
20130019938 | METHOD FOR FORMING PHOTOVOLTAIC CELL, AND RESULTING PHOTOVOLTAIC CELL - A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout. | 01-24-2013 |
20130193565 | SEMICONDUCTOR MASK BLANKS WITH A COMPATIBLE STOP LAYER - Provided is a method for creating a mask blank that include a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detect of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer. | 08-01-2013 |
20130323625 | Systems and Methods for Lithography Masks - Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate Mo | 12-05-2013 |
20140014176 | METHOD FOR MANUFACTURING PHOTOVOLTAIC DEVICE - A photovoltaic device manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell using nanoimprint technology to define individual cell units of the photovoltaic device. The methods can include providing a substrate; forming a first conductive layer over the substrate; forming first grooves in the first conductive layer using a nanoimprint and etching process; forming an absorption layer over the first conductive layer, the absorption layer filling in the first grooves; forming second grooves in the absorption layer using a nanoimprint process; forming a second conductive layer over the absorption layer, the second conductive layer filling in the second grooves; and forming third grooves in the second conductive layer and the absorption layer, thereby defining a photovoltaic cell unit. | 01-16-2014 |
20140106262 | Image Mask Film Scheme and Method - A system and method for repairing a photolithographic mask is provided. An embodiment comprises forming a shielding layer over an absorbance layer on a substrate. Once the shielding layer is in place, the absorbance layer may be repaired using, e.g., an e-beam process to initiate a reaction to repair a defect in the absorbance layer, with the shielding layer being used to shield the remainder of the absorbance layer from undesirable etching during the repair process. | 04-17-2014 |
20140189614 | METHOD AND SYSTEM OF MASK DATA PREPARATION FOR CURVILINEAR MASK PATTERNS FOR A DEVICE - A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask. | 07-03-2014 |
20140199787 | Semiconductor Mask Blanks with a Compatible Stop Layer - Provided is a method for creating a mask blank that includes a stop layer. The stop layer is optically compatible and process compatible with other layers included as part of the mask blanks. Such blanks may include EUV, phase-shifting, or OMOG masks. The stop layer includes molybdenum, silicon, and nitride in a proportion that allows for compatibility and aids in detection by a residual gas analyzer. Provided is also a method for the patterning of mask blanks with a stop layer, particularly the method for removing semi-transparent residue defects that may occur due to problems in prior mask creation steps. The method involves the detection of included materials with a residual gas analyzer. Provided is also a mask blank structure which incorporates the compatible stop layer. | 07-17-2014 |
20140255825 | Mask Blank for Scattering Effect Reduction - Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons. | 09-11-2014 |
20140335446 | Systems and Methods for Lithography Masks - Structure of mask blanks and masks, and methods of making masks are disclosed. The new mask blank and mask comprise a tripe etching stop layer to prevent damages to the quartz substrate when the process goes through etching steps three times. The triple etching stop layer may comprise a first sub-layer of tantalum containing nitrogen (TaN), a second sub-layer of tantalum containing oxygen (TaO), and a third sub-layer of TaN. Alternatively, the triple etching stop layer may comprise a first sub-layer of SiON material, a second sub-layer of TaO material, and a third sub-layer of SiON material. Another alternative may be one layer of low etching rate Mo | 11-13-2014 |
20150024306 | MASK OVERLAY CONTROL - Some embodiments of the present disclosure relate to a method of patterning a workpiece with a mask, wherein a scale factor between a geometry of the mask and a corresponding target shape of the mask is determined. The scale factor results from thermal expansion of the mask and geometry due to heating of the mask during exposure to radiation by an electron beam (e-beam) in the mask manufacturing process. A number of radiation pulses necessary to dispose the geometry on the mask is determined. A scale factor for the mask is then determined from the number of pulses. The target shape is then generated on the mask by re-scaling the geometry according to the scale factor prior to mask manufacturing. This method compensates for thermal deformation due to e-beam heating to improve OVL variability in advanced technology nodes. | 01-22-2015 |
20150060669 | Three-Dimensional Semiconductor Image Reconstruction Apparatus and Method - A system comprises an electron beam directed toward a three-dimensional object with one tilting angle and at least two azimuth angles, a detector configured to receive a plurality of scanning electron microscope (SEM) images from the three-dimensional object and a processor configured to calculate a height and a sidewall edge of the three-dimensional object. | 03-05-2015 |
Chih-Kai Tu, Taipei Hsien TW
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20090016014 | DISC DRIVE HOLDER FOR HOLDING A DISC DRIVE AND RELATED ELECTRONIC DEVICE - A disc drive holder includes a frame connected to a first side of a casing in a rotatable manner. A containing space is formed inside the frame for containing a disc drive. The disc drive holder further includes a supporting component pivoted to the frame. The supporting component includes a flexible section pivoted to the frame in a flexible manner, and a base section for supporting the frame on a second side of the casing when the flexible section is rotated out of the frame. | 01-15-2009 |
20090296344 | PORTABLE STORAGE DEVICE CAPABLE OF BEING DISASSEMBLED EASILY - A portable storage device includes a storage module whereon a hole is formed, and at least one lateral plate disposed on a lateral side of the storage module. A slot is formed on the lateral plate. The portable storage device further includes a fixture disposed on a front side of the storage module. The fixture includes at least one wedging component for wedging in the slot of the lateral plate, and at least one groove is formed on the fixture. The portable storage device further includes a lock mechanism disposed on a side of the fixture. The lock mechanism includes at least one lock including a protrusion for protruding into the groove on the fixture, and an elastic component connected to the lock for providing an elastic force to the lock so that the protrusion wedges in the groove on the fixture. | 12-03-2009 |
Chih-Wei Tu, Taoyuan County TW
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20080287007 | CONNECTOR FOR FIRST AND SECOND JOINTS HAVING DIFFERENT PIN QUANTITIES, ELECTRONIC APPARATUS WITH CONNECTOR AND COMBINATION - A connector and an electronic apparatus and a combination comprising the connector for first and second joints are disclosed. The connector includes a base, a plurality of first pins, and a plurality of second pins. The base has a first and a second connecting surface. The first pins are disposed on the first connecting surface and the quantity of the first pins is the same as the pin quantity of the first joint. In addition, the second pins are disposed on the second connecting surface and the total quantity of the second pins and the first pins is the same as the pin quantity of the second joint. The base may include two convex parts and a concave part. The first connecting surface and the second connecting surface are disposed on surfaces of the two convex parts respectively. The concave part accommodates the two convex parts. | 11-20-2008 |
20130149914 | SOCKET CONNECTOR, PLUG CONNECTOR, CONNECTOR ASSEMBLY, AND HANDHELD ELECTRONIC DEVICE - A socket connector having high current carrying capacity is provided by enlarging cross-section of particular terminals, to meet requirement such as transmitting large current or quick charge. Furthermore, a plug connector coupled with the socket connector, a connector assembly including the socket connector and the plug connector, and a handheld electronic device applying the socket connector are provided. | 06-13-2013 |
20130225000 | ELECTRONIC DEVICE AND AUDIO JACK THEREOF - An audio jack for receiving an audio plug includes a connection hole with a position detection portion and a first audio channel contact portion therein. When the audio plug is inserted into the connection hole to the linking position, a first audio channel connection portion of the audio plug contacts the position detection portion and the first audio channel contact portion. The position detection portion and the first audio channel contact portion respectively have a first distance and a second distance to an opening of the connection hole, wherein the second distance is smaller than the first distance. | 08-29-2013 |
20140051296 | METHOD OF FORMING COLORED APPEARANCE AND CONDUCTIVE CASING - A method of forming a colored appearance suitable for forming a colored appearance for a conductive casing of a connector is provided. The conductive casing has a body and at least one lead. The lead extends from the body. The method of forming a colored appearance includes the following steps. A surface of the conductive casing is roughened. A conductive metal layer is formed on the roughened surface of the conductive casing. A shielding layer is formed on a part of the conductive metal layer located on the lead. A colorful conductive layer is formed on the conductive casing. The shielding layer and a part of the colorful conductive layer located on the shielding layer are removed to expose the part of the conductive metal layer on the lead. Therefore, the conductive casing has a colored appearance. | 02-20-2014 |
20140065890 | CONNECTOR MODULE AND HANDHELD ELECTRONIC DEVICE - A connector module includes an electrical connector and a sound-receiving component. The connector includes an insulation casing and multiple conductive terminals disposed at and passing through the insulating casing. The insulation casing has a jack hole at the outer-side thereof and a channel at the inner-side thereof and extending along an axial direction. The connector is adapted to connect the plug plugged into the channel from the jack hole. The sound-receiving component is disposed at the insulation casing along a radial direction, wherein the insulation casing has an opening communicated with the channel and corresponding to the sound-receiving component and the sound-receiving component is adapted to receive the sound transmitted into the channel from the jack hole via the opening. A handheld electronic device is also provided which includes a casing and a connector module disposed in the casing and adapted to connect a plug or receive a sound. | 03-06-2014 |
20140268585 | ELECTRONIC MODULE AND ELECTRONIC DEVICE - An electronic device including a rear cover, a transparent front cover, a first electronic element, a second electronic element, a conductive tape, and an elastomer is provided. The transparent front cover is disposed on the rear cover. The first electronic element is disposed between the transparent front cover and the rear cover. The second electronic element is disposed between the first electronic element and the rear cover. The conductive tape is disposed between the first electronic element and the second electronic element, and contacts the first electronic element and the second electronic element to electrically connect the first electronic element to the second electronic element. The elastomer is disposed between the first electronic element and the second electronic element, and is attached to the conductive tape under pressure. An electronic module including the first electronic element, the second electronic element, the conductive tape, and the elastomer above is provided. | 09-18-2014 |
20140293555 | RECEPTACLE CONNECTOR AND ELECTRONIC DEVICE - A receptacle connector adapted to be fixed to a casing of an electronic device and electrically connected to a circuit board for enabling the receptacle connector to be adapted to connect with a plug connector is provided. The receptacle connector includes an insulating body and a plurality of conductive terminals. The insulating body has a tunnel, and the tunnel extends from the outer side of the insulating body to the inner side of the insulating body, wherein a side of the tunnel is exposed at a top portion of the insulating body, and the insulating body is adapted to be fixed to the casing to cover the side of the tunnel, so that the tunnel is adapted to form a plug hole with the casing. The conductive terminals are disposed through the insulating body. A receptacle connector and an electronic device are also provided. | 10-02-2014 |
20150064966 | CONNECTOR ASSEMBLY AND ELECTRONIC DEVICE - A connector assembly adapted to be disposed in a casing of an electronic device is provided. The connector assembly includes a connector and a locking member. The locking member includes a supporting portion and a holding portion connected to the supporting portion. The connector is disposed on the supporting portion. The locking member is adapted to clamp at an end of a substrate disposed in the casing, and the supporting portion and the holding portion lean against an upper side and a lower side of the end of the substrate respectively. An electronic device including the connector assembly aforementioned is also provided. | 03-05-2015 |
Chih-Yi Tu, Taoyuan TW
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20090175713 | BOARD INVERTER - The present invention relates to a board inverter and a boarding inverting system. The board inverter includes a support, a first board picking device, an second board picking device and a controller. Each of the first board picking device and the second board picking device includes a driving mechanism and a first board picking device. The driving mechanism comprises a first linear driving means mounted on the support, a second linear driving means mechanically coupled to the first linear driving means, and a rotary driving means attached to the second linear driving means. The controller is connected to all the power supply members. The controller controls the motion of the first board picking device and the second board picking device such that the first board picking device and the second board picking device cooperatively inverting workpieces transmitted on a production line. The board inverter can be installed on a production line without altering the arrangement of existing production line. | 07-09-2009 |
Chih-Ying Tu, Fongshan City TW
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20100201844 | Apparatus and Method for Image Capturing - An image capturing method including following steps is provided. A preview image is captured and compressed into a compressed preview image according to a preview quantization table. An image complexity is judged by determining the amount of high frequency components the preview image has according to a set of factors consisting of the preview quantization table, a resolution of the preview image and a size of the compressed preview image. The more the amount of high frequency components the preview image has, the higher the image complexity. A to-be-captured image is captured. An initial quantization table is determined according to a set of factors consisting of the image complexity, a resolution of the to-be-captured image and an image compression target. The to-be-captured image is compressed into an output image according to the initial quantization table. | 08-12-2010 |
Chih-Ying Tu, Jhubei City TW
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20080284861 | Image processing method and apparatus thereof - A method for obtaining a still image frame with anti-vibration clearness includes the following steps. Multiple raw image frames are captured during a capturing period according to a capturing instruction. The raw image frames are compressed respectively, according to a predetermined compression rule, into multiple compressed image frames each of which has a data length after such compression. The compressed image frames are stored according to a predetermined sequence. The data lengths of the compressed image frames stored are compared according to the predetermined sequence. The desired still image frame is obtained through the compressed image frame of which the data length has a unique feature among all the compressed image frames. | 11-20-2008 |
Ching-Hsiang Tu, Kaohsiung City TW
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20090062005 | Method for adjusting sensing range and sensitivity and inertia interactive aparatus and system using thereof - The present invention provides an architecture of a method, apparatus and system for user adjusting the sensing range and sensitivity dynamically according to various user statuses so as to obtain an appropriate interactive effect regardless of different age group of users. In the present invention, a way of adjusting sensing range according to a switch signal, or a ratio for adjusting magnitude of a processed signal, or changing the threshold of the application program directly are illustrated as embodiments respectively for adjusting the sensing range and sensitivity dynamically. | 03-05-2009 |
20130085712 | INERTIAL SENSING INPUT APPARATUS AND METHOD THEREOF - An inertial sensing input apparatus includes a motion sensing module, a state determination module, an attitude estimation module, a coordinate transformation module, a gravity elimination module, an integral operation module, a data storage module, a trajectory modification module and a trajectory removal module. When the inertial sensing input apparatus is in a moving time period, the coordinate transformation module transforms a relative acceleration measured by the motion sensing module to an absolute acceleration based on a rotational attitude estimated by the attitude estimation module. The integral operation module calculates a velocity and a displacement based on an absolute acceleration revised by the gravity elimination module and forwards them to the data storage module. When the K | 04-04-2013 |
Ching Liang Tu, Sinshih Township TW
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20090177007 | PROCESS FOR PRODUCING CARBOXYLIC ACID ANHYDRIDES - The present invention relates to a process for producing carboxylic acid anhydrides, in which a carboxylic acid ester, derived from an alcohol and a carboxylic acid, and carbon monoxide containing a small amount of hydrogen are used as raw materials and subjected to a carbonylation reaction in a liquid reaction medium in the presence of a Group VIII B catalyst to produce a carboxylic acid anhydride. The reaction medium comprises the Group VIII B catalyst, an organic halide, the carboxylic acid ester, an alkali metal salt, at least one organic promoter, the carboxylic acid anhydride and the carboxylic acid, wherein the organic promoter is selected from at least one of the following structural forms (I), (II) and (III). According to the process of the present invention, the reaction rate of the carbonylation reaction is increased by the use of the specified organic promoters. | 07-09-2009 |
Ching Liang Tu, Tainan County TW
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20100145098 | PROCESS FOR PRODUCING CARBOXYLIC ACID ANHYDRIDES - A process for producing carboxylic acid anhydrides by the carbonylation reaction of a carboxylic acid ester, derived from an alcohol and a carboxylic acid, with carbon monoxide containing a small amount of hydrogen in a liquid reaction medium in the presence of a Group VIII B catalyst to produce a carboxylic acid anhydride. The reaction medium comprises the Group VIII B catalyst, an organic halide, the carboxylic acid ester, an alkali metal salt, the carboxylic acid anhydride, the carboxylic acid, and at least one ionic liquid consisting of a cation and an anion where the cation of the ionic liquid has a nitrogen-containing heterocyclic structure. The ionic liquid has at least one of the following structural forms: | 06-10-2010 |
Chin-Yuan Tu, Taoyuan County TW
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20110001534 | Voltage Generator Capable of Preventing Latch-up and Method Thereof - A voltage generator capable of preventing latch-up is disclosed. The voltage generator includes a positive charge pump unit, a negative charge pump unit, a second stage charge pump unit, and a control unit. The positive charge pump unit is utilized for generating a positive charge pump voltage according to a first enable signal. The negative charge pump is utilized for generating a negative charge pump voltage according to a second enable signal. The second stage charge pump unit is utilized for generating a gate-on voltage and a gate-off voltage according to a third enable signal and a fourth enable signal. The control unit is utilized for generating the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal and make the second stage charge pump unit generate the gate-on voltage (or the gate-off voltage) in a successively-increasing (or decreasing) manner. | 01-06-2011 |
Guan-Hua Tu, Tainan County TW
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20090161663 | METHOD AND SYSTEM FOR SERVERLESS VOIP SERVICE IN PERSONAL COMMUNICATION NETWORK - Method and system for supporting serverless VoIP service are provided. Network information of a first device and a second device is exchanged through a telecommunication network. A VoIP connection between the first and second devices can be established through an internet based network according to the exchanged network information. The network information may comprise an IP address and a port number, and can be delivered by short message service. | 06-25-2009 |
Hsiang-Chien Tu, Taipei Hsien TW
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20110131418 | METHOD OF PASSWORD MANAGEMENT AND AUTHENTICATION SUITABLE FOR TRUSTED PLATFORM MODULE - A password management and authentication method suitable for an electronic device with a trusted platform module (TPM) is provided. An authentication code is automatically generated according to a TPM password, and the authentication code is stored into an authentication device selected by a user. The authentication device storing the authentication code is directly served as an electronic key of the TPM so that the user needs not to memorize any password and can access data or a hard disk (HD) encrypted by the TPM by simply connecting the authentication device to the electronic device. Thereby, it is very convenient to the user. | 06-02-2011 |
Hsiao-Hua Tu, Taipei Hsien TW
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20090312074 | ROTARY COVER MECHANISM FOR PORTABLE ELECTRONIC DEVICES - A rotary mechanism includes a base ( | 12-17-2009 |
Hsieh-Min Tu, Tainan TW
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20090026217 | Seasoning can structure - A seasoning can for holding and dispensing seasonings includes a shell to contain seasonings, and a slip-prevention layer adhered to at least a portion of an outer side of the shell; the shell has a smooth surface; the slip-prevention layer comprises a film made of rubber paint, and is made by means of spraying rubber paint on the outer side of the shell; the slip-prevention layer has a high frictional coefficient so as to increase friction between the slip-prevention layer and the user's hands/fingers. | 01-29-2009 |
20130048680 | QUANTITATIVE DISPENSER - A quantitative dispenser is disclosed. The quantitative dispenser includes a container body, a rod, a connection base, an elastic part, and a pressing element. The container body consists of a first space with an isolation ring and a second space. The rod is passed into the first space and the second space. One end of the rod in the first space is through the elastic part and is connected to the pressing element while the other end of the rod is with a pull part. A bottom of the first space is connected to the connection base and a bottom of the rod is inserted into a material discharge opening of the connection base so as to close the material discharge opening. By pressing and releasing the pressing element, a gap is formed between the rod and the material discharge opening and a constant amount of seasoning falls off. | 02-28-2013 |
Hsi-Ku Tu, Taipei Hsien TW
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20080253113 | Illumination assembly - An illumination assembly comprises a base and at least one illumination cell. The base comprises a supply circuit for supplying an external power after connecting to a power source. The illumination cell is optionally connected to the base or removed from thereof, and includes a power storage unit stored with a storage power, a discharging circuit, and a charging circuit, wherein the power storage unit is electrically connected to the discharging circuit and the charging circuit. When the illumination cell is removed from the base, the storage power released from the power storage unit drives the illumination cell projecting an illumination light beam via the discharging circuit. When the illumination cell is assembled to the base, the supply circuit is electrically connected to the discharging circuit and the charging circuit respectively, so that the external power can drive the illumination cell projecting the illumination light beam and charge the power storage unit simultaneously. | 10-16-2008 |
20090040758 | Lighting assembly - A lighting assembly is adapted to be connected to at least one conductive connection hole of an illumination device. The lighting assembly comprises at least one lighting cell and connection mechanism, wherein the lighting cell comprises a base, at least one electrical connector and a lighting unit. The electrical connector and the lighting unit are connected to the base, and electrically connected with each other. The lighting unit has a plurality of lighting circuits linearly arranged thereon, and one end of the connection mechanism is electrically connected to the electrical connector. When the lighting assembly only comprises one lighting cell, the other end of the connection mechanism is connected to the electrode connection hole; while when the lighting assembly comprises a plurality of said lighting cells, the other end of the connection mechanism is selectively connected to the conductive connection hole and the other electrical connector of the neighbor lighting cell. | 02-12-2009 |
Hsi-Ku Tu, Taichung City TW
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20090284933 | COMBINATION TYPE HEAT DISSIPATION MODULE - A combination type heat dissipation module applied to dissipate at least one heat source is disclosed. The combination type heat dissipation module comprises a heat dissipation base and a plurality of heat dissipation cells. A base heat conduction surface of the heat dissipation base is applied to connect the heat source, a plurality of assembling grooves are recessed from a base heat dissipation surface of the heat dissipation base, and a cell body of each heat dissipation cell has a cell heat dissipation surface. At least two of the heat dissipation cells are respectively assembled to at least two of the assembling grooves, and keep their cell heat dissipation surfaces being exposed from the base heat dissipation surface. | 11-19-2009 |
20100001654 | ILLUMINATION SYSTEM CAPABLE OF AUTOMATICALLY ADJUSTING ILLUMINATION DIRECTION ACCORDING TO HUMAN BODY'S SIGNAL - An illumination system comprises an illumination assembly, a human body's signal detecting unit, a processing unit and an illumination direction adjustment unit. The illumination assembly projects an illumination light beam along an illumination direction; the human body's signal detecting unit detects at least one human body's signal released from at least one user to accordingly generate an intensity signal; the processing unit receives the intensity signal and transmits an illumination direction adjustment signal according to the intensity signal; and the illumination direction adjustment unit receives the illumination direction adjustment signal to automatically adjust the illumination direction. | 01-07-2010 |
20110020961 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE ASSEMBLY - A method for manufacturing a light emitting diode (LED) assembly comprises the steps of: preparing a chip carrier comprising a carrier substrate, a P type electrode and an N type electrode, and arranging an LED chip onto the carrier substrate to electrically connect the LED chip with the P type electrode and the N type electrode; packaging the LED chip with a light-transmissible packaging gel and making the P type electrode and the N type electrode exposed to form a molded LED chip cell; preparing an arrangement carrier comprising a arrangement carrier substrate, a P type electrode plate and an N type electrode plate; forming an arrangement recess on the arrangement carrier substrate; and arranging the molded LED chip cell into the arrangement recess to make the P type electrode and the N type electrode electrically connect to the P type electrode plate and the N type electrode plate respectively. | 01-27-2011 |
Hsin Chieh Tu, Tai Pei City TW
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20090153732 | METHOD AND APPARATUS FOR ADAPTIVE SELECTION OF YC SEPARATION - A method for adaptive selection of YC separation is provided. While a video decoder is re-sampling, a frequency of a re-sampling signal and a pixel rate of an output signal have a fixed relation, which is used to determine if a sampling frequency of the signal is deviated. And, accordingly, an appropriate Y/C separation is selected and then performed to obtain a better image quality. | 06-18-2009 |
Hsin-Lung Tu, Xinzhuang City TW
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20090149762 | Apparatus for displaying the blood pressure value and method thereof - An apparatus for displaying the blood pressure and a method thereof are disclosed. The apparatus uses a blood-measuring unit for receiving an analog blood pressure signal; a photoplethysmography (PPG) signal measuring unit for receiving an analog PPG signal; an analog-to-digital converter for converting the analog blood pressure signal into a digital blood pressure signal and the analog PPG signal into a digital PPG signal; an input unit for generating a human data; a microprocessor unit for receiving the digital blood pressure signal, the digital PPG signal and the human data so as to generate a different value in response to the digital blood pressure signal and the digital PPG signal, and output a pulse wave velocity (PWV) signal in response to the operation of the different value and the human data; an LCD driving unit for outputting an first LCD driving voltage and a second LCD driving voltage respectively in response to the digital blood pressure signal and the pulse wave velocity (PWV) signal; an LCD unit for displaying the colors that correspond to the first LCD driving and the second LCD driving voltage respectively. | 06-11-2009 |
Hsiu-Wen Tu, Tanzih Township TW
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20090045476 | IMAGE SENSOR PACKAGE AND METHOD FOR FORMING THE SAME - An image sensor package is provided including a substrate; a sensor chip; a plurality of bond wires for connecting the sensor chip to the substrate at predetermined locations; a sensor housing on the substrate for substantially encompassing the sensor chip, the sensor housing having a through-hole cavity defining an optical glass (IR filter) seat, the sensor housing defining an upper surface and an edge surface thereof; an optical glass (IR filter) on the optical glass (IR filter) seat; an encapsulation material for substantially encapsulating the upper surface and edge surface of the sensor housing, a corresponding surface of the substrate adjacent the edge surface of the sensor housing, and the side edge of the optical glass (IR filter); wherein the sensor housing is provided with a gas-exit allowing possible high temperature gas to exit; the encapsulation material forms an upper surface which is substantially aligned with a top surface of the optical glass (IR filter); the encapsulation material forms an upper surface which is lower than a top surface of the optical glass (IR filter); the sensor housing defines a profile shape, the profile shape has at least a step-wise configuration for facilitating and accommodating flowing of the encapsulation material; the sensor housing has a bottom surface adhered to the substrate by an adhesive; and a slot is provided on the bottom surface of the sensor housing for accommodating the adhesive. | 02-19-2009 |
Hsiu-Wen Tu, Chu-Pei TW
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20110024862 | IMAGE SENSOR PACKAGE STRUCTURE WITH LARGE AIR CAVITY - The present invention discloses an image sensor package structure with a large air cavity. The image sensor package structure includes a substrate, a chip, a cover and a package material. The chip is combined with the substrate. A plastic sheet of the cover is adhered to the chip and a transparent lid of the cover is combined with the plastic sheet to provide a covering over a sensitization area of the chip so as to form an air cavity. The package material is arranged on the substrate and encapsulated around the chip and the cover. The plastic sheet having a predetermined thickness can increase the distance between the transparent lid and the chip to enlarge the air cavity. Thus, the image-sensing effect of the image sensor package structure can be improved and the ghost image problem resulting from multi-refraction and multi-reflection of light can be minimized. | 02-03-2011 |
20110241146 | MANUFACTURING METHOD AND STRUCTURE OF A WAFER LEVEL IMAGE SENSOR MODULE WITH PACKAGE STRUCTURE - The present invention discloses a manufacturing method and structure of a wafer level image sensor module with package structure. The structure of the wafer level image sensor module with package structure includes a semi-finished product, a plurality of solder balls, and an encapsulant. The semi-finished product includes an image sensing chip and a wafer level lens assembly. The encapsulant is disposed on lateral sides of the image sensing chip and the wafer level lens assembly. Also, the manufacturing method includes the steps of: providing a silicon wafer, dicing the silicon wafer, providing a lens assembly wafer, fabricating a plurality of semi-finished products, performing a packaging process, mounting the solder balls, and cutting the encapsulant. Accordingly, the encapsulant encapsulates each of the semi-finished products by being disposed on the lateral sides thereof. | 10-06-2011 |
20110241147 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method of the same. The manufacturing method includes the following steps: providing a silicon wafer, dicing the silicon wafer, providing a plurality of transparent lids, fabricating a plurality of semi-finished products, performing a packaging process, mounting solder balls, and cutting an encapsulant between the semi-finished products. The manufacturing method of the invention has the advantage of being straightforward, uncomplicated, and cost-saving. Thus, the wafer level image sensor package structure is lightweight, thin, and compact. To prevent the image sensor chip from cracking on impact during handling, the encapsulant will be arranged on the lateral sides of the semi-finished products during the packaging process. | 10-06-2011 |
20130149805 | METHOD FOR REDUCING TILT OF OPTICAL UNIT DURING MANUFACTURE OF IMAGE SENSOR - A method for reducing the tilt of an optical unit during manufacture of an image sensor includes the steps of: providing a semimanufacture of the image sensor, carrying out a preheating process, carrying out an adhesive application process, carrying out an optical unit mounting process, and carrying out a packaging process. Due to the preheating process, the semimanufacture will be subjected to a stabilized process environment during the adhesive application process and the optical unit mounting process, so as for the optical unit to remain highly flat once attached to the semimanufacture. The method reduces the chances of tilt and crack of the optical unit and thereby contributes to a high yield rate. | 06-13-2013 |
20140098287 | STRUCTURE AND MANUFACTURING METHOD FOR HIGH RESOLUTION CAMERA MODULE - The present invention discloses a structure and a manufacturing method for a high-resolution camera module, wherein the method includes the following steps: providing an image sensor wafer comprising multiple image sensor chips; performing inspection and defining if each image sensor chip is a good chip; disposing an optical cover on the image sensor chip defined as the good chip, wherein the optical cover faces a sensing area and does not cover conductive contacts; cutting the image sensor wafer to obtain the discrete image sensor chip covered with the optical cover; and disposing a first surface of the divided image sensor chip on a bottom surface of a ceramic substrate. The present invention can seal the high resolution camera module during early stage of the manufacturing process to improve the yield rate of the camera module, and downsize the camera module effectively. | 04-10-2014 |
Hsiu-Wen Tu, Chu-Pei City TW
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20110024610 | IMAGE SENSOR PACKAGE STRUCTURE - The present invention discloses an image sensor package structure. The image sensor package structure includes a substrate, a chip, a transparent lid, a first casing and a package material. The transparent lid covers a sensitization area of the chip and it also adheres to the chip which is deposed on the substrate. The first casing, which adheres to the transparent lid, forms an opening so that light can pass through the opening and the transparent lid to enter into the sensitization area. The package material covers around the chip and the transparent lid and fills between the substrate and the first casing. Because of the arrangement of adhesive layers placed between the first casing and the transparent lid and between the transparent lid and the chip, the blockage area from moisture is elongated. Therefore, the reliability of the image sensor package structure can be enhanced. | 02-03-2011 |
20110024861 | MANUFACTURING METHOD FOR MOLDING IMAGE SENSOR PACKAGE STRUCTURE AND IMAGE SENSOR PACKAGE STRUCTURE THEREOF - A manufacturing method for molding an image sensor package structure and the image sensor package structure thereof are disclosed. The manufacturing method includes following steps of providing a half-finished image sensor for packaging, arranging a dam on the peripheral of a transparent lid of the half-finished image sensor, positioning the half-finished image sensor within a mold, and injecting a mold compound into the mold cavity of the mold. The dam is arranged on the top surface of the transparent lid and the inner surface of the mold can exactly contact with the top surface of dam so that the mold compound injected into the mold cavity is prevented from overflowing to the transparent lid by the dam. Furthermore, the arrangement of the dam and the mold compound can increase packaged areas and extend blockage to invasive moisture so as to enhance the reliability of the image sensor package structure. | 02-03-2011 |
Hsiu-Wen Tu, Hsin-Chu Hsien TW
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20110156187 | IMAGE SENSOR PACKAGING STRUCTURE WITH PREDETERMINED FOCAL LENGTH - An image sensor packaging structure with a predetermined focal length is provided. The image sensor packaging structure includes a substrate, a chip, an optical assembly, and an encapsulation compound. The chip has a sensitization area and is coupled to the substrate. Conductive contacts on the substrate are electrically connected with conductive contacts around the sensitization area. The optical assembly has the predetermined focal length and is disposed above the chip so as to form an air cavity between the optical assembly and the sensitization area of the chip. The encapsulation compound is formed on the substrate to surround the chip and the optical assembly. With the above stated structure, not only can the focus adjusting procedure be dispensed with, but also the image sensor packaging structure can be manufactured by a molding or dispensing process. | 06-30-2011 |
20110156188 | IMAGE SENSOR PACKAGING STRUCTURE WITH LOW TRANSMITTANCE ENCAPSULANT - An image sensor packaging structure with a low transmittance encapsulant is provided. The image sensor packaging structure includes a substrate, a chip, a transparent lid, and the low transmittance encapsulant. The chip is combined with the substrate. The transparent lid is adhered to the chip and cover above a sensitization area of the chip to form an air cavity. The low transmittance encapsulant is formed on the substrate and encapsulates the chip and the transparent lid so as to accomplish the package of the image sensor packaging structure. Due to the feature of prohibiting from light passing through the low transmittance encapsulant, the arrangement of the low transmittance encapsulant can avoid the light from outside interfere the image sensing effect of the image sensor. Therefore, the quality of the image sensing can be ensured. | 06-30-2011 |
20110279815 | MANUFACTURING METHOD AND STRUCTURE FOR WAFER LEVEL IMAGE SENSOR MODULE WITH FIXED FOCAL LENGTH - This present invention discloses a manufacturing method and structure for a wafer level image sensor module with fixed focal length. The method includes the following steps. First, a silicon wafer comprising several image sensor chips having a photosensitive area and a lens module array wafer comprising several wafer level lens modules with fixed focal length are provided. Next, the image sensor chips and the wafer level lens modules are sorted in grades according to the different quality grades. According to the sorting results, each of the wafer level lens modules is assigned to be situated above the image sensor chip that has the same grade. At the same time, each of the wafer level lens modules is directed to face the photosensitive area of each image sensor chip. Finally, in the packaging process, the wafer level lens module is surrounded by an encapsulation material. | 11-17-2011 |
20110291215 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method for the same. The manufacturing method includes the following steps: providing a silicon wafer with image sensor chips, providing a plurality of transparent lids, allotting one said transparent lid on top of the corresponding image sensor chip, and carrying out a packaging process. The manufacturing method of the invention has the advantage of having a simpler process, lower cost, and higher production yield rate. The encapsulation compound arranges on the first surface of the image sensor chip and covers the circumference of the transparent lid to avoid the side light leakage as traditional chip scale package (CSP). Thus, the sensing performance of the wafer level image sensor packaging structure can be enhanced. | 12-01-2011 |
20120068288 | MANUFACTURING METHOD OF MOLDED IMAGE SENSOR PACKAGING STRUCTURE WITH PREDETERMINED FOCAL LENGTH AND THE STRUCTURE USING THE SAME - A manufacturing method of a molded image sensor packaging structure with a predetermined focal length and the structure using the same are disclosed. The manufacturing method includes: providing a substrate; providing a sensor chip disposed on the substrate; providing a lens module set over the sensing area of the chip to form a semi-finished component; providing a mold that has an upper mold member with a buffer layer; disposing the semi-finished component into the mold to form a mold cavity therebetween; injecting a molding compound into the mold cavity; and after transfer molding the molding compound, opening the mold and performing a post mold cure process to cure the molding compound. The buffer layer can fill the air gap between the upper surface of the lens module and the upper mold member, thereby preventing the upper surface of the lens module from being polluted by the molding compound. | 03-22-2012 |
Huang-Yao Tu, Kaohsiung City TW
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20110039922 | 18beta-GLYCYRRHETINIC ACID DERIVATIVES AND SYNTHETIC METHOD THEREOF - The present invention provides a chemical compound having the structure being one selected from a group consisting of | 02-17-2011 |
20110190388 | URSOLIC ACID DERIVATIVE AND PHARMACEUTICAL COMPOSITION THEREOF - Several ursolic acid derivatives and pharmaceutical compositions thereof are provided. The ursolic acid derivatives and the pharmaceutical compositions thereof have at least one of an anticancer and an anti-inflammatory effects. A method for increasing a reactive oxygen species in a cell is also provided. The method comprises a step of providing the cell with a pharmaceutical composition including an ursolic acid derivative. | 08-04-2011 |
20110306775 | SYNTHESIS AND BIOLOGICAL EVALUATION OF 2',5'-DIMETHOXYCHALCONE DERIVATIVES AS MICROTUBULE-TARGETED ANTICANCER AGENTS - Disclosed are a serious of 2′,5′-dimethoxychalcone derivatives for treating cancer, wherein 2,5-dimethoxyacetophenone and methyl 4-formylbenzoate are condensed to form 4-carboxyl-2′,5′-dimethoxychalcone (compound 1), which is further reacted with alkyl halides or amines to synthesize the chalcone derivatives of compounds 2-17. In addition, 2,5-dimethoxyacetophenone is reacted with 5-formyl-2-thiophenecarboxylic acid to form compound 18 (3-(3-thiophene)carboxyl-1-(2,5-dimethoxyphenyl)prop-2-en-1-one). The synthesized 2′,5′-dimethoxychalcone derivatives can be acted as microtubule-targeted tubulin-polymerizing agents. | 12-15-2011 |
20130072694 | 18 -GLYCYRRHETINIC ACID DERIVATIVES AND SYNTHETIC METHOD THEREOF - The present invention provides a chemical compound having the structure being one selected from a group consisting of | 03-21-2013 |
Hung-Jung Tu, Hualien TW
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20100117226 | STRUCTURE AND METHOD FOR STACKED WAFER FABRICATION - A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages. | 05-13-2010 |
20100140767 | Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film. | 06-10-2010 |
20100171203 | Robust TSV structure - A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure. | 07-08-2010 |
20100330743 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 12-30-2010 |
20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110186967 | Component Stacking Using Pre-Formed Adhesive Films - A method of forming integrated circuits includes laminating a patterned film including an opening onto a wafer, wherein a bottom die in the wafer is exposed through the opening. A top die is placed into the opening. The top die fits into the opening with substantially no gap between the patterned film and the top die. The top die is then bonded onto the bottom die, followed by curing the patterned film. | 08-04-2011 |
20120032348 | THREE-DIMENSIONAL INTEGRATED CIRCUITS WITH PROTECTION LAYERS - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 02-09-2012 |
20120104578 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 05-03-2012 |
20120187576 | Three-Dimensional Integrated Circuits with Protection Layers - A semiconductor structure includes a first die comprising a first substrate and a first bonding pad over the first substrate, a second die having a first surface and a second surface opposite the first surface, wherein the second die is stacked on the first die and a protection layer having a vertical portion on a sidewall of the second die, and a horizontal portion extending over the first die. | 07-26-2012 |
20120238057 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 09-20-2012 |
20120289062 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 11-15-2012 |
20130133688 | WAFER DEBONDING AND CLEANING APPARATUS AND METHOD OF USE - This description relates to a wafer debonding and cleaning apparatus including an automatic wafer handling module. The automatic wafer handling module loads a semiconductor wafer into a wafer debonding module for a debonding process. The automatic wafer handling module removes the semiconductor wafer from the debonding module and loads the semiconductor wafer into a wafer cleaning module for a cleaning process. | 05-30-2013 |
20140130962 | THIN WAFER HANDLING METHOD - A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer. | 05-15-2014 |
20140261997 | Selective Curing Method of Adhesive on Substrate - Embodiments of the present disclosure include methods of forming a semiconductor device. An embodiment is a method for forming a semiconductor device, the method including applying a substrate to a carrier with an adhesive layer between the carrier and the substrate, curing a portion of the adhesive layer, the cured portion surrounding an uncured portion of the adhesive layer, removing the carrier from adhesive layer, removing the uncured portion of the adhesive layer, and removing the cured portion of the adhesive layer. | 09-18-2014 |
20140374031 | WAFER DEBONDING AND CLEANING APPARATUS AND METHOD - A wafer debonding and cleaning apparatus comprises a wafer debonding module configured to separate a semiconductor wafer from a carrier wafer. The wafer debonding and cleaning apparatus also comprises a first wafer cleaning module configured perform a first cleaning process to clean a surface of the semiconductor wafer. The wafer debonding and cleaning apparatus further comprises an automatic wafer handling module configured to transfer the semiconductor wafer from one of the wafer debonding module or the first wafer cleaning module to the other of the wafer debonding module or the first wafer cleaning module. The semiconductor wafer has a thickness ranging from about 0.20 μm to about 3 mm. | 12-25-2014 |
Hung-Sen Tu, Taishan Township TW
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20090309448 | END COVER AND MOTOR ROTOR HAVING THE END COVER - An end cover adapted to engage with an end surface of a spindle of a motor rotor is proposed for securely coupling to the spindle with a plurality of permanent magnets disposed around the peripheral wall of the spindle. The end cover has a first surface facing an end surface of the spindle and an second surface opposing to the first surface, which is formed with a plurality of inserting slots indentedly disposed around the rim thereof and corresponding to the permanent magnets for coupling the ends of the permanent magnets, thereby securely fastening each of the permanent magnets to the spindle of the motor rotor. Further, the present invention further provides a motor rotor having the end covers described above. | 12-17-2009 |
Jhih-Ming Tu, Hsi Chih City TW
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20100159751 | USB CONNECTOR AND CONTACT ARRAY THEREOF - Disclosed herein is a contact array of a universal serial bus (USB) connector including a first signal differential pair, a second signal differential pair and a third signal differential pair, wherein the second signal differential pair is disposed between the first and third signal differential pairs, and at least one power contact or ground contact is disposed between the first and second signal differential pairs, or between the second and third signal differential pairs. | 06-24-2010 |
Jia-Jin Tu, Chu-Nan TW
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20090121986 | DISPLAY APPARATUS WITH SOLID STATE LIGHT EMITTING ELEMENTS - A display apparatus includes a display system and a control system. The display system includes pixel units and a network interface based on a network protocol. The pixel units are arranged in a matrix and each of the pixel units includes solid state light emitting elements. The control system includes a control module, an input module, and an output module. The output module is electronically coupled to the network interface. The control system is configured to receive an input signal through the input module, generate a corresponding control signal by the control module, and output the control signal by the output module to the display system via the network interface according to the network protocol to control the display contents of the display system. | 05-14-2009 |
20090213585 | LIGHT EMITTING DIODE DISPLAY DEVICE - A light emitting diode display device includes a circuit board and a plurality of pixel units. Each pixel unit includes a light emitting diode assembly positioned on and electrically connected to the circuit board, and a light-mixed component positioned on a side of the light emitting diode assembly configured for mixing lights emitted from the light emitting diode assembly to generate a mixed light beam. | 08-27-2009 |
Jih-Sheng Tu, Yilan County TW
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20100166082 | METHOD FOR PACKING BITSTREAM OF SCALABLE VIDEO CODING - A method for packing a bitstream of scalable video coding (SVC) is provided. The method includes the following steps. First, a SVC bitstream is obtained, wherein the SVC bitstream has a plurality of frames, and each of the frames has a base layer and a plurality of enhancement layers. Next, complexity of the frames is analyzed according to the features of a bitstream parameter of the SVC bitstream. Next, the base layers of the frames are selectively packed to form a base layer packet according to the complexity of the frame. Thereafter, the remainder of the SVC bitstream is packed to form a plurality of enhancement layers according to a packing mechanism of the base layer packet. | 07-01-2010 |
20110145265 | Video search method using motion vectors and apparatus thereof - A video search method and an apparatus thereof are provided. In the video search method, the bit streams of a query video file and a plurality of video files to be searched are parsed to obtain a plurality of corresponding motion vectors (MVs). A plurality of corresponding MV maps is constructed in a time domain according to the MVs. Correlations are obtained according to the MV map corresponding to the query video file and the MV maps corresponding to the video files, and a video search result is obtained according to the correlations. | 06-16-2011 |
20110225136 | VIDEO SEARCH METHOD, VIDEO SEARCH SYSTEM, AND METHOD THEREOF FOR ESTABLISHING VIDEO DATABASE - A video search method including following steps is provided. Meta-data of a query clip is received, wherein the meta-data includes an index tag and a semantic pattern. One or more candidate clips are retrieved from at least one video database according to the index tag. The semantic pattern is compared with a semantic pattern of each of the candidate clips, and each of the candidate clips is marked as a returnable video clip or a non-returnable video clip according to a comparison result. The candidate clips marked as the returnable video clip are served as a query result matching the query clip. A video search system and a method for establishing a video database are also provided. | 09-15-2011 |
20120317275 | METHODS AND DEVICES FOR NODE DISTRIBUTION - Methods for node distribution in a P2P network system and include the steps of: mapping nodes to a numerical space respectively, wherein each node has a neighborhood table recorded a certain number of nodes and the certain number of nodes are close to the node along one of two sides in increasing and decreasing direction; performing a search process to find a plurality of reference nodes, wherein any two consecutive reference nodes are a first reference node and a second reference node, and the second reference node is the node in the neighborhood table of the first reference node and a distance between the second and the first reference node conforms to a predetermined condition; finding two positioning reference nodes; mapping a target node to a target value, and locating the target node in a position corresponding to the target value and informing the reference nodes of the position. | 12-13-2012 |
20130141531 | COMPUTER PROGRAM PRODUCT, COMPUTER READABLE MEDIUM, COMPRESSION METHOD AND APPARATUS OF DEPTH MAP IN 3D VIDEO - A compression method and apparatus of depth map in a 3D video are provided. The compression apparatus includes an edge detection module, a homogenizing module, and a compression encoding module. An edge detection is performed on a depth map of a frame in the 3D video. When at least one macroblock in the frame with no object edge passing through is found, a homogenizing processing is performed on the at least one macroblock. And then the depth map is encoded. Therefore, data quantity might be decreased when the depth map is compressed and encoded according to the present disclosure. | 06-06-2013 |
20140146134 | METHOD AND SYSTEM FOR ENCODING 3D VIDEO - A method and system for encoding three-dimensional (3D) video are provided. The method includes: obtaining a depth map of the 3D video, wherein the depth map includes multiple pixels and each of the pixels has a depth value; identifying a first contour of an object in the depth map; changing the depth values according to whether the pixels are located on the first contour to generate a contour bit map; compressing the contour bit map to generate a first bit stream, and decompressing the first bit stream to generate a reconstructed contour bit map; obtaining multiple sampling pixels of the pixels in the object according to a second contour corresponding to the object in the reconstructed contour bit map; and, encoding locations and the depth values of the sampling pixels. Therefore, a compression ratio of the 3D video is increased. | 05-29-2014 |
Jin-Tong Tu, Chiayi City TW
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20100201142 | Telescopic Clipping Apparatus - A telescopic clipping apparatus includes a handle, a lever, a telescopic unit, a clipping unit, a reel, a pulley and a cable. The lever is movably connected to the handle. The telescopic unit is connected to the handle. The clipping unit is pivotally connected to the telescopic unit. A reel is located in the telescopic unit. A pulley is connected to the clipping unit. The cable is wound around the pulley, and includes a first end tied to the lever and a second end tied to the reel. | 08-12-2010 |
Kao- Way Tu, Jhonghe TW
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20100171171 | Trench mosfet device with low gate charge and the manfacturing method thereof - A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased. | 07-08-2010 |
Kou-Way Tu, Zhonghe City TW
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20100155840 | POWER MOSFET AND FABRICATING METHOD THEREOF - A power MOSFET is disclosed. In the power MOSFET, an epitaxial layer doped with dopants of a first conduction type is formed on a substrate. A first trench extends downward from a first region of the top surface of the epitaxial layer, and a second trench extends downward from the bottom of the first trench. The width of the second trench is smaller than that of the first trench. The first well is located adjacent to the bottom of the first trench and the bottom of the second trench, and is doped with dopants of a second conduction type. The second well extends downward from a second region of the top surface and is doped with dopants of the second conduction type. The first well and the second well are separated. A source region doped with dopants of the first conduction type is formed in the second well. | 06-24-2010 |
Kuo-Chiang Tu, Taoyuan Hsien TW
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20090244900 | ILLUMINATING DEVICE AND HEAT-DISSIPATING STRUCTURE THEREOF - The present invention provides an illuminating device and heat-dissipating structure thereof. The heat-dissipating structure includes a plurality of heat-dissipating units stacked together. Each heat-dissipating unit includes a cone-like portion with an opening and a plurality of protrusions connected to the cone-like portion, wherein at least one of the protrusions of one heat-dissipating unit is coupled to that of the adjacent heat-dissipating unit to form one or more zonal planes for allowing a light source to be disposed thereon to constitute the illuminating device, and the openings of the heat-dissipating units are liked together to form an airflow passage. | 10-01-2009 |
20090296411 | ILLUMINATING DEVICE AND HEAT-DISSIPATING STRUCTURE THEREOF - The present invention provides an illuminating device and heat-dissipating structure thereof. The heat-dissipating structure includes at least one thermally conductive element and a plurality of heat-dissipating units stacked together. Each heat-dissipating unit includes a cone-like fin with an opening and a plurality of protrusions connected to the cone-like fin, wherein at least one of the protrusions of one heat-dissipating unit is coupled to that of the adjacent heat-dissipating unit to form one or more zonal planes for allowing one end of the thermally conductive element to be disposed thereon, and the other end of the thermally conductive element is connected with a heat source to constitute the illuminating device. | 12-03-2009 |
Li-Shu Tu, Taoyuan County TW
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20090101880 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary memory device includes a first dielectric layer with a first conductive contact therein. A phase change material (PCM) is disposed on top of the first dielectric layer and provided with an insulating layer integrally on a top surface of the PCM. A first electrode is disposed over the first dielectric layer and covered a portion of the first conductive contact and the insulating layer in a first direction, contacting to the first conductive contact and a first side of the PCM. A second electrode is disposed over the first dielectric layer and covered a portion of the insulating layer in a second direction, contacting to a second side of the PCM. A second dielectric layer is disposed over the first dielectric layer to cover the first electrode, the second electrode, the insulating layer and the PCM, including a second conductive contact connected to the second electrode. | 04-23-2009 |
20090101884 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer and electrically connected to the first conductive electrode. A space is disposed in the second dielectric layer to at least isolate a sidewall of the phase change material layer and the second dielectric layer adjacent thereto. A second conductive electrode is disposed in the second dielectric layer and electrically connected to the phase change material layer. | 04-23-2009 |
20100163828 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer. | 07-01-2010 |
Ming-Chang Tu, Tao Yuan Shien TW
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20080220599 | Method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices - A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity. | 09-11-2008 |
Po-Min Tu, Hukou TW
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20100096616 | LIGHT-EMITTING AND LIGHT-DETECTING OPTOELECTRONIC DEVICE - An exemplary optoelectronic device includes a substrate and an epitaxial structure formed on the optoelectronic device. The epitaxial structure includes an N-type semiconductor layer, a P-type semiconductor layer, a multi-quantum-well layer and an undoped semiconductor layer. The multi-quantum-well layer is arranged between the N-type semiconductor layer and the P-type semiconductor layer. The undoped semiconductor layer is sandwiched between the N-type semiconductor layer and the multi-quantum-well layer. The undoped semiconductor layer is represented by a general formula Al | 04-22-2010 |
20110114983 | PHOTOELECTRIC DEVICE HAVING GROUP III NITRIDE SEMICONDUCTOR - A photoelectric device having Group III nitride semiconductor includes a conductive layer, a metallic mirror layer located on the conductive layer, and a Group III nitride semiconductor layer located on the metallic mirror layer. The Group III nitride semiconductor layer defines a number of microstructures thereon. Each microstructure includes at least one angled face, and the angled face of each microstructure is a crystal face of the Group III nitride semiconductor layer. | 05-19-2011 |
20110163295 | SEMICONDUCTOR WITH LOW DISLOCATION - A semiconductor includes a semiconductor layer, a plurality of recesses and a blocking layer. The recesses are formed on a surface of the semiconductor layer by etching fragile locations of the semiconductor layer where dislocation occurs. The blocking layer is filled in each recess. The semiconductor further includes a re-epitaxial semiconductor layer grown from a surface of the semiconductor layer without the covering of blocking layer, and the re-epitaxial semiconductor layer laterally overgrows toward areas of the recesses for overlaying the blocking layer. | 07-07-2011 |
20110266552 | LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF - A light emitting element includes a substrate, a GaN layer formed on the substrate, a first low refractive index semiconductor layer formed on the GaN layer, and a lighting structure having a high refractive index formed on the first low refractive index semiconductor layer. A second low refractive index semiconductor layer is embedded in the first low refractive index semiconductor layer. The first low refractive index semiconductor layer and the GaN layer exhibit a lattice mismatch therebetween. | 11-03-2011 |
20110278613 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, a buffer layer on the substrate, a patterned layer having a first reflective index on the buffer layer, a semiconductor layer having a second reflective index on the patterned layer, and an illumination structure on the semiconductor layer. A method for manufacturing the light emitting diode is also provided. | 11-17-2011 |
20110291121 | LIGHT EMITTING ELEMENT PACKAGE - A light emitting element package includes a substrate, at least two light emitting element modules and an encapsulation member. The substrate includes a circuit layer. The circuit layer includes a plurality of solder pads. The at least two light emitting element modules are mounted on the substrate. Each of the at least two light emitting element modules includes a plurality of light emitting elements. Each light emitting element of the at least two light emitting element modules is electrically coupled to neighboring light emitting element in serial through the solder pads. The at least two light emitting element modules are reversely arranged. The encapsulation member is configured to encapsulate the at least two light emitting element modules on the substrate. | 12-01-2011 |
20120001303 | SEMICONDUCTOR STRUCTURE HAVING LOW THERMAL STRESS AND METHOD FOR MANUFACTURING THEREOF - A semiconductor structure includes a Si substrate, a supporting layer and a blocking layer formed on the substrate and an epitaxy layer formed on the supporting layer. The supporting layer defines a plurality of grooves therein to receive the blocking layer. The epitaxy layer is grown from the supporting layer. A plurality of slots is defined in the epitaxy layer and over the blocking layer. The epitaxy layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer. A method for manufacturing the semiconductor structure is also disclosed. | 01-05-2012 |
20120018847 | GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. | 01-26-2012 |
20120074531 | EPITAXY SUBSTRATE - An epitaxy substrate for growing a plurality of semiconductor epitaxial layers thereon, includes a plurality of growth areas and a plurality of protected areas. The growth areas are provided for growing the semiconductor epitaxial layers thereon. The growth areas and the protected areas are alternating. A thickness of the growth areas is less than ⅓ of a thickness H of the protected areas. | 03-29-2012 |
20120086032 | SEMICONDUCTOR LIGHT-EMITTING STRUCTURE HAVING LOW THERMAL STRESS - A semiconductor light-emitting structure includes a silicon substrate, a distributed Bragg reflector, a semiconductor structures layer and an epitaxy connecting layer. The silicon substrate has a top surface. The distributed Bragg reflector is formed on the top surface of the silicon substrate. The semiconductor structures layer is configured for emitting light. The epitaxy connecting layer is placed between the distributed Bragg reflector and the semiconductor structures layer. Grooves extend from the semiconductor structures layer through the epitaxy connecting layer and the distributed Bragg reflector to reach the semiconductor structures layer. | 04-12-2012 |
20120097976 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode chip includes an electrically conductive substrate, a reflecting layer disposed on the substrate, a semiconductor structure formed on the reflecting layer, an electrode disposed on the semiconductor structure, and a plurality of slots extending through the semiconductor structure. The semiconductor structure includes a P-type semiconductor layer formed on the reflecting layer, a light-emitting layer formed on the P-type semiconductor layer, and an N-type semiconductor layer formed on the light-emitting layer. A current diffusing region is defined in the semiconductor structure and around the electrode. The slots are located outside the current diffusing region. | 04-26-2012 |
20120100648 | METHOD FOR MANUFACTURING LIGHT EMITTING CHIP - A method for manufacturing light emitting chips includes steps of: providing a substrate having a plurality of separate epitaxy islands thereon, wherein the epitaxy islands are spaced from each other by channels; filling the channels with an insulation material; sequentially forming a reflective layer, a transition layer and a base on the insulation material and the epitaxy islands; removing the substrate and the insulation material to expose the channels; and cutting the reflective layer, the transition layer and the base to form a plurality of individual chips along the channels. | 04-26-2012 |
20120100656 | METHOD FOR MAKING A SOLID STATE SEMICONDUCTOR DEVICE - A method for making a solid state semiconductor device includes: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer; forming a surface-textured second epitaxial layer on the first epitaxial layer by chemical vapor deposition; and forming a solid state stacked layer structure having a PN-junction type light-emitting part on a textured surface of the second epitaxial layer. | 04-26-2012 |
20120142133 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHTING CHIP - A method for fabricating a semiconductor lighting chip includes steps of providing a substrate with an epitaxial layer thereon. The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer successively grown on the substrate. The epitaxial layer has dislocation defects traversing the first semiconductor layer, the active layer and the second semiconductor layer. The epitaxial layer is then subjected to an etching process which remove parts of the second semiconductor layer and the active layer along the dislocation defects to form recesses recessing from the second semiconductor layer to the active layer. Thereafter a first electrode and a second electrode are formed on the first semiconductor layer and the second semiconductor layer, respectively. | 06-07-2012 |
20120153332 | EPITAXIAL STRUCTURE OF AN LED AND MANUFACTURING METHOD THEREOF - An epitaxial structure of a light emitting diode (LED) includes a substrate, an epitaxial layer, and a light capturing microstructure. The substrate has a top surface. The epitaxial layer is grown on the top surface of the substrate and has a P-type semiconductor layer, an active layer, and an N-type semiconductor layer in sequence. The light capturing microstructure is positioned on an upper portion of the epitaxial layer which is distant from the substrate. A manufacturing method of an epitaxial structure of an LED is also disclosed. The light capturing microstructure includes at least a concave and an insulating material filled in the at least a concave. | 06-21-2012 |
20120156815 | METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP - A method for fabricating an LED chip includes: providing a sapphire substrate with a SiO | 06-21-2012 |
20120164764 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHTING CHIP - A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate with a first block layer dividing an upper surface of the substrate into a plurality of epitaxial regions; forming a first semiconductor layer on the epitaxial regions; forming a second block layer partly covering the first semiconductor layer; forming a lighting structure on an uncovered portion of the first semiconductor layer; removing the first and the second block layers thereby defining clearances at the bottom surfaces of the first semiconductor layer and the lighting structure; and permeating etching solution into the first and second clearances to etch the first semiconductor layer and the lighting structure, thereby to form each of the first semiconductor layer and the lighting structure with an inverted frustum-shaped structure. | 06-28-2012 |
20120164773 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHTING CHIP - A method for fabricating a semiconductor lighting chip includes steps of: providing a substrate; forming a first etching layer on the substrate; forming a connecting layer on the first etching layer; forming a second etching layer on the connecting layer; forming a lighting structure on the second etching layer; and etching the first etching layer, the connecting layer, the second etching layer and the lighting structure, wherein an etching rate of the first etching layer and the second etching layer is lager than that of the connecting layer and the lighting structure, thereby to form the connecting layer and the lighting structure each with an inverted frustum-shaped structure. | 06-28-2012 |
20120168797 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting diode chip, comprising steps: providing a substrate with a first patterned blocking layer formed thereon; growing a first n-type semiconductor layer on the substrate between the constituting parts of first patterned blocking layer, and stopping the growth of the first n-type semiconductor layer before the first n-type semiconductor layer completely covers the first patterned blocking layer; removing the first patterned blocking layer, whereby a plurality of first holes are formed at position where the first patterned blocking layer is originally existed; continuing the growth of the first n-type semiconductor layer until the first holes are completely covered by the first n-type semiconductor layer; and forming an active layer and a p-type current blocking layer on the first n-type semiconductor layer successively. | 07-05-2012 |
20120171791 | METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP - A method for fabricating an LED chip is provided. Firstly, a SiO | 07-05-2012 |
20120175628 | LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An exemplary LED includes an electrode layer, an LED die, a transparent electrically conductive layer, and an electrically insulating layer. The electrode layer includes a first section and a second section electrically insulated from the first section. The LED die is arranged on and electrically connected to the second section of the electrode layer. The transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. The electrically insulating layer is located between the LED die and the transparent electrically conductive layer to insulate the transparent electrically conductive layer from the second section of the electrode layer. | 07-12-2012 |
20120175630 | LIGHT EMITTING DIODES AND METHOD FOR MANUFACTURING THE SAME - An LED comprises an electrode layer comprising a first a second sections electrically insulated from each other; an electrically conductive layer on the second section, an electrically conductive pole protruding from the electrically conductive layer; an LED die comprising an electrically insulating substrate on the electrically conductive layer, and a P-N junction on the electrically insulating substrate, the P-N junction comprising a first electrode and a second electrode, the electrically conductive pole extending through the electrically insulating substrate to electrically connect the first electrode to the second section; a transparent electrically conducting layer on the LED die, the transparent electrically conducting layer electrically connecting the second electrode to the first section; and an electrically insulating layer between the LED die, the electrically conductive layer, and the transparent electrically conducting layer, wherein the electrically insulating layer insulates the transparent electrically conducting layer from the electrically conductive layer and the second section. | 07-12-2012 |
20120175646 | LIGHT EMITTING DIODE MODULE - An LED module includes a base, a circuit layer formed on the base and multiple LEDs each having an LED die connecting to the circuit layer. The circuit layer includes multiple connecting sections. Each connecting section includes a first connecting part and a second connecting part electrically insulating and spaced from each other. Each LED includes an electrode layer having a first section and a second section electrically insulated from the first section and respectively electrically connecting the first and second connecting parts of a corresponding connecting section. The LED die is electrically connected to the second section. A transparent electrically conductive layer is formed on the LED die and electrically connects the LED die to the first section of the electrode layer. An electrically insulating layer is located between the LED die and surrounding the LED die except where the transparent electrically conductive layer connects. | 07-12-2012 |
20120190141 | METHOD FOR MANUFACTURING POLYCHROMATIC LIGHT EMITTING DIODE DEVICE HAVING WAVELENGTH CONVERSION LAYER MADE OF SEMICONDCUTOR - A method for manufacturing a polychromatic light emitting diode device, comprising steps of providing an epitaxial substrate and forming a multiple semiconductor layer on the epitaxial substrate, wherein the multiple semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer and an active layer. The active layer emits light of a first wavelength. Thereafter a first wavelength conversion layer is formed on the multiple semiconductor layer. The first wavelength conversion layer is made of semiconductor and absorbs a portion of the light of a first wavelength and emits light of a second wavelength, wherein the second wavelength is longer than the first wavelength. | 07-26-2012 |
20120196391 | METHOD FOR FABRICATING SEMICONDUCTOR LIGHTING CHIP - A method for fabricating a semiconductor lighting chip includes steps: providing a substrate with an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a second semiconductor layer and an active layer located between the first semiconductor layer and the second semiconductor layer; dipping the epitaxial layer into an electrolyte to etch surfaces of the epitaxial layer and form a number of holes on the epitaxial layer; and forming electrodes on the epitaxial layer. | 08-02-2012 |
20120205690 | GROUP III-NITRIDE BASED SEMICONDUCTOR LED - A group III-nitride based semiconductor LED includes a sapphire substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer grown sequentially on the sapphire substrate. An n-type strain lattice structure is arranged between the n-type semiconductor layer and the active layer. A lattice constant of the n-type strain lattice structure exceeds that of the active layer, and is less than that of the n-type semiconductor layer. | 08-16-2012 |
20120211771 | LED EPITAXIAL STRUCTURE AND MANUFACTURING METHOD - An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein. | 08-23-2012 |
20120261696 | LIGHT EMITTING DIODE EPITAXIAL STRUCTURE AND MANUFACTURING METHOD THEREOF - A light emitting device (LED) epitaxial structure includes a substrate, a nitride semiconductor layer, a patterned oxide total-reflective layer, a first-type semiconductor layer, an active layer and a second-type semiconductor layer. The nitride semiconductor layer is formed on the substrate. The patterned oxide total-reflective layer is formed on the nitride semiconductor layer. An upper surface of the nitride semiconductor layer is partially exposed out from the oxide total-reflective layer. The first-type semiconductor layer is arranged on the exposed upper surface of the nitride semiconductor layer and covers the oxide total-reflective layer. The active layer is arranged on the first-type semiconductor layer. The second-type semiconductor layer is arranged on the active layer. | 10-18-2012 |
20120273830 | LIGHT EMITTING DIODE CHIP AND METHOD OF MANUFACTURING THE SAME - An LED chip includes a substrate, a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first electrode and a second electrode formed on the substrate in sequence. A surface of the first type semiconductor layer away from the substrate comprises an exposed first area and a second area covered by the light-emitting layer. The first electrode is formed on the exposed first area of the substrate. A number of recesses are defined in the second area of the surface of the first type semiconductor layer. The recesses are spaced apart from each other and arranged in sequence in a direction away from the first electrode; depths of the recesses gradually decrease following an increase of a distance between the recesses and the first electrode. The second electrode is formed on the second type semiconductor layer. | 11-01-2012 |
20130001508 | LIGHT EMITTING DIODE - An LED comprises a substrate, a buffer layer, an epitaxial layer and a conductive layer. The epitaxial layer comprises a first N-type epitaxial layer, a second N-type epitaxial layer, and a blocking layer with patterned grooves sandwiched between the first and second N-type epitaxial layers. The first and second N-type epitaxial layers make contact each other via the patterned grooves. Therefore, the LED enjoys a uniform current distribution and a larger light emitting area. A manufacturing method for the LED is also provided. | 01-03-2013 |
20130032779 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) comprises a substrate, an epitaxial layer and an aluminum nitride (AlN) layer sequentially disposed on the substrate. The AlN layer comprises a plurality of stacks separated from each other, wherein the epitaxial layer entirely covers the plurality of stacks of the AlN layer. The AlN layer with a plurality of stacks reflects upwardly light generated by the epitaxial layer and downwardly toward the substrate to an outside of LED through a top plan of the LED. A method for forming the LED is also disclosed. | 02-07-2013 |
20130119421 | LIGHT EMITTING DIODE EPITAXIAL STRUCTURE AND MANUFACTURING METHOD OF THE SAME - An LED epitaxial structure includes a substrate, a buffer layer, a functional layer and a light generating layer. The buffer layer is located on a top surface of the substrate. The functional layer includes a plurality of high-temperature epitaxial layers and low-temperature epitaxial layers alternatively arranged between the buffer layer and light generating layer. A textured structure is formed in the low-temperature epitaxial layer. A SiO2 layer including a plurality of convexes is located on the textured structure to increase light extraction efficiency of the LED epitaxial structure. A manufacturing method of the LED epitaxial structure is also disclosed. | 05-16-2013 |
20130161652 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) includes a substrate, a buffer layer and an epitaxial structure. The substrate has a first surface with a patterning structure formed thereon. The patterning structure includes a plurality of projections. The buffer layer is arranged on the first surface of the substrate. The epitaxial structure is arranged on the buffer layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer arranged on the buffer layer in sequence. The first semiconductor layer has a second surface attached to the active layer. A distance between a peak of each the projections and the second surface of the first semiconductor layer is ranged from 0.5 μm to 2.5 μm. | 06-27-2013 |
20130234150 | LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF - A light emitting diode includes a substrate, a transitional layer on the substrate and an epitaxial layer on the transitional layer. The transitional layer includes a planar area with a flat top surface and a patterned area with a rugged top surface. An AlN material includes a first part consisting of a plurality of spheres and a second part consisting of a plurality of slugs. The spheres are on a top surface of the transitional layer, both at the planar area and the patterned area. The slugs are in grooves defined in the patterned area. Air gaps are formed between the slugs and a bottom surface of the epitaxial layer. The spheres and slugs of the AlN material help reflection of light generated by the epitaxial layer to a light output surface of the LED. | 09-12-2013 |
20140027806 | SEMICONDUCTOR OPTOELECTRONIC STRUCTURE WITH INCREASED LIGHT EXTRACTION EFFICIENCY - A semiconductor optoelectronic structure with increased light extraction efficiency, includes a substrate; a buffer layer is formed on the substrate and includes a pattern having plural grooves formed adjacent to the substrate; a semiconductor layer is formed on the buffer layer and includes an n-type conductive layer formed on the buffer layer, an active layer formed on the n-type conductive layer, and a p-type conductive layer formed on the active layer; a transparent electrically conductive layer is formed on the semiconductor layer; a p-type electrode is formed on the transparent electrically conductive layer; and an n-type electrode is formed on the n-type conductive layer. | 01-30-2014 |
20140065745 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE - A manufacturing method for an LED (light emitting diode) includes following steps: providing a substrate; disposing a transitional layer on the substrate, the transitional layer comprising a planar area with a flat top surface and a patterned area with a rugged top surface; coating an aluminum layer on the transitional layer; using a nitriding process on the aluminum layer to form an AlN material on the transitional layer; disposing an epitaxial layer on the transitional layer and covering the AlN material, the epitaxial layer contacting the planar area and the patterned area of the transitional layer, a plurality of gaps being defined between the epitaxial layer and the slugs of the second part of the AlN material in the patterned area of the transitional layer. | 03-06-2014 |
20140106485 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODES - An LED manufacturing method includes following steps: providing an LED die; providing an electrode layer having a first section and a second section electrically insulated from the first section, and arranging the LED die on the second section wherein an electrically conductive material electrical connects a bottom of the LED die with second section; forming a transparent conductive layer to electrically connect a top of the LED die with the first section; providing a base and coating an outer surface of the base with a layer of electrically conductive material, defining a continuous gap in the electrically conductive material to divide the electrically conductive material into a first electrode part, and a second electrode part, arranging the electrode layer on the base so that the first section contacts the first electrode part, and the second section contacts the second electrode part. | 04-17-2014 |
20140131656 | LIGHT EMITTING DIODE CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode chip includes a sapphire substrate and a plurality of carbon nano-tubes arranged on an upper surface of the sapphire substrate. Gaps are formed between two adjacent carbon nano-tubes to expose parts of the upper surface of the sapphire substrate. An un-doped GaN layer is formed on the exposed parts of the upper surface of the sapphire substrate and covers the carbon nano-tubes. An n-type GaN layer, an active layer and a p-type GaN layer are formed on the un-doped GaN layer in sequence. A method for manufacturing the light emitting diode chip is also provided. | 05-15-2014 |
20140146519 | ILLUMINATION DEVICE HAVING AIR PURIFYING APPARATUS - An exemplary illumination device includes a lamp and an air purifying apparatus received in the lamp. The lamp includes a base, a lamp post, a lamp cover, and a light source in the lamp cover. The air purifying apparatus is received in the base. A plurality of inlets and outlets is defined in the base. The inlets and outlets communicate with the air purifying apparatus. Air near the inlets is drawn into the air purifying apparatus via the air inlets, and the air is exhausted out of the base via the air outlets after purified by the air purifying apparatus. | 05-29-2014 |
20140175506 | LED EPITAXIAL STRUCTURE - An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein. The first n-type epitaxial layer has a doping concentration which varies along a thickness direction of the first n-type epitaxial layer. | 06-26-2014 |
20140242738 | MANUFACTURING METHOD FOR AN LED - A manufacturing method for an LED includes providing a substrate having a buffer layer and a first N-type epitaxial layer, forming a blocking layer on the first N-type epitaxial layer, and etching the blocking layer to form patterned grooves penetrating the blocking layer to the first N-type epitaxial layer. A second N-type epitaxial layer is then formed on the blocking layer to contact the first N-type epitaxial layer; a light emitting layer, a P-type epitaxial layer and a conductive layer are thereafter disposed on the second N-type epitaxial layer; an N-type electrode is formed to electrically connect with the first N-type epitaxial layer, and a P-type electrode is formed on the conductive layer. The N-type electrode is disposed on the blocking layer and separated from the second | 08-28-2014 |
20140291689 | LIGHT EMITTING DIODE WITH WAVE-SHAPED BRAGG REFLECTIVE LAYER AND METHOD FOR MANUFACTURING SAME - An exemplary light emitting diode includes a substrate and a first undoped GaN layer formed on the substrate. The first undoped GaN layer has ion implanted areas on an upper surface thereof. A plurality of second undoped GaN layers is formed on the first undoped GaN layer. Each of the second undoped GaN layers is island shaped and partly covers at least one corresponding ion implanted area. A Bragg reflective layer is formed on the second undoped GaN layer and on portions of upper surfaces of the ion implanted areas not covered by the second undoped GaN layers. An n-type GaN layer, an active layer and a p-type GaN layer are formed on an upper surface of the Bragg reflective layer in that sequence. A method for manufacturing the light emitting diode is also provided. | 10-02-2014 |
20140306176 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING LIGHT EMITTING DIODES - An exemplary light emitting diode includes a substrate and a first undoped gallium nitride (GaN) layer formed on the substrate. The first undoped GaN layer defines a groove in an upper surface thereof. A distributed Bragg reflector is formed in the groove of the first undoped GaN layer. The distributed Bragg reflector includes a plurality of second undoped GaN layers and a plurality of air gaps alternately stacked one on the other. An n-type GaN layer, an active layer and a p-type GaN layer are formed on the distributed Bragg reflector and the first undoped GaN layer. A p-type electrode and an n-type electrode are electrically connected with the p-type GaN layer and the n-type GaN layer, respectively. A method for manufacturing plural such light emitting diodes is also provided. | 10-16-2014 |
20140327036 | LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) chip includes an N-type semiconductor layer, a compensation layer arranged on the N-type semiconductor layer, an active layer arranged on the compensation layer; and a P-type semiconductor layer arranged on the active layer. During growth of the compensation layer, atoms of an element (i.e., Al) of the compensation layer move to fill epitaxial defects in the N-type semiconductor layer, wherein the epitaxial defects are formed due to lattice mismatch when growing the N-type semiconductor. A method for manufacturing the chip is also disclosed. The compensation layer is made of a compound having a composition of Al | 11-06-2014 |
20140329347 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODES - An exemplary method for manufacturing a light emitting diode includes following steps: providing a substrate; growing an undoped GaN layer on the substrate, the undoped GaN layer comprising an upper surface away from the substrate and a lower surface contacting the substrate; etching the upper surface of the undoped GaN layer to form a plurality of cavities; growing an Distributed Bragg Reflector layer on the upper surface of the undoped GaN layer; and forming sequentially an N-type GaN layer, an active layer and a P-type GaN layer on the Distributed Bragg Reflector layer. | 11-06-2014 |
20140342099 | METHOD OF PHOTOCURING A COATING FILM - A method of photocuring a coating film includes steps: providing a component, and coating the coating film on the component; then a pulse UV LED light source is used to irradiate the coating film to thereby solidify the coating film. During the on time of the pulse UV light source, it supplies a UV light with an enhanced intensity to the coating film to cause a top surface of the coating film to be cured quickly. Accordingly, a reaction between oxygen and free radicals in the coating film can be effectively avoided. | 11-20-2014 |
20150041823 | LED DIE AND METHOD OF MANUFACTURING THE SAME - An LED die includes a substrate, a first buffer layer, a second buffer layer, a plurality of nanospheres, a first semiconductor layer, an active layer and a second semiconductor layer. The first buffer layer, the second buffer layer, the first semiconductor layer, the active layer and the second semiconductor layer are formed successively on the substrate. The substrate has a plurality of protrusions formed on a surface thereof. The nanospheres are located on the first buffer layer formed on the protrusions and covered by the second buffer layer. The present disclosure also provides a method of manufacturing an LED die. | 02-12-2015 |
20150048302 | LIGHT EMITTING DIODE HAVING CARBON NANOTUBES THEREIN AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a substrate, an un-doped GaN layer, a plurality of carbon nanotubes, an N-type GaN layer, an active layer formed on the N-type GaN layer, and a P-type GaN layer formed on the active layer. The substrate includes a first surface and a second surface opposite and parallel to the first surface. A plurality of convexes is formed on the first surface of the substrate. The un-doped GaN layer is formed on the first surface of the substrate. The plurality of carbon nanotubes is formed on an upper surface of the un-doped GaN layer. The plurality of carbon nanotubes is spaced from each other to expose a portion of the upper surface of the un-doped GaN layer. The N-type GaN layer is formed on the exposed portion of the upper surface of the un-doped GaN layer and covering the carbon nanotubes therein. | 02-19-2015 |
20150054012 | LED DIE AND METHOD OF MANUFACTURING THE SAME - An LED die includes a substrate, a first buffer layer, a second buffer layer, a plurality of nanospheres, a first semiconductor layer, an active layer and a second semiconductor layer. The first buffer layer, the second buffer layer, the first semiconductor layer, the active layer and the second semiconductor layer are formed successively on the substrate. The substrate has a plurality of protrusions on a surface thereof. The nanospheres are located on the protrusions and covered by the second buffer layer and located in the second buffer layer. The present disclosure also provides a method of manufacturing an LED die. | 02-26-2015 |
20150069323 | SINGLE PHOTON SOURCE DIE AND METHOD OF MANUFACTURING THE SAME - A single photon source die includes a first semiconductor layer, a plurality of columnar structures formed on the first semiconductor layer, a second semiconductor layer formed on the columnar structures. Each columnar structure includes a bottom layer, a single photon point layer and a connecting layer. The single photon point layer includes a plurality of single photon points. | 03-12-2015 |
Sheng-Han Tu, Taoyuan Hsien TW
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20090090929 | LIGHT-EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light-emitting diode (LED) chip includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer and a groove. The first semiconductor layer, active layer and second semiconductor layer are formed on the substrate in sequence. The groove is formed in the first semiconductor layer, the active layer and the second semiconductor layer. | 04-09-2009 |
Shih-Chung Tu, Taipei Country TW
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20090254717 | STORAGE SYSTEM AND METHOD THEREOF - A storage system and a method thereof. The storage system comprises first and second storage devices, first and second analog front ends, and a controller. The first and second analog front ends, coupled to the first and second storage devices, receive first and second analog data from the first and second drive devices for conversion to first and second digital data. The controller, coupled to the first and second analog front ends, comprises a signal processor and a common memory. The signal processor receives the first and second digital data to perform first and second digital signal processing and access the common memory. The common memory is coupled to the signal processor to be accessed thereby. | 10-08-2009 |
Shih-Wang Tu, Kaohsiung City TW
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20100232170 | HEADLIGHT OF MOTORCYCLE - A headlight of motorcycle includes a dashboard, a connection member, a headlight, a bracket, and front support racks. The dashboard is coupled to the headlight by the connection member in a modularized manner. The headlight forms coupling holes for mounting to the front support racks. The bracket carries signal lights thereon. By coupling the headlight and the dashboard together in a modularized manner and mounting the bracket that carries the signal lights to the opposite sides of the headlight, and further fixing the front support racks to the opposite sides of the headlight, a headlight module is formed. The headlight module can be easily attached between upper and lower beams of a steering handlebar by using the front support racks so as to simplify the assembling operation and to conceal the front support racks between the bracket and the steering handlebar for improving the outside appearance of the headlight. | 09-16-2010 |
Shu-Hui Tu, Chung-Li TW
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20100005430 | DDCC and FDCCII-Grounded Resistor and Capacitor Filter Structures - A voltage-mode nth-order differential difference current conveyor (DDCC) and fully differential current conveyor (FDCCII)-resistor and capacitor filter structures are proposed using a new effective analytical synthesis method (ASM), a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint sub-circuitry, A new ASM can effectively carry out (i) use of all the grounded capacitors and grounded resistors, and (ii) employment of the minimum number of active and passive components and then enjoys the low sensitivities, lower parasitics, power consumption, noise, and smaller chip area leading to simultaneously achieving two important features: (i) higher output performance and (ii) lower cost, without tradeoff. Moreover, the component value variations of all the relative sensitivities have the same incremental percentage or decrement. | 01-07-2010 |
20100031205 | ANALYTICAL SYNTHESIS METHOD AND OTA-BASED CIRCUIT STRUCTURE - An analytical Synthesis Method (ASM) is clearly and effectively demonstrated in the realization of current/voltage-mode Operational Trans-conductance Amplifier and Capacitor (OTA-C) circuits, where a complicated nth-order transfer function is manipulated and decomposed by a succession of innovative algebra operations until a set of simple equations are produced, which are then realized using n integrators and a constraint circuitry. The circuits realized includes voltage-mode nth-order OTA-C universal filter structures, tunable voltage/current-mode OTA-C universal biquad filters, voltage-mode odd/even-nth-order OTA-C elliptic filter structures, voltage/current-mode odd-nth-order OTA-C elliptic high-pass filter structures, and OTA-C quadrature oscillators. Some realized OTA-C circuits can be simplified to be OTA-only (OTA-parasiic C) circuits which fit for the operation at high frequencies. | 02-04-2010 |
20100264996 | Nth-Order Arbitrary-Phase-Shift Sinusoidal Oscillator Structure and Analytical Synthesis Method of Making the same - Nth-order voltage- and current-mode arbitrary phase shift oscillator structures are synthesized using n operational trans-conductance amplifiers (OTAs) or second-generation current controlled conveyors (CCCIIs) and n grounded capacitors. Linking up the I/O characteristics of the OTA and the CCCII and the reactance of grounded capacitor, the step of synthesis is first based on the algebraic analysis to oscillatory characteristic equations, resulting in a quadrature oscillator structure. Secondly, instead of the quadrature characteristic, to control each output signal with one another by a desired phase difference > or <90°, selectively superposing any of two fundamental OTA/CCCII-C sub-circuitries benefits the transformation of quadrature to arbitrary-phase-shift characteristic for the sinusoidal oscillator structure. Furthermore, several compensation schemes are presented for reducing the output parameter deviation due to the non-ideal effects. | 10-21-2010 |
20110316628 | COMPLIMENTARY SINGLE-ENDED-INPUT OTA-C UNIVERSAL FILTER STRUCTURES - A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source. | 12-29-2011 |
Ta-Sen Tu, Fengyuan City TW
Ting-Chieh Tu, Danshui Township TW
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20110122025 | ANTENNA ADJUSTMENT APPARATUS, ANTENNA ADJUSTMENT METHOD AND TANGIBLE MACHINE-READABLE MEDIUM THEREOF - An antenna adjustment apparatus, an antenna adjustment method and a tangible machine-readable medium thereof are provided. The antenna adjustment apparatus is electrically connected to a directional antenna and is configured to generate a signal loss value according to an environmental coordinate parameter, an antenna coordinate parameter, an excitation parameter set and an antenna structure parameter. The antenna adjustment apparatus is configured to determine whether the signal loss value meets a communication quality condition and set an excitation parameter set, which meets the communication quality condition, as an available excitation parameter set so that the antenna radiation pattern of the directional antenna may be adjusted according to the available excitation parameter set. | 05-26-2011 |
Tseng-Rong Tu, Taitung City TW
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20090060939 | COMPOSITIONS AND METHODS FOR TREATING ALLERGIES, AUTO-IMMUNE DISEASES, AND IMPROVING SKIN CONDITION BY GANODERMA LUCIDUM (REISHI) POLYSACCHARIDES - A method for treating an allergy by providing a pharmaceutical composition containing at least | 03-05-2009 |
20090060940 | Compositions and methods for treating psoriasis by ganoderma lucidum (Reishi) polysaccharides - A method for treating psoriasis by providing a pharmaceutical composition containing at least | 03-05-2009 |
20110028428 | HIRSUTELLA SINENSIS MYCELIA COMPOSITIONS AND METHODS FOR TREATING SEPSIS AND RELATED INFLAMMATORY RESPONSES - Compositions comprising | 02-03-2011 |
Wen-Chieh Tu, Tainan County TW
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20090091028 | SEMICONDUCTOR DEVICE AND METHOD OF BUMP FORMATION - A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface. | 04-09-2009 |
Wen-Ching Tu, Taipei Hsien TW
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20100238130 | ELECTRONIC BOOK DEVICE AND METHOD FOR OPERATING THE SAME - An electronic book device and a method for operating the electronic book device are disclosed, wherein the electronic book device includes a memory module, an electronic paper, a touch display and a first touch control module. The touch display is separate from the electronic paper and has a touch panel. The memory module can store an electronic book. The electronic paper can display a first frame according to the electronic book. The first touch control module can control the first frame when the touch panel is touched. | 09-23-2010 |
Wen - Yi Tu, Taichung County TW
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20100176178 | Nailing mechanism for a packing plates - A nailing mechanism for a packing plate comprises a middle feeding device, an upper feeding device, a lower feeding device, a first conveying belt, a second conveying belt, a third conveying belt, a first push panel, a second push panel, a plurality of first nail guns, and a plurality of second nail guns, wherein the nailing mechanism are used to automatically assemble a plurality of first, second, and third slabs together to make a finished packing plate, thus lowering production costs and enhancing manufacturing efficiency. | 07-15-2010 |
Wu Chang Tu, Tainan County TW
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20090243056 | CHIP PACKAGE HAVING ASYMMETRIC MOLDING - A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal. | 10-01-2009 |
20100264540 | IC Package Reducing Wiring Layers on Substrate and Its Carrier - An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed. | 10-21-2010 |
Ya-Sen Tu, Taoyuan Hsien TW
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20100181950 | FAN AND CONTROLLING DEVICE THEREOF - A fan is electrically connected with an alternating current power source. The fan includes an impeller, a motor and a controlling device. The controlling device includes a commutating unit, a magnetic detecting unit, a first switching unit, a second switching unit, a third switching unit and a controlling unit. The alternating current power source is electrically connected with the first switching unit, the second switching unit and the commutating unit, respectively. The commutating unit is electrically connected with the magnetic detecting unit and the controlling unit, respectively. The controlling unit is electrically connected with the third switching unit and the first switching unit, respectively. The third switching unit is electrically connected with the second switching unit. The first switching unit and the second switching unit are electrically connected with the motor, respectively. A controlling device of the fan is also disclosed. | 07-22-2010 |
20110122581 | HEAT EXCHANGE DEVICE AND CLOSED-TYPE ELECTRONIC APPARATUS USING THE SAME - A heat exchange device includes a housing, an internal circulating fan, an external circulating fan and a heat exchange unit. The internal and external circulating fans and the heat exchange unit are disposed in the housing. The internal and external circulating fans are disposed at the same side relative to the heat exchange unit. A closed-type electronic apparatus including the heat exchange device is also disclosed. | 05-26-2011 |
20110198061 | HEAT EXCHANGE DEVICE FOR CLOSED ELECTRICAL APPARATUS - A heat exchange unit is disclosed. At least one air opening of the heat exchange unit is formed from a sloped surface, enabling the area of the air opening to exceed the cross-sectional area of heat exchange of the heat exchange unit, and further enhancing heat exchange efficiency. A heat exchange device employing the heat exchange unit and a closed electrical apparatus employing the heat exchange device are also disclosed. | 08-18-2011 |
20120068642 | SINGLE PHASE DC BRUSHLESS MOTOR CONTROLLER AND METHOD FOR CONTROLLING ROTATION SPEED AND DIRECTION OF SINGLE PHASE DC BRUSHLESS MOTOR - A single phase DC brushless motor controller, including: a micro control unit including: a Pulse Width Modulation (PWM) pin for receiving a PWM signal from a system; and a commutation logic unit for controlling the speed and rotation of a single phase DC brushless motor according to the PWM signal. | 03-22-2012 |
20120181002 | HEAT EXCHANGER - A heat exchanger is provided. The heat exchanger includes a heat dissipation module, an inner heat-dissipating device and an outer heat-dissipating device. The heat dissipation module includes a body, a plurality of first inlets, a plurality of first outlets, a plurality of second inlets, a plurality of second outlets, a plurality of first flow paths and a plurality of second flow paths, wherein the first flow paths are staggered with the second flow paths, and the first inlets and the first outlets are communicated with the first flow paths, the second inlets and the second outlets are communicated with the second flow paths, the body includes a first surface and a second surface opposite to the first surface, the first inlets and the first outlets are formed on the first surface, and the second inlets and the second outlets are formed on the second surface. | 07-19-2012 |
20130086931 | AIR CONDITIONING APPARATUS AND CONTROL METHOD THEREOF - An air conditioning apparatus and a control method thereof are provided. The air conditioning apparatus includes a first switch valve, a compressor, a decompression element, a second switch valve, a condenser, and an evaporator. The control method of an air conditioning apparatus includes steps of setting a preset temperature, measuring an indoor temperature, and comparing the preset temperature with the indoor temperature. When the indoor temperature is lower than the preset temperature, the first switch valve and the second switch valve are turned on and the compressor is turned off; and when the indoor temperature is higher than the preset temperature, the first switch valve and the second switch valve are turned off and the compressor is turned on. | 04-11-2013 |
Yean-Hung Tu, Taoyuan County TW
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20110077430 | Method and precursor for production of no-carrier-added N-(4-[18F] fluorobutyl)-Ethacrynic amide - The present invention is related to a precursor for no-carrier-added fluorine-18 labeled ethacrynic acid, N-(4-[ | 03-31-2011 |
Yeur-Luen Tu, Taichung TW
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20080217775 | Method of forming contact plugs for eliminating tungsten seam issue - A method of forming a contact plug of an eDRAM device includes the following steps: forming a tungsten layer with tungsten seam on a dielectric layer to fill a contact hole; removing the tungsten layer from the top surface of the dielectric layer, recessing the tungsten layer in the contact hole to form a recess of about 600˜900 Angstroms in depth below the top surface of the dielectric layer, depositing a conductive layer on the dielectric layer and the recessed tungsten plug to fill the recess; and removing the conductive layer from the top surface of the dielectric layer to form a conductive plug on the recessed tungsten plug in the contact hole. | 09-11-2008 |
20080318378 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 12-25-2008 |
20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
20100248446 | METHOD AND APPARATUS OF HOLDING A DEVICE - Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. | 09-30-2010 |
20110260280 | Back Side Defect Reduction For Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystalized silicon layer is formed on the back side of the substrate. The recrystalized silicon layer has different photoluminescence intensity than the substrate. | 10-27-2011 |
20110263069 | METHODS TO AVOID LASER ANNEAL BOUNDARY EFFECT WITHIN BSI CMOS IMAGE SENSOR ARRAY - Methods are disclosed herein for determining the laser beam size and the scan pattern of laser annealing when fabricating backside illumination (BSI) CMOS image sensors to keep dark-mode stripe patterns corresponding to laser scan boundary effects from occurring within the sensor array regions of the image sensors. Each CMOS image sensor has a sensor array region and a periphery circuit. The methods determines a size of the laser beam from a length of the sensor array region and a length of the periphery circuit so that the laser beam covers an integer number of the sensor array region for at least one alignment of the laser beam on the array of BSI image sensors. The methods further determines a scan pattern so that the boundary of the laser beam does not overlap the sensor array regions during the laser annealing, but only overlaps the periphery circuits. | 10-27-2011 |
20120034730 | Backside Illuminated Sensor Processing - The present disclosure provides methods and apparatus for reducing dark current in a backside illuminated semiconductor device. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside surface and a backside surface, and forming a plurality of sensor elements in the substrate, each of the plurality of sensor elements configured to receive light directed towards the backside surface. The method further includes forming a dielectric layer on the backside surface of the substrate, wherein the dielectric layer is formed to have a compressive stress to induce a tensile stress in the substrate. A backside illuminated semiconductor device fabricated by such a method is also disclosed. | 02-09-2012 |
20120038015 | ANTIREFLECTIVE LAYER FOR BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MANUFACTURING SAME - The present disclosure provides an image sensor device that exhibits improved quantum efficiency. For example, a backside illuminated (BSI) image sensor device is provided that includes a substrate having a front surface and a back surface; a light sensing region disposed at the front surface of the substrate; and an antireflective layer disposed over the back surface of the substrate. The antireflective layer has an index of refraction greater than or equal to about 2.2 and an extinction coefficient less than or equal to about 0.05 when measured at a wavelength less than 700 nm. | 02-16-2012 |
20120091549 | FORMATION OF EMBEDDED MICRO-LENS - Provided is an image sensor device. The image sensor device includes a pixel formed in a substrate. The image sensor device includes a first micro-lens embedded in a transparent layer over the substrate. The first micro-lens has a first upper surface that has an angular tip. The image sensor device includes a color filter that is located over the transparent layer. The image sensor device includes a second micro-lens that is formed over the color filter. The second micro-lens has a second upper surface that has an approximately rounded profile. The pixel, the first micro-lens, the color filter, and the second micro-lens are all at least partially aligned with one another in a vertical direction. | 04-19-2012 |
20120235280 | INTEGRATED CIRCUIT INCLUDING A BIPOLAR TRANSISTOR AND METHODS OF MAKING THE SAME - An integrated circuit includes a bipolar transistor disposed over a substrate. The bipolar transistor includes a base electrode disposed around at least one germanium-containing layer. An emitter electrode is disposed over the at least one germanium-containing layer. At least one isolation structure is disposed between the emitter electrode and the at least one germanium-containing layer. A top surface of the at least one isolation structure is disposed between and electrically isolating a top surface of the emitter electrode from a top surface of the at least one germanium-containing layer. | 09-20-2012 |
20120258564 | METHOD TO AVOID FIXED PATTERN NOISE WITHIN BACKSIDE ILLUMINATED (BSI) COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) SENSOR ARRAY - The present disclosure provides one embodiment of a method. The method includes providing a semiconductor substrate having a front side and a backside, wherein the front side of the semiconductor substrate includes a plurality of backside illuminated imaging sensors; bonding a carrier substrate to the semiconductor substrate from the front side; thinning the semiconductor substrate from the backside; performing an ion implantation to the semiconductor substrate from the backside; performing a laser annealing process to the semiconductor substrate from the backside; and thereafter, performing a polishing process to the semiconductor substrate from the backside. | 10-11-2012 |
20120261781 | SIDEWALL FOR BACKSIDE ILLUMINATED IMAGE SENSOR METAL GRID AND METHOD OF MANUFACTURING SAME - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 10-18-2012 |
20130040446 | Backside Surface Treatment of Semiconductor Chips - A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O | 02-14-2013 |
20130048936 | PHASE CHANGE MEMORY AND METHOD OF FABRICATING SAME - A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer. | 02-28-2013 |
20130113061 | IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING - Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner. | 05-09-2013 |
20130210188 | Method and Apparatus for Reducing Stripe Patterns - A method for reducing stripe patterns comprising receiving scattered light signals from a backside surface of a laser annealed backside illuminated image sensor wafer, generating a backside surface image based upon the scattered light signals, determining a distance between an edge of a sensor array of the laser anneal backside illuminated image sensor wafer and an adjacent boundary of a laser beam and re-calibrating the laser beam if the distance is less than a predetermined value. | 08-15-2013 |
20130270663 | ANTI-REFLECTIVE LAYER FOR BACKSIDE ILLUMINATED CMOS IMAGE SENSORS - A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide. | 10-17-2013 |
20130285130 | BACKSIDE ILLUMINATED IMAGE SENSOR WITH NEGATIVELY CHARGED LAYER - A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these. | 10-31-2013 |
20130329102 | IMAGE SENSOR HAVING COMPRESSIVE LAYERS - An image sensor device including a semiconductor substrate that includes an array region and a black level correction region. The array region contains a plurality of radiation-sensitive pixels. The black level correction region contains one or more reference pixels. The substrate has a front side and a back side. The image sensor device includes a first compressively-stressed layer formed on the back side of the substrate. The first compressively-stressed layer contains silicon oxide, and is negatively charged. The second compressively-stressed layer contains silicon nitride, and is negatively charged. A metal shield is formed over at least a portion of the black level correction region. The image sensor device includes a third compressively-stressed layer formed on the metal shield and the second compressively-stressed layer. The third compressively-stressed layer contains silicon oxide. A sidewall of the metal shield is protected by the third compressively-stressed layer. | 12-12-2013 |
20140061738 | Method to Form a CMOS Image Sensor - The present disclosure relates to a method and composition to limit crystalline defects introduced in a semiconductor device during ion implantation. A high-temperature low dosage implant is performed utilizing a tri-layer photoresist which maintains the crystalline structure of the semiconductor device while limiting defect formation within the semiconductor device. The tri-layer photoresist comprises a layer of spin-on carbon deposited onto a substrate, a layer of silicon containing hard-mask formed above the layer of spin-on carbon, and a layer of photoresist formed above the layer of silicon containing hard-mask. A pattern formed in the layer of photoresist is sequentially transferred to the silicon containing hard-mask, then to the spin-on carbon, and defines an area of the substrate to be selectively implanted with ions. | 03-06-2014 |
20140061842 | Multiple Metal Film Stack in BSI Chips - A method includes forming an opening extending from a back surface of a semiconductor substrate to a metal pad on a front side of the semiconductor substrate, and forming a first conductive layer including a first portion overlapping active image sensors in the semiconductor substrate, a second portion overlapping black reference image sensors in the semiconductor substrate, and a third portion in the opening to contact the metal pad. A second conductive layer is formed over and contacting the first conductive layer. A first patterning step is performed to remove the first and the second portions of the second conductive layer, wherein the first conductive layer is used as an etch stop layer. A second patterning step is performed to remove a portion of the first portion of the first conductive layer. The second and the third portions of the first conductive layer remain after the second patterning step. | 03-06-2014 |
20140065756 | Sidewall for Backside Illuminated Image Sensor Metal Grid and Method of Manufacturing Same - The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature. | 03-06-2014 |
20140073080 | Back Side Defect Reduction for Back Side Illuminated Image Sensor - Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor also includes a radiation-detection device that is formed in the substrate. The radiation-detection device is operable to detect a radiation wave that enters the substrate through the back side. The image sensor further includes a recrystallized silicon layer. The recrystallized silicon layer is formed on the back side of the substrate. The recrystallized silicon layer has different photoluminescence intensity than the substrate. | 03-13-2014 |
20140117546 | HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS - The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers. | 05-01-2014 |
20140252635 | Bonding Structures and Methods of Forming the Same - A package includes a package component and a second package component. A first elongated bond pad is at a surface of the first package component, wherein the first elongated bond pad has a first length in a first longitudinal direction, and a first width smaller than the first length. A second elongated bond pad is at a surface of the second package component. The second elongated bond pad is bonded to the first elongated bond pad. The second elongated bond pad has a second length in a second longitudinal direction, and a second width smaller than the second width. The second longitudinal direction is un-parallel to the first longitudinal direction. | 09-11-2014 |
20140256087 | Hybrid Bonding and Apparatus for Performing the Same - A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded pair, first metal pads in the first package component are bonded to second metal pads in the second package component, and a first surface dielectric layer at a surface of the first package component is bonded to a second surface dielectric layer at a surface of the second package component. After the hybrid bonding, a thermal compressive annealing is performed on the bonded pair. | 09-11-2014 |
20140264493 | Semiconductor Device and Fabricating the Same - A semiconductor device includes a substrate, a gate stack having at least one gate vertex directed to an area in the substrate below the gate stack. The semiconductor device also includes a source structure having at least one vertex directed toward the area in the substrate and a drain structure having at least one vertex directed toward the area in the substrate. | 09-18-2014 |
20140264506 | METHODS AND APPARATUS FOR CMOS SENSORS - Methods and apparatus for a sensor are disclosed. An oxide layer is formed on a substrate, followed by a spacer layer and a buffer layer. A photoresist layer is formed on the buffer layer over a pixel region, with an opening exposing a first part of the buffer layer. A first etching is performed to remove the first part of the buffer layer to expose a first part of the spacer layer. A second etching is performed to remove the first part of the spacer layer, the remaining buffer layer, and partially remove a second part of the spacer layer so that the result spacer layer will have an end with a shape substantially similar to a triangle, a height of the end is in a substantially same range as a length of the end. | 09-18-2014 |
20150028402 | PHOTODIODE GATE DIELECTRIC PROTECTION LAYER - The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor. | 01-29-2015 |
20150031189 | MECHANISMS FOR CLEANING SUBSTRATE SURFACE FOR HYBRID BONDING - Embodiments of mechanisms for cleaning a surface of a semiconductor wafer for a hybrid bonding are provided. The method for cleaning a surface of a semiconductor wafer for a hybrid bonding includes providing a semiconductor wafer, and the semiconductor wafer has a conductive pad embedded in an insulating layer. The method also includes performing a plasma process to a surface of the semiconductor wafer, and metal oxide is formed on a surface of the conductive structure. The method further includes performing a cleaning process using a cleaning solution to perform a reduction reaction with the metal oxide, such that metal-hydrogen bonds are formed on the surface of the conductive structure. The method further includes transferring the semiconductor wafer to a bonding chamber under vacuum for hybrid bonding. Embodiments of mechanisms for a hybrid bonding and a integrated system are also provided. | 01-29-2015 |
20150041761 | Backside Illuminated Photo-Sensitive Device with Gradated Buffer Layer - A method for forming a backside illuminated photo-sensitive device includes forming a gradated sacrificial buffer layer onto a sacrificial substrate, forming a uniform layer onto the gradated sacrificial buffer layer, forming a second gradated buffer layer onto the uniform layer, forming a silicon layer onto the second gradated buffer layer, bonding a device layer to the silicon layer, and removing the gradated sacrificial buffer layer and the sacrificial substrate. | 02-12-2015 |
20150041874 | MIM Capacitors with Improved Reliability - A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer. | 02-12-2015 |
20150056739 | IMAGE SENSOR TRENCH ISOLATION WITH CONFORMAL DOPING - Provided is a semiconductor image sensor device. The image sensor device includes a substrate. The image sensor device includes a first pixel and a second pixel disposed in the substrate. The first and second pixels are neighboring pixels. The image sensor device includes an isolation structure disposed in the substrate and between the first and second pixels. The image sensor device includes a doped isolation device disposed in the substrate and between the first and second pixels. The doped isolation device surrounds the isolation structure in a conformal manner. | 02-26-2015 |
20150069619 | 3DIC Interconnect Apparatus and Method - An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug. | 03-12-2015 |
20150072505 | METHOD AND APPARATUS OF HOLDING A DEVICE - Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. | 03-12-2015 |
20150076646 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A backside illumination semiconductor image sensing device includes a semiconductor substrate. The semiconductor substrate includes a radiation sensitive diode and a peripheral region. The peripheral region is proximal to a sidewall of the backside illumination semiconductor image sensing device. The backside illumination semiconductor image sensing device further includes a first anti reflective coating (ARC) on a backside of the semiconductor substrate and a dielectric layer on the first anti reflective coating. Additionally, a radiation shielding layer is disposed on the dielectric layer. Moreover, the backside illumination semiconductor image sensing device has a photon blocking layer on the sidewall of the of the backside illumination semiconductor image sensing device. The at least a portion of a sidewall of the radiation shielding layer is not covered by the photon blocking layer and the photon blocking layer is configured to block photons penetrating into the semiconductor substrate. | 03-19-2015 |
Yi-Chang Tu, Tai-Nan City TW
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20090040087 | DATA WEIGHTED AVERAGE CIRCUIT AND DYNAMIC ELEMENT MATCHING METHOD - A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data. | 02-12-2009 |
20090326692 | DIGITAL-TO-ANALOG CONVERTER FOR REDUCING POP NOISE AND HARMONIC TONE AND RELATED CONVERTING METHOD - A digital-to-analog converting (DAC) circuit is utilized for converting a 1-bit stream into an analog output signal. The DAC includes an N-bit encoder, a multiplexer, a low-pass filter, and a digital-to-analog conversion circuit. The N-bit encoder is utilized for receiving the 1-bit stream and encoding the 1-bit stream to generate an N-bit stream, where N is larger than 1; the multiplexer is utilized for selectively outputting the N-bit stream or a zero signal as an output signal according to a selection signal; the low-pass filter is utilized to generate a filtered output signal according to the output signal; and the digital to analog conversion circuit is utilized to generate the analog output signal according to the filtered output signal. | 12-31-2009 |
20100026907 | TV AUDIO MULTI-STANDARD DETECTION APPARATUS AND METHOD - An audio multi-standard detection apparatus is provided to pre-record a plurality of audio broadcasting format carrier bands. The detection apparatus includes: a carrier calculation unit and a switch controller. The carrier calculation unit is used for receiving an intermediate frequency signal and calculates the first carrier energy of the intermediate frequency signal in each of the frequency bands. From this first carrier energy, the switch controller determines which frequency bands are existed in the intermediate frequency signal, then analyzes the signal via at least one threshold value to determine the frequency band's primary carrier. The switch controller obtains an effective carrier. Further, the switch controller compares the effective carrier with the pre-recorded carrier bands for selectively outputting the appropriate audio broadcasting format. Hence, the present invention achieves the objective of determining the appropriate audio multi-standard and enables the support of broadcast systems in various countries with a single audio decoding chip. | 02-04-2010 |
Yi-Jen Tu, Pincheo City TW
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20090136750 | Process for the production of squared-analogous cross-section polyamide yarns and uses thereof - The present invention relates to a process for the production of a yarn consisting of a squared-analogous cross-section polyamide filament for uncoated airbag fabrics, characterized in that the process comprises the steps of: heating and melting a raw material of polyamide, extruding the molten polyamide through a squared-analogous spinning nozzle to form a spun filament, cooling and solidifying the spun filament, followed by drawing the filament, to obtain a squared-analogous cross-section drawn yarn; to uncoated fabrics for the manufacture of airbags prepared by the said process, characterized in that the fabrics are prepared from a yarn consisting of a squared-analogous cross-section polyamide filament and exhibit low air permeability, enhanced flame resistance and aging performance against the environment; and to a use of the uncoated fabrics for the manufacture of airbags with a low air permeability prepared therefrom. | 05-28-2009 |
Ying-Chieh Tu, Hsinchu Hsien TW
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20110001883 | Motion Estimation Method and Apparatus Thereof - A motion estimation method, applied to an image frame having a time constraint, includes calculating an available time for estimating a motion vector of a block unit of the image frame; and selectively performing at least one stage of a plurality of motion estimation stages according to the available time to estimate the motion vector of the block unit. | 01-06-2011 |
20110293011 | Motion Estimation Apparatus and Motion Estimation Method - A motion estimation apparatus used in a video encoding system is provided. The motion estimation apparatus includes a first calculation module and a second calculation module. When a search position moves from a first candidate search position to a second candidate search position along a search path, the first calculation module estimates a first differential motion vector cost according to a search path information corresponding to the search path. The second calculation module selectively adds the first differential motion vector cost to an initial motion vector cost or subtracts the first differential motion vector cost from the initial motion vector cost according to a predetermined rule, so that a first motion vector cost corresponding to the second candidate search position is obtained. | 12-01-2011 |
20110317933 | Image Coding Method for Facilitating Run Length Coding and Image Encoding Device Thereof - An image coding method for run-length coding (RLC), including quantizing a coefficient string representing a plurality of pixel values to generate a first quantization coefficient string, determining a cutoff quantization coefficient in the first quantization coefficient string, discarding a part of quantization coefficients of the first quantization coefficient string according to the cutoff quantization coefficient, and forming remaining quantization coefficients of the first quantization coefficient string as a second quantization coefficient string, and performing image coding to the second quantization coefficient string with the RLC. | 12-29-2011 |
20120016922 | Video Codec and Method thereof - A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor α to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by α | 01-19-2012 |
20140195736 | DATA ACCESSING METHOD AND ELECTRONIC APPARATUS UTILIZING THE DATA ACCESSING METHOD - A data access method applicable on an electronic apparatus is provided. The electronic apparatus comprises a control unit, a first storage apparatus, and a second storage apparatus. The method comprising: storing a first part of data and a second part of data of a data group in the first storage apparatus and the second storage apparatus, respectively; and selectively accessing the first storage apparatus and the second storage apparatus via different data paths for the first part of data and the second part of data, wherein access speed to the first storage apparatus is different from access speed to the second storage apparatus. | 07-10-2014 |
Ying-Te Tu, Kaohsiung City TW
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20110157950 | MEMORY CHIPS AND JUDGEMENT CIRCUITS THEREOF - A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indicates which mode the memory chip is operating at. The judgment circuit includes a detection unit and a sampling unit. The detection unit is coupled to a first voltage source and the option pad and further controlled by a control signal to generate at least one detection signal according to the current status of the option pad. The sampling unit samples the at least one detection signal after the control signal is asserted to generate the judgment signal. When the control signal is asserted, a level of the at least one detection signal is varied by a voltage provided by the first voltage source. | 06-30-2011 |
20120170400 | MEMORY DEVICES AND ACCESSING METHODS THEREOF - A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal. | 07-05-2012 |
20130155782 | RANDOM ACCESS MEMORY AND REFRESH CONTROLLER THEREOF - A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result. | 06-20-2013 |
20140112088 | CONTROL CIRCUIT, MEMORY DEVICE AND VOLTAGE CONTROL METHOD THEREOF - A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal. | 04-24-2014 |
Yueh-Mei Tu, Hsichih City TW
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20080197158 | Structure mannequin model foot - An improved structure mannequin model foot comprised of a mannequin model calf and a foot piece designed to be separable into two physical entities, the foot piece and calf detachment capability enabling the assembling of different height and size heeled foot pieces to the calves of one single mannequin, thereby facilitating the wearing of different shoes on different foot pieces, to achieve, on the same single mannequin model, the objective of alternating the assembly of different foot pieces to display assorted footwear (such as low, medium, and high heel shoes as well as riding boots, etc.). | 08-21-2008 |
Yung-Yi Tu, Taichung City TW
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20110020975 | METHOD FOR MANUFACTURING PHOTODIODE DEVICE - A method of manufacturing photodiode device includes the following steps: providing a wafer having a substrate and an epitaxy layer, the substrate having a first surface and a second surface and the epitaxy layer formed on the first surface; forming a first conductive layer on the second surface of the substrate; forming a patterned conductive layer above the epitaxy layer; and etching the patterned conductive layer by a reactive ion etching (RIE) process performed under argon gas and helium gas. | 01-27-2011 |
20110284983 | PHOTODIODE DEVICE AND MANUFACTURING METHOD THEREOF - A photodiode device and the manufacturing method of the same are provided. The photodiode device includes a substrate; an epitaxy layer on the substrate, the epitaxy layer including a window layer and a cap layer on the window layer, the cap layer covering a portion of the window layer; and a patterned conductive layer on the cap layer, the patterned conductive layer being formed with a bottom area and a top area wherein the bottom area is greater than the top area. | 11-24-2011 |
Zong-Ru Tu, Keelung City TW
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20090009868 | DIFFRACTION GRATING RECORDING MEDIUM - A diffraction grating recording medium including a waveguide layer and a grating structure layer is provided. The waveguide layer has a reflective surface and a light incident surface, in which a thickness of the waveguide layer is between 100 nanometers and 2 micrometers, and the reflective surface reflects a light that enters the waveguide layer from the light incident layer. The grating structure layer is disposed on the light incident surface of the waveguide layer, in which the grating structure layer has a plurality of diffractive elements, and the arranging period of the diffractive elements is between 50 nanometers and 900 nanometers. | 01-08-2009 |
20140184863 | METHOD FOR CORRECTING PIXEL INFORMATION OF COLOR PIXELS ON A COLOR FILTER ARRAY OF AN IMAGE SENSOR - A method for correcting pixel information of color pixels on a color filter array of an image sensor includes: establishing an M×M distance factor table, selecting M×M pixels of the color filter array, calculating a red/green/blue-color contribution from the red/green/blue pixels to a target pixel in the selected M×M pixels, calculating a red/blue/green-color pixel performance of the target pixel, calculating a red/blue/green-color correcting factor, obtaining a corrected pixel information of each of the red/green/blue pixels, by applying the red/green/blue-color correcting factor to the measured pixel information of each of the red/green/blue pixels. | 07-03-2014 |
20140264686 | SOLID-STATE IMAGING DEVICES - A solid-state imaging device is provided. The solid-state imaging device includes a semiconductor substrate containing a plurality of image sensors. A color filter including a plurality of color filter segments is disposed above the semiconductor substrate. Each of the color filter segments corresponds to one of the image sensors. Further, a plurality of partitions is disposed between the color filter segments. Each of the partitions is disposed between any two adjacent color filter segments. The partition has a height smaller than the height of the color filter segment, wherein the height of the partition is based on the bottom of the color filter segment to the top of the partition, and the height of the color filter segment is based on the bottom of the color filter segment to the top of the color filter segment. | 09-18-2014 |
20140339606 | BSI CMOS IMAGE SENSOR - A back surface illuminated image sensor is provided. The back surface illuminated image sensor includes: a first passivation layer disposed on the photodiode array; an oxide grid disposed on the first passivation layer and forming a plurality of holes exposing the first passivation layer; a color filter array including a plurality of color filters filled into the holes, wherein the oxide grid has a refractive index smaller than that of plurality of color filters; and a metal grid aligned to the oxide grid, wherein the metal grid has an extinction coefficient greater than zero. | 11-20-2014 |
20140339615 | BSI CMOS IMAGE SENSOR - A back surface illuminated image sensor is provided. The back surface illuminated image sensor includes: a first passivation layer disposed on the photodiode array; an oxide grid disposed on the first passivation layer and forming a plurality of holes exposing the first passivation layer; a color filter array including a plurality of color filters filled into the holes, wherein the oxide grid has a refractive index smaller than that of plurality of color filters; and a metal grid aligned to the oxide grid, wherein the metal grid has an extinction coefficient greater than zero. | 11-20-2014 |
20140362250 | METHOD FOR CORRECTING PIXEL INFORMATION OF COLOR PIXELS ON A COLOR FILTER ARRAY OF AN IMAGE SENSOR - A method for correcting pixel information of color pixels on a color filter array of an image sensor includes: establishing an M×M distance factor table, selecting M×M pixels of the color filter array, calculating a red/green/blue-color contribution from the red/green/blue pixels to a target pixel in the selected M×M pixels, calculating a red/blue/green-color pixel performance of the target pixel, calculating a red/blue/green-color correcting factor, obtaining a corrected pixel information of each of the red/green/blue pixels, by applying the red/green/blue-color correcting factor to the measured pixel information of each of the red/green/blue pixels. | 12-11-2014 |