Patent application number | Description | Published |
20130277745 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type. | 10-24-2013 |
20130307080 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 11-21-2013 |
20140035039 | ELECTROSTATIC DISCHARGE (ESD) GUARD RING PROTECTIVE STRUCTURE - An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type. | 02-06-2014 |
20140094009 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERCONNECTS - A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant. | 04-03-2014 |
20140183518 | N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD) - One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor. | 07-03-2014 |
20140264604 | FinFET Having Source-Drain Sidewall Spacers with Reduced Heights - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height. | 09-18-2014 |
Patent application number | Description | Published |
20140131765 | ESD Devices Comprising Semiconductor Fins - A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node. | 05-15-2014 |
20140145249 | Diode Structure Compatible with FinFET Process - An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process. | 05-29-2014 |
Patent application number | Description | Published |
20130175859 | NETWORK APPARATUS WITH COMMON POWER INTERFACE - Disclosed herein is a network apparatus with a common power interface. The network apparatus mechanically connects to a power adapter via an electrical connector, and transfers the power to other electronic device via an electrical port in addition to taking power for the apparatus. In accordance with one of the embodiments of the invention, the apparatus substantially includes a control unit for processing the inner signals and data of the apparatus, and a communication module for processing the wired or wireless communication. A common power interfacing module is particularly introduced to processing the power allocation from the power adapter. A power management unit is also incorporated to managing the power inside the network apparatus, for example taking power for the operation of the apparatus. According to one further embodiment, the network apparatus is a routing device capable of connecting with external storages. | 07-11-2013 |
20140106621 | MEMORY CARD ADAPTER DEVICE - A memory card adapter device made of electricity insulating materials is exemplarily illustrated, and shape of the memory card adapter device is a pentagon. The memory card adapter device is used to switch a mini memory card or a micro memory card, and the memory card adapter includes a linking portion, a socket portion, and a transmission interface. The linking portion is a connection interface, having a plurality of metal conductive touch points used to be electrically connected to computer equipment. The socket portion is used to accommodate the mini the memory card or micro memory card. The transmission interface located inside the socket portion is used to electrically connect the mini memory card or the micro memory card, and the linking portion. A length of a distance between a longer side of the linking portion to an opposite side of which is 20 millimeters to 25 millimeters. | 04-17-2014 |