Patent application number | Description | Published |
20100258993 | METHOD AND DEVICE FOR RESTRAINING MOVEMENT OF CONTINUOUSLY TRAVELING GLASS SHEET - A sheet restrainer is used to restrain movement of continuously traveling glass sheet and includes arms on either side of the glass sheet. A driving device coupled to the arms moves the arms from a retracted position in which the arms are withdrawn from the glass sheet to an engaged position in which the arms are near the glass sheet and in alignment with each other. Rollers are connected to the arms and contact the glass sheet in the engaged position. A damping device applies an adjustable damping force to at least one of the arms dampening movement of the arm in the engaged position thereby restraining movement of the sheet. In a method of operation, the damping devices restrain angular and/or lateral movement of the sheet by transmitting movement of the sheet against the rollers into a resistive damping force of the damping devices. | 10-14-2010 |
20110017713 | Methods and Apparatus for Initiating Scoring - Methods and apparatus are provided for forming an initiation flaw ( | 01-27-2011 |
20140041503 | METHODS AND APPARATUS FOR INITIATING SCORING - Methods and apparatus are provided for forming an initiation flaw ( | 02-13-2014 |
20140143996 | METHODS OF FORMING GRADIENT INDEX (GRIN) LENS CHIPS FOR OPTICAL CONNECTIONS AND RELATED FIBER OPTIC CONNECTORS - Gradient index (GRIN) lens chips for optical connections, and related methods of creating GRIN lens chips are disclosed. Each GRIN lens chip may include at least one GRIN lens and a GRIN lens holder for aligning the GRIN lens in an optical connection. When creating a GRIN lens chip, a shaped substrate may be provided including a GRIN lens holder and at least one GRIN groove for securing and aligning the GRIN lens relative to the GRIN lens holder. The GRIN lens may be part of a GRIN lens rod. By freeing the GRIN lens holder from the shaped substrate, the GRIN lens holder may include a fiber mating surface and a terminal mating surface. The fiber mating surface and the terminal mating surface may be used to align the GRIN lens holder in the optical connection. | 05-29-2014 |
20140147078 | GRADIENT INDEX (GRIN) LENS CHIPS AND ASSOCIATED SMALL FORM FACTOR OPTICAL ARRAYS FOR OPTICAL CONNECTIONS, RELATED FIBER OPTIC CONNECTORS - Gradient index (GRIN) lens chips and associated small form factor optical arrays for optical connections, and related fiber optic connectors are disclosed. By aligning GRIN lenses within a GRIN lens chip, a more precise and reliable alignment may be achieved with respect to optical fibers than if a single conventional ferrule is utilized to align and secure both GRIN lenses and optical fibers. The GRIN lens chip may include a GRIN lens received and thereby aligned within a groove disposed between a fiber end and a terminal end of a GRIN lens holder body. The optical fibers may also be received and thereby aligned within a groove of a ferrule body. In this manner, when the GRIN lens chip containing the GRIN lenses is aligned with a ferrule body containing the optical fibers, then the GRIN lenses may be precisely located relative to the optical fibers. | 05-29-2014 |
20140174132 | ROLLER PAIRS FOR PROCESSING GLASS RIBBONS AND DRAW APPARATUSES INCORPORATING THE SAME - Roller pairs and draw apparatus for processing glass ribbons are disclosed. The roller pairs applying force to a glass ribbon moving through the draw apparatus. The roller pairs include a first roller assembly and a second roller assembly positioned along opposite sides of the glass ribbon. A shaft of the second roller assembly is coupled to an actuation system that includes a repositionable support member allowing translation of the shaft of the second roller assembly in a direction transverse to the draw direction of the glass ribbon, a pneumatic actuator controlling a position of the contact wheel of the second roller assembly in the direction transverse to the draw direction of the glass ribbon, and a pneumatic reservoir in fluid communication with the pneumatic actuator delivering fluid at an elevated pressure to the pneumatic actuator. | 06-26-2014 |
Patent application number | Description | Published |
20110090220 | ORDER-PRESERVING DISTRIBUTED RASTERIZER - One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock. | 04-21-2011 |
20130070760 | SYSTEM AND METHOD FOR USING DOMAINS TO IDENTIFY DEPENDENT AND INDEPENDENT OPERATIONS - One embodiment of the present invention is a control unit for distributing packets of work to one or more consumer of works. The control unit is configured to assign at least one processing domain from a set of processing domains to each consumer included in the one or more consumers, receive a plurality of packets of work from at least one producer of work, wherein each packet of work is associated with a processing domain from the set of processing domains, and a first packet of work associated with a first processing domain can be processed by the one or more consumers independently of a second packet of work associated with a second processing domain, identify a first consumer that has been assigned the first processing domain, and transmit the first packet of work to the first consumer for processing. | 03-21-2013 |
20130117751 | COMPUTE TASK STATE ENCAPSULATION - One embodiment of the present invention sets forth a technique for encapsulating compute task state that enables out-of-order scheduling and execution of the compute tasks. The scheduling circuitry organizes the compute tasks into groups based on priority levels. The compute tasks may then be selected for execution using different scheduling schemes. Each group is maintained as a linked list of pointers to compute tasks that are encoded as task metadata (TMD) stored in memory. A TMD encapsulates the state and parameters needed to initialize, schedule, and execute a compute task. | 05-09-2013 |
20130120412 | METHOD FOR HANDLING STATE TRANSITIONS IN A NETWORK OF VIRTUAL PROCESSING NODES - One embodiment of the present invention sets forth a technique for executing an operation once work associated with a version of a state object has been completed. The method includes receiving the version of the state object at a first stage in a processing pipeline, where the version of the state object is associated with a reference count object, determining that the version of the state object is relevant to the first stage, incrementing a counter included in the reference count object, transmitting the version of the state object to a second stage in the processing pipeline, processing work associated with the version of the state object, decrementing the counter, determining that the counter is equal to zero, and in response, executing an operation specified by the reference count object. | 05-16-2013 |
20130120413 | METHOD FOR HANDLING STATE TRANSITIONS IN A NETWORK OF VIRTUAL PROCESSING NODES - One embodiment of the present invention sets forth a technique for receiving versions of state objects at one or more stages in a processing pipeline. The method includes receiving a first version of a state object at a first stage in the processing pipeline, determining that the first version of the state object is relevant to the first stage, incrementing a first reference counter associated with the first version of the state object, assigning the first version of the state object to work requests that arrive at the first stage subsequent to the receipt of the first version of the state object, and transmitting the first version of the state object to a second stage in the processing pipeline. | 05-16-2013 |
20130152093 | Multi-Channel Time Slice Groups - A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units. | 06-13-2013 |
20130160021 | SIGNALING, ORDERING, AND EXECUTION OF DYNAMICALLY GENERATED TASKS IN A PROCESSING SYSTEM - One embodiment of the present invention sets forth a technique for enabling the insertion of generated tasks into a scheduling pipeline of a multiple processor system allows a compute task that is being executed to dynamically generate a dynamic task and notify a scheduling unit of the multiple processor system without intervention by a CPU. A reflected notification signal is generated in response to a write request when data for the dynamic task is written to a queue. Additional reflected notification signals are generated for other events that occur during execution of a compute task, e.g., to invalidate cache entries storing data for the compute task and to enable scheduling of another compute task. | 06-20-2013 |
20130198759 | CONTROLLING WORK DISTRIBUTION FOR PROCESSING TASKS - A technique for controlling the distribution of compute task processing in a multi-threaded system encodes each processing task as task metadata (TMD) stored in memory. The TMD includes work distribution parameters specifying how the processing task should be distributed for processing. Scheduling circuitry selects a task for execution when entries of a work queue for the task have been written. The work distribution parameters may define a number of work queue entries needed before a cooperative thread array” (“CTA”) may be launched to process the work queue entries according to the compute task. The work distribution parameters may define a number of CTAS that are launched to process the same work queue entries. Finally, the work distribution parameters may define a step size that is used to update pointers to the work queue entries. | 08-01-2013 |
20140152652 | ORDER-PRESERVING DISTRIBUTED RASTERIZER - One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock. | 06-05-2014 |
Patent application number | Description | Published |
20110302385 | MEMORY DEVICE SYNCHRONIZATION - A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively. | 12-08-2011 |
20120026175 | HIERARCHICAL PROCESSOR ARRAY - Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component. | 02-02-2012 |
20140032828 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR COPYING DATA BETWEEN MEMORY LOCATIONS - A system, method, and computer program product are provided for copying data between memory locations. In use, a memory copy instruction is implemented. Additionally, data is copied from a first memory location to a second memory location, utilizing the memory copy instruction. | 01-30-2014 |