Patent application number | Description | Published |
20100178747 | Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme - Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed. | 07-15-2010 |
20110095395 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 04-28-2011 |
20130071983 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 03-21-2013 |
20130161792 | SEMICONDUCTOR DEVICE HAVING TRENCH CAPACITOR STRUCTURE INTEGRATED THEREIN - Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate. The substrate includes multiple capacitor regions, such as a first capacitor region and a second capacitor region that are adjacent to one another. Each capacitor region includes trenches that are formed within the substrate. A metal-insulator-metal capacitor is formed within the trenches and at least partially over the substrate. The trenches disposed within the first capacitor region are at least substantially perpendicular to the trenches disposed within the second capacitor region. | 06-27-2013 |
20130175666 | SEMICONDUCTOR DEVICE HAVING CAPACITOR INTEGRATED THEREIN - Semiconductor devices are described that include a capacitor integrated therein. In an implementation, the semiconductor devices include a substrate including a dopant material of a first conductivity type. A plurality of trenches are formed within the substrate. The semiconductor devices also include a diffusion region having dopant material of a second conductivity type formed proximate to the trenches. A capacitor is formed within the trenches and at least partially over the substrate. The capacitor includes at least a first electrode, a second electrode, and a dielectric material formed between the first and second electrodes. | 07-11-2013 |
20140252655 | FAN-OUT AND HETEROGENEOUS PACKAGING OF ELECTRONIC COMPONENTS - Aspects of the disclosure pertain to a packaging structure configured for providing heterogeneous packaging of electronic components and a process for making same. The packaging structure includes a carrier substrate having a plurality of cavities formed therein. The packaging structure further includes a first die and a second die. The first die is at least substantially contained within a first cavity included in the plurality of cavities. The second die is at least substantially contained within a second cavity included in the plurality of cavities. The first die is fabricated via a first fabrication technology, and the second die is fabricated via a second fabrication technology, the second fabrication technology being different than the first fabrication technology. The packaging structure also includes electrical interconnect circuitry connected to (e.g., for electrically connecting) the first die, the second die and/or the carrier substrate. | 09-11-2014 |
20140264711 | LIGHT SENSOR WITH VERTICAL DIODE JUNCTIONS - Light sensors are described that include a trench structure integrated therein. In an implementation, the light sensor includes a substrate having a dopant material of a first conductivity type and multiple trenches disposed therein. The light sensor also includes a diffusion region formed proximate to the multiple trenches. The diffusion region includes a dopant material of a second conductivity type. A depletion region is created at the interface of the dopant material of the first conductivity type and the dopant material of the second conductivity type. The depletion region is configured to attract charge carriers to the depletion region, at least substantially a majority of the charge carriers generated due to light incident upon the substrate. | 09-18-2014 |
20150155264 | TECHNIQUES FOR ADHESIVE CONTROL BETWEEN A SUBSTRATE AND A DIE - Semiconductor devices are described that employ techniques configured to control adhesive application between a substrate and a die. In an implementation, a sacrificial layer is provided on a top surface of the die to protect the surface, and bonds pads thereon, from spill-over of the adhesive. The sacrificial layer and spill-over adhesive are subsequently removed from the die and/or chip carrier. In an implementation, the die includes a die attach film (DAF) on a bottom surface of the die for adhering the die to the cavity of the substrate. The die is applied to the cavity with heat and pressure to cause a portion of the die attach film (DAF) to flow from the bottom surface of the die to a sloped surface of the substrate cavity. | 06-04-2015 |
20150262944 | WAFER-BASED ELECTRONIC COMPONENT PACKAGING - A surface mount device includes at least one semiconductor device including an exposed top metal, an encapsulation layer partially encapsulating the at least one semiconductor device, and at least one end-termination cap on the surface mount device resulting in an electrical connection from a first side of the surface mount device to a second side of the surface mount device. In implementations, one process for fabricating the surface mount device includes dicing a finished device wafer in a scribe-line region, applying tape to a first side of the finished device wafer, backgrinding a second side of the finished device wafer, encapsulating the second side of the finished device wafer with an encapsulation layer, singulating the finished device wafer, and forming at least one wrap-around connection from a first side of the surface mount device to a second side of the surface mount device. | 09-17-2015 |
Patent application number | Description | Published |
20100065901 | Electrically programmable and erasable memory device and method of fabrication thereof - The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride. | 03-18-2010 |
20100123178 | High ultraviolet light absorbance silicon oxynitride film for improved flash memory device performance - An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain. | 05-20-2010 |
20140124848 | ELECTRICALLY PROGRAMMABLE AND ERASEABLE MEMORY DEVICE - The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. | 05-08-2014 |