Torack
Ellen Torack, St. Louis, MO US
Patent application number | Description | Published |
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20150378372 | SYSTEMS AND METHODS FOR CONTROLLING TEMPERATURES IN AN EPITAXIAL REACTOR - A method for controlling temperatures in an epitaxial reactor for use in a wafer-production process is provided. The method is implemented by a computing device coupled to a memory. The method includes transmitting, to a heating device in a first zone of the epitaxial reactor, an output power instruction representing a base output power. The method additionally includes determining an actual time period for a temperature in the first zone of the epitaxial reactor to reach a target temperature, determining a difference between the actual time period and a reference time period, determining an output power offset based on the difference, and storing the output power offset in the memory in association with the heating device. | 12-31-2015 |
Thomas A. Torack, Oakland, MO US
Patent application number | Description | Published |
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20080314319 | SUSCEPTOR FOR IMPROVING THROUGHPUT AND REDUCING WAFER DAMAGE - A susceptor for supporting a semiconductor wafer in a heated chamber having an interior space. The susceptor includes a body having an upper surface and a lower surface opposite the upper surface. The susceptor also has a recess extending downward from the upper surface into the body along an imaginary central axis. The recess is sized and shaped for receiving the semiconductor wafer therein. The susceptor includes a plurality of lift pin openings extending through the body from the recess to the lower surface. Each of the lift pin openings is sized for accepting lift pins to selectively lift and lower the wafer with respect to the recess. The susceptor has a central opening extending through the body along the central axis from the recess to the lower surface. | 12-25-2008 |
20100065696 | WAFER HOLDER FOR SUPPORTING A SEMICONDUCTOR WAFER DURING A THERMAL TREATMENT PROCESS - A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports. | 03-18-2010 |
20110159668 | Methods For Processing Silicon On Insulator Wafers - Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited. | 06-30-2011 |
Thomas A. Torack, St. Louis, MO US
Patent application number | Description | Published |
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20110148128 | Semiconductor Wafer Transport System - A system and a wand are disclosed for the transport of a semiconductor wafer. The system and wand include a plate and a locator. The plate includes a plurality of plate outlets for directing gas flow against the wafer to hold the wafer using the Bernoulli principle. The locator extends from the plate and includes a locating outlet for directing a gas flow to locate the wafer laterally relative to the plate. The plate outlets and the locating outlet operate to prevent the wafer from contacting the plate or the locator. In some embodiments, a plurality of locators are used to locate the wafer laterally relative to the plate. | 06-23-2011 |