Topaloglu
Ilim Topaloglu, Schweinfurt DE
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20140072250 | BEARING ASSEMBLY, FAN, AND METHOD FOR GUIDING A SHAFT - A bearing assembly includes a bearing formed to at least radially guide a shaft, a seat for the bearing, an annular gap around the bearing between the bearing and the seat that allows the bearing to undergo a movement perpendicular to an axis of the bearing, a magnetorheological fluid in the gap and a magnetic field source configured to subject the magnetorheological fluid to a magnetic field. Also, a method of controlling a strength of the magnetic field generated by the magnetic field source to control a viscosity of the magnetorheological fluid and affect an operating condition of the bearing assembly. | 03-13-2014 |
Rasit Topaloglu, Santa Clara, CA US
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20090097186 | DENSITY-CONFORMING VERTICAL PLATE CAPACITORS EXHIBITING ENHANCED CAPACITANCE AND METHODS OF FABRICATING THE SAME - Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor. | 04-16-2009 |
20120204134 | METHODS FOR FABRICATING AN ELECTRICALLY CORRECT INTEGRATED CIRCUIT - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a logical design for the semiconductor device and comparing an element in the logical design to a library of element patterns. The library of element patterns is derived by identifying layout patterns having electrical properties that deviate from modeled properties; the library also includes a quantitative measure of deviation from the modeled properties. In response to the comparing and with consideration of the quantitative measure, a determination is made as to whether the element is acceptable in the logical design. A mask set is generated that implements the logical design using either the element or a modified element if the element is not acceptable, and the mask set is employed to implement the logical design in and on a semiconductor substrate. | 08-09-2012 |
Rasit O. Topaloglu, Santa Clara, CA US
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20090072316 | DOUBLE LAYER STRESS FOR MULTIPLE GATE TRANSISTORS - Multiple gate transistors are provided with a dual stress layer for increased channel mobility and enhanced effective and saturated drive currents. Embodiments include transistors comprising a first stress layer under the bottom gate and a second stress layer overlying the top gate. Embodiments further include transistors with the bottom gate within or through the first stress layer. Methodology includes sequentially depositing stressed silicon nitride, nitride, oxide, amorphous silicon, and oxide layers on a substrate having a bottom oxide layer thereon, patterning to define a channel length, depositing a top nitride layer, patterning stopping on the stressed silicon nitride layer, removing the amorphous silicon layer, epitaxially growing silicon through a window in the substrate to form source, drain, and channel regions, doping, removing the deposited nitride and oxide layers, growing gate oxides, depositing polysilicon to form gates, growing isolation oxides, and depositing the top stress layer. | 03-19-2009 |
20090094013 | TWO-STEP SIMULATION METHODOLOGY FOR AGING SIMULATIONS - The present invention is a method and system for simulating the aging process of a circuit. A two-step process is employed whereby, in a first simulation step, a simulation is conducted to obtain node voltages for the original circuit and the node voltages are stored in a file. In the second step, a subsequent simulation is run after transistors of the circuit are replaced by aging subcircuits, which contain aging models, and initial node voltages are updated. A script is used to set the bias voltage inputs for the aging models using the node voltages stored in the file from the first step. With more accurate bias voltage inputs for the aging models, the aging simulations are conducted to compute the circuit degradation. | 04-09-2009 |
20100107166 | SCHEDULER FOR PROCESSOR CORES AND METHODS THEREOF - A data processing device assigns tasks to processor cores in a more distributed fashion. In one embodiment, the data processing device can schedule tasks for execution amongst the processor cores in a pseudo-random fashion. In another embodiment, the processor core can schedule tasks for execution amongst the processor cores based on the relative amount of historical utilization of each processor core. In either case, the effects of bias temperature instability (BTI) resulting from task execution are distributed among the processor cores in a more equal fashion than if tasks are scheduled according to a fixed order. Accordingly, the useful lifetime of the processor unit can be extended. | 04-29-2010 |
20130027127 | INTEGRATED CIRCUIT SYSTEMS INCLUDING VERTICAL INDUCTORS - An integrated circuit system is provided that includes a circuit function in and on a surface of a semiconductor substrate. First and second portions of an inductor overlie the surface of the semiconductor substrate and each is coupled to the first circuit function. A third portion of the inductor is positioned on a second substrate. A first through substrate via (TSV) extends through the semiconductor substrate and electrically couples the first portion to the third portion and a second TSV extends through the semiconductor substrate and electrically couples the second portion to the third portion. | 01-31-2013 |
Rasit O. Topaloglu, Poughkeepsie, NY US
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20140284813 | INTERCONNECT LEVEL STRUCTURES FOR CONFINING STITCH-INDUCED VIA STRUCTURES - A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts. | 09-25-2014 |
Rasit Onur Topaloglu, Santa Clara, CA US
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20090099829 | INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM FOR NONLINEAR MOBILITY MODEL FOR STRAINED DEVICE - A method for operating an integrated circuit tester information processing system includes: measuring current information from test structures for an integrated circuit having a stress liner; forming a transfer curve by simulating based on the current information with a first range of first mobility multipliers; forming an inverse transfer curve by applying an inverse transfer function to the transfer curve; forming a stress curve with second mobility multipliers from the inverse curve; and validating the second mobility multipliers by comparing a measured curve and a simulated curve with the measured curve based on the current information and the simulated curve based on stress curve. | 04-16-2009 |