Patent application number | Description | Published |
20080258303 | Novel structure for reducing low-k dielectric damage and improving copper EM performance - A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a dielectric layer; a chemical mechanical polish (CMP) stop layer on the dielectric layer; a conductive wiring in the dielectric layer; and a metal cap over the conductive wiring. | 10-23-2008 |
20080277797 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 11-13-2008 |
20090091038 | AIR GAP FOR INTERCONNECT APPLICATION - The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer. | 04-09-2009 |
20090286394 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 11-19-2009 |
20100123224 | HIGH MECHANICAL STRENGTH ADDITIVES FOR POROUS ULTRA LOW-K MATERIAL - A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group. | 05-20-2010 |
20100203722 | Semiconductor Device Having a Second Level of Metallization Formed over a First Level with Minimal Damage to the First Level and Method - A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage. | 08-12-2010 |
20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110115088 | INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER - An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion. | 05-19-2011 |
20110217840 | Method for Forming Self-Assembled Mono-Layer Liner for Cu/Porous Low-k Interconnections - A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon. | 09-08-2011 |
20110223762 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-15-2011 |
20120074535 | LOW DIELECTRIC CONSTANT MATERIAL - The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH | 03-29-2012 |
20130069234 | STRUCTURE AND METHOD FOR TUNABLE INTERCONNECT SCHEME - The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively. | 03-21-2013 |