Patent application number | Description | Published |
20100274988 | Flexible vector modes of operation for SIMD processor - In addition to the usual modes of SIMD processor operation, where corresponding elements of two source vector registers are used as input pairs to be operated upon by the execution unit, or where one element of a source vector register is broadcast for use across the elements of another source vector register, the new system provides several other modes of operation for the elements of one or two source vector registers. Improving upon the time-costly moving of elements for an operation such as DCT, the present invention defines a more general set of modes of vector operations. In one embodiment, these new modes of operation use a third vector register to define how each element of one or both source vector registers are mapped, in order to pair these mapped elements as inputs to a vector execution unit. Furthermore, the decision to write an individual vector element result to a destination vector register, for each individual element produced by the vector execution unit, may be selectively disabled, enabled, or made to depend upon a selectable condition flag or a mask bit. | 10-28-2010 |
20110087859 | SYSTEM CYCLE LOADING AND STORING OF MISALIGNED VECTOR ELEMENTS IN A SIMD PROCESSOR - The present invention provides efficient transfer of misaligned vector elements between a vector register file and data memory in a single clock cycle. One vector register of N elements can be loaded from memory with any memory element address alignment during a single clock cycle of the processor. Also, a partial segment of vector register elements can be loaded into a vector register in a single clock cycle with any element alignment from data memory. The present invention comprises properly partitioned multiple multi-port data memory modules in conjunction with a crossbar and address generation circuit. A preferred embodiment of the present invention uses a dual-issue processor containing both a RISC-type scalar processor and a vector/SIMD processor, whereby one scalar and one SIMD instruction are executed every clock cycle, and the RISC processor handles program flow control and also loading and storing of vector registers. | 04-14-2011 |
20130212353 | System for implementing vector look-up table operations in a SIMD processor - The present invention incorporates a system for vector Look-Up Table (LUT) operations into a single-instruction multiple-data (SIMD) processor in order to implement plurality of LUT operations simultaneously, where each of the LUT contents could be the same or different. Elements of one or two vector registers are used to form LUT indexes, and the output of vector LUT operation is written into a vector register. No dedicated LUT memory is required; rather, data memory is organized as multiple separate data memory banks, where a portion of each data memory bank is used for LUT operations. For a single-input vector LUT operation, the address input of each LUT is operably coupled to any of the input vector register's elements using input vector element mapping logic in one embodiment. Thus, one input vector element can produce (a positive integer) N output elements using N different LUTs, or (another positive integer) K input vector elements can produce N output elements, where K is an integer from one to N. | 08-15-2013 |
20130212355 | Conditional vector mapping in a SIMD processor - The present invention provides a method for mapping input vector register elements to output vector register elements in one step in relation to a control vector register controlling vector-to-vector mapping and condition code values. The method includes storing an input vector having N-elements of input data in a vector register and storing a control vector having N-elements in a vector register, and providing for enabling vector-to-vector mapping where the mask bit is not set to selectively disable. The masking of certain elements is useful to partition large mappings of vectors or matrices into sizes that fits the number of elements of a given SIMD, and merging of multiple mapped results together. This method and system provides a highly efficient mechanism of mapping vector register elements in parallel based on a user-defined mapping and prior calculated condition codes, and merging these mapped vector elements with another vector using a mask. | 08-15-2013 |
20140139655 | DRIVER DISTRACTION AND DROWSINESS WARNING AND SLEEPINESS REDUCTION FOR ACCIDENT AVOIDANCE - The present invention relates to a vehicle telematics device for driver monitoring for accident avoidance for drowsiness and distraction conditions. The distraction and drowsiness is detected by facial processing of driver's face and pose tracking as a function of speed and maximum allowed travel distance, and issuing a driver alert when a drowsiness or distraction condition is detected. The mitigation includes audible alert, as well as other methods such as dim blue night to perk up the driver. Adaptation center of driver's gaze direction and allowed maximum time for a given driver and camera angle offset as well as temporary offset for cornering for shift of vanishing point and other conditions is also performed. | 05-22-2014 |
20140300739 | VEHICLE SECURITY WITH ACCIDENT NOTIFICATION AND EMBEDDED DRIVER ANALYTICS - The present invention relates to a vehicle telematics device with one or more cameras embedded in the same package for evidentiary surround audio-video recording, automatic accident detection and emergency help request notification, facial processing for drowsiness and distraction accident avoidance, and embedded multiple profiles of driver analytics, and mobile internet connectivity for contacting emergency services directly and without the delay of a call center and for mobile hot spot for in-vehicle infotainment. Each profile of driver analytics has many selectable advanced driver analysis parameters and multiple profiles can be active for a given driver. In case of emergency help request accident panoramic accident video is uploaded to a cloud drop box and link to video of accident is available along with severity index, location, nearest address, number of passengers, etc. | 10-09-2014 |
Patent application number | Description | Published |
20090276606 | METHOD AND SYSTEM FOR PARALLEL HISTOGRAM CALCULATION IN A SIMD AND VLIW PROCESSOR - The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where the SIMD processor could perform N LUT operations per instruction. Histogram operation is partitioned into a vector LUT operation, followed by vector increment, vector LUT update, and at the end by reduction of vector histogram components. The present invention could be used for intensity, RGBA, YUV, and other type of multi-component images. | 11-05-2009 |
20090316798 | AUDIO AND VIDEO PROCESSING APPARATUS - The present invention performs video and audio compression/decompression, video input and output scaling, video input and output processing for enhancement, and system layer functions on a single semiconductor chip. The media processor is compromised of video processor with a SIMD vector engine, audio processor, stream processor, system processor, and video scalers, LUTs and hardware blender. Unified memory architecture is used where these four processors use a shared memory for data and instructions. Data transfers between multiple processors use multiple packet-based unidirectional communication channels via hardware-assisted circular queues in unified memory. The video processor is a SIMD processor coupled to a regular RISC processor as a dual-issue processor. Such integrated and programmable functionality provides implementation of multiple video and audio for compression standards and programmable video enhancement. Important applications of this include Digital TV, IP Video Phone, and Digital Camcorder/Camera. | 12-24-2009 |
20110072065 | Method for efficient DCT calculations in a programmable processor - The present invention relates to a efficient implementation of integer and fractional 8-length or 4-length, or 8×8 or 4×4 DCT in a SIMD processor as part of MPEG and other video compression standards. | 03-24-2011 |
20110072236 | Method for efficient and parallel color space conversion in a programmable processor - The present invention relates to an efficient implementation of color space conversion in a SIMD processor as part of converting output of video decompression to interface to a display unit. | 03-24-2011 |
20110072238 | Method for variable length opcode mapping in a VLIW processor - The present invention provides a method for reducing program memory size required for a dual-issue processor with a scalar processor plus a SIMD vector processor. Coding the map of next group of instruction pairs in a no-operation (NOP) instruction of scalar and vector processor reduces the cases where one of the scalar or vector opcode being a NOP opcode. NOP for either scalar or vector processor defines the next 13 instructions as scalar-plus-vector, scalar-followed-by-scalar, or vector-followed-by-vector so that execution unit performs accordingly until next NOP or a branch instruction. | 03-24-2011 |
20120307049 | Networked security camera with local storage and continuous recording loop - A networked surveillance audio-video recorder for security applications with local storage and continuous record loop using high-definition video and encrypted data is described. Evidentiary audio-video is locally stored on a non-volatile storage media, and later transmitted in accordance with channel bandwidth with optional temporal, spatial or peak signal-to-noise ratio (PSNR) scalability and in accordance to display capabilities of target viewing device upon request of time regions of interest or window around alarm trigger events, or for periodic archival reasons. | 12-06-2012 |
20120307050 | Mobile security audio-video recorder with local storage and continuous recording loop - An internet connected mobile security system for recording at least one audio and video on a removable semiconductor storage media in a continuous record loop for evidentiary documentation purposes inside an automotive vehicle or as a wearable video recording device is described. | 12-06-2012 |
20130212354 | Method for efficient data array sorting in a programmable processor - The present invention provides a method for performing data array sorting of vector elements in a N-wide SIMD that is accelerated by a factor of about N/2 over scalar implementation excluding scalar load/store instructions. A vector compare instruction with ability to compare any two vector elements in accordance to optimized data array sorting algorithms, followed by a vector-multiplex instruction which performs exchanges of vector elements in accordance with condition flags generated by the vector compare instruction provides an efficient but programmable method of performing data sorting with a factor of about N/2 acceleration. A mask bit prevents changes to elements which is not involved in a certain stage of sorting. | 08-15-2013 |