Tian, TX
Aibo Tian, Austin, TX US
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20120257830 | SYSTEM AND METHOD FOR DETERMINING THE INFORMATIVE ZONE OF AN IMAGE - A system and a method are disclosed that determine the informative zone of an image. A system and method include receiving image data representative of an image, determining the non-redundant regions of the image based on analysis of patterns of the image data, and determining an area of the image that encompasses the non-redundant regions of the image as the informative zone of the image. | 10-11-2012 |
20120257842 | SYSTEM AND METHOD FOR DETERMINING IMAGE PLACEMENT ON A CANVAS - A system and a method are disclosed that determine placement of a background image on a canvas and area for placement of foreground images. A system and method include receiving data indicative of an informative zone of a background image and computing an estimated foreground area on a canvas for each candidate placement of the background image on the canvas. The estimated foreground area is computed based on the data indicative of the informative zone and the number of images to be used as foreground images and does not include the informative zone. One of the candidate placements is determined as a selected background placement based on the computed values of estimated foreground area. A composite image can be generated from the background image positioned on the canvas according to the selected background placement and foreground images positioned outside of the informative zone. | 10-11-2012 |
Cechan Tian, Plano, TX US
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20090201564 | Monitoring Modulator Bias Using Photon Absorption - Monitoring a bias point of an optical modulator includes receiving an optical signal modulated by the optical modulator. Photons of the optical signal are received at a photon reactive material operable to produce a reaction in response to the arrival of a predetermined number of photons. Reactions are produced in response to the arrival of the photons of the optical signal. Feedback is generated in response to the reactions. The feedback reflects the waveform of the optical signal, and indicates one or more bias points of the optical modulator. | 08-13-2009 |
20110044698 | Free-Space DQPSK Demodulator - A demodulator comprises an input splitter, optical device sets, and couplers. The input splitter splits an input signal comprising symbols to yield a number of signals. A first optical device set directs a signal of along a first path. A second optical device set directs another signal along a second path to yield a delayed signal. At least a portion of the second path is in free space. A path length difference between the first path and the second path introduces a delay between the first signal and the second signal. A coupler receives a portion of the signal and a portion of the delayed signal to generate interference, where the interference indicates a phase shift between a phase corresponding to a symbol and a successive phase corresponding to a successive symbol. | 02-24-2011 |
Charles Yang Tian, Allen, TX US
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20130212469 | Web Reader for Readers with reading disabilities - A method and system for providing a web reader for people with reading disabilities. A web browser extension is included with a web browser add-on functionality that changes a web content hypersensitive marking code at real time to use a cascading style sheet specifically designed for people with a reading disability. | 08-15-2013 |
Hong Tian, Austin, TX US
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20150303246 | SYSTEMS AND METHODS FOR FABRICATING A POLYCRYSTALINE SEMICONDUCTOR RESISTOR ON A SEMICONDUCTOR SUBSTRATE - In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion. | 10-22-2015 |
Li Tian, Denton, TX US
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20080282423 | METHODS AND COMPOSITIONS FOR MODIFYING PLANT BIOSYNTHETIC PATHWAYS - The invention provides bifunctional plant biosynthetic enzymes that increase the efficiency by which modification can be made to plant biosynthetic pathways. In certain aspects of the invention, bifunctional isoflavone biosynthetic enzymes are provided. The invention therefore allows the modification of plants for isoflavone content. The inventors have demonstrated increased isoflavone biosynthesis can be obtained even in non-legume plants. | 11-13-2008 |
Peter Tian, Plano, TX US
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20100307041 | Light Emitting Diode LED Internally Illuminated Sign - An LED sign may include a top frame member, two side frame members connected to the top frame member, a bottom frame member connected to the side frame members. A first detachable outer sheet member may include indicia to cooperate with the top frame member, the bottom frame member and the side frame members. The LED sign may further include a second translucent sheet member to cooperate with the top frame member, the bottom frame member and the side frame members. The LED sign may further include a sign frame member. The LED sign may include LED lighting modules an LED photocell. The LED lighting modules may be detachably connected to the LED sign, and the top, bottom and side frame members may be substantially U-shaped to define a channel for the outer sheet member. | 12-09-2010 |
Qi Tian, Helotes, TX US
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20120109943 | Adaptive Image Retrieval Database - Adaptive image retrieval image allows retrieval of images that are more likely to reflect a current trend of user preferences and/or interests, and therefore can provide relevant results to an image search. Adaptive image retrieval includes receiving image query log data from one or more clients, and updating a codebook of features based on the received query log data. The image query log data includes images that have been queried by the one or more clients within a predetermined period of time. | 05-03-2012 |
20120114248 | Hierarchical Sparse Representation For Image Retrieval - A hierarchical sparse codebook allows efficient search and comparison of images in image retrieval. The hierarchical sparse codebook includes multiple levels and allows a gradual determination/classification of an image feature of an image into one or more groups or nodes by traversing the image feature through one or more paths to the one or more groups or nodes of the codebook. The image feature is compared with a subset of nodes at each level of the codebook, thereby reducing processing time. | 05-10-2012 |
20120117449 | Creating and Modifying an Image Wiki Page - An ImageWiki architecture is used to generate an image-based web page for an image on the Web. An ImageWiki page may be created automatically or individually, by a user of the Web. Additionally, a user may revise existing ImageWiki pages to update a particular page or correct an incorrect or misleading previous entry. The ImageWiki application indexes images located on the Web. Once the images are indexed, the information related to the images is mined and extracted from various sources of web data. Finally, an ImageWiki page or web page is generated for each image. The resulting ImageWiki page contains the image as well as the aggregated information relating to the image. | 05-10-2012 |
20140314324 | GEOMETRIC CODING FOR BILLION-SCALE PARTIAL-DUPLICATE IMAGE SEARCH - Most of large-scale image retrieval systems are based on Bag-of-Visual-Words model. However, traditional Bag-of-Visual-Words model does not well capture the geometric context among local features in images, which plays an important role in image retrieval. In order to fully explore geometric context of all visual words in images, efficient global geometric verification methods have been attracting lots of attention. Unfortunately, current existing global geometric verification methods are either computationally expensive to ensure real-time response. To solve the above problems, a novel geometric coding algorithm is used to encode the spatial context among local features for large scale partial duplicate image retrieval. With geometric square coding and geometric fan coding, our geometric coding scheme encodes the spatial relationships of local features into three geo-maps, which are used for global verification to remove spatially inconsistent matches. This approach is not only computationally efficient, but also effective in detecting duplicate images with rotation, scale changes, occlusion, and background clutter. | 10-23-2014 |
Qi Tian, Helotex, TX US
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20140133759 | Semantic-Aware Co-Indexing for Near-Duplicate Image Retrieval - An image retrieval method includes learning multiple object category classifiers with a processor offline and generating classifications scores of images as the semantic attributes; performing vocabulary tree based image retrieval using local features with semantic-aware co-indexing to jointly embed two distinct cues offline for near-duplicate image retrieval; and identifying top similar or dissimilar images using multiple semantic attributes. | 05-15-2014 |
Ruhai Tian, Irving, TX US
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20130291627 | FIN-FET SENSOR WITH IMPROVED SENSITIVITY AND SPECIFICITY - The claimed invention is directed to a fmFET biosensor with improved sensitivity and selectivity. Embodiments of the invention are also directed to finFET biosensor arrays, methods for operating fmFET biosensors with improved sensitivity and selectivity, and methods of operating finFET biosensor arrays. | 11-07-2013 |
Ruiqi Tian, Austin, TX US
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20080217714 | SEMICONDUCTOR DEVICE HAVING TILES FOR DUAL-TRENCH INTEGRATION AND METHOD THEREFOR - A method for forming a semiconductor device includes providing a semiconductor substrate having a first region and a second region. The first region has one or more first elements and the second region has one or more second elements. The first elements are different from the second elements. A tile location and a first tile surface area for a tile feature on the semiconductor device is defined. An active semiconductor layer is formed over both the first region and the second region of the semiconductor substrate. A first trench is formed in the active semiconductor layer at the tile location using a negative tone mask. The first trench has a first depth and forms at least a portion of the tile feature. A second trench is formed in the active semiconductor layer using a positive tone mask. The second trench has a second depth different than the first depth. | 09-11-2008 |
20090291547 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 11-26-2009 |
20110179394 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 07-21-2011 |
20110269300 | Integrated Assist Features for Epitaxial Growth - A method for making a semiconductor device is provided which comprises (a) creating a data set ( | 11-03-2011 |
Weidong Tian, Dallas, TX US
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20080277761 | ON-CHIP ISOLATION CAPACITORS, CIRCUITS THEREFROM, AND METHODS FOR FORMING THE SAME - An integrated circuit includes a substrate having a semiconducting surface, and at least one isolation capacitor on the surface. The capacitor includes a bottom electrically conductive plate in or on the surface, a multi-layer dielectric comprising stack over the bottom plate, and a top electrically conductive plate formed over the dielectric stack. The dielectric stack comprises at least one layer of silicon dioxide and at least one layer of silicon nitride, wherein the layer of silicon nitride is located immediately below or immediately above the top plate. | 11-13-2008 |
20100276783 | SELECTIVE PLASMA ETCH OF TOP ELECTRODES FOR METAL-INSULATOR-METAL (MIM) CAPACITORS - A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas. | 11-04-2010 |
20120098045 | Zero Temperature Coefficient Capacitor - A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×10 | 04-26-2012 |
20120292682 | Electrically Erasable Programmable Non-Volatile Memory - In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. | 11-22-2012 |
20130065374 | Fluorine Implant Under Isolation Dielectric Structures to Improve Bipolar Transistor Performance and Matching - A method of fabricating an integrated circuit including bipolar transistors that reduces the effects of transistor performance degradation and transistor mismatch caused by charging during plasma etch, and the integrated circuit so formed. A fluorine implant is performed at those locations at which isolation dielectric structures between base and emitter are to be formed, prior to formation of the isolation dielectric. The isolation dielectric structures may be formed by either shallow trench isolation, in which the fluorine implant is performed after trench etch, or LOCOS oxidation, in which the fluorine implant is performed prior to thermal oxidation. The fluorine implant may be normal to the device surface or at an angle from the normal. Completion of the integrated circuit is then carried out, including the use of relatively thick copper metallization requiring plasma etch. | 03-14-2013 |
20130143375 | On Current in One-Time-Programmable Memory Cells - A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I | 06-06-2013 |
20130143376 | CURRENT IN ONE-TIME-PROGRAMMABLE MEMORY CELLS - A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (I | 06-06-2013 |
20130256773 | ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY - In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. | 10-03-2013 |
Xiaoyang Tian, Austin, TX US
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20140108717 | System and Method to Backup Objects on an Object Storage Platform - A method and system enable tape back-up of objects stored to an object storage platform and also enable efficient backup to a secondary storage device data objects. An offline-replica bit within a metadata of an object being stored is set to a first value, indicating that the stored object is available for secondary storage to a second storage device. In response to receiving a request for backup of one or more objects from the object storage platform: the storage controller: identifies which objects have an offline-replica bit value that is the first value; and provides only those objects requested that have their offline-replica bit value equal to the first value. An external backup tracking mechanism identifies which objects have been backed-up to the secondary storage, and only those objects that have not previously been backed up are backed up during a subsequent backup request. | 04-17-2014 |