Patent application number | Description | Published |
20080286913 | FIELD EFFECT TRANSISTOR WITH RAISED SOURCE/DRAIN FIN STRAPS - Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures. | 11-20-2008 |
20090050975 | Active Silicon Interconnect in Merged Finfet Process - Dummy fins are positioned between source and drain regions of adjacent complementary multi-gate fin-type field effect transistors (MUGFETS) prior to selective silicon growth and silicidation. The dummy fins are parallel to, have the same thickness as, and have a smaller length than the fins within the MUGFETs. Further, the source regions of a first MUGFET, the drain regions of a second MUGFET, and the dummy fins are positioned along a single straight linear path, such that the single straight linear path crosses all of the source regions of the first MUGFET, the drain regions of the second MUGFET, and the dummy fins. Because the dummy fins comprise silicon, the dummy fins enhance the ability to selectively grow silicon within the source/drain connection silicide region. Then, after the source/drain connection silicide region is silicided, a consistently formed and reliable electrical connection is made between the source regions of one transistor and the drain regions of the other transistor to properly connect a CMOS structure. | 02-26-2009 |
20090089726 | Layout Quality Gauge for Integrated Circuit Design - A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality. | 04-02-2009 |
20090235215 | GRIDDED GLYPH GEOMETRIC OBJECTS (L3GO) DESIGN METHOD - A method of gridded glyph geometric objects (L3GO) integrated circuit (IC) design, wherein at least one inter-level connect in a L3GO circuit design is represented as a point matrix glyph (PMG) on a L3GO grid. Each PMG connects a pair of conductors on the next adjacent (above and below) layer and includes an array (one or two dimensional) of point glyphs contained within a cage. The point glyphs may have uniform size and may be on minimum pitch. Each PMG may also include a flange on the above and below layer. A default flange insures adequate coverage of cut shapes represented by the point glyphs. | 09-17-2009 |
20100037198 | PORT ASSIGNMENT IN HIERARCHICAL DESIGNS BY ABSTRACTING MACRO LOGIC - A method to reduce the problem complexity maintains a relatively high quality port assignment by abstracting local connections in the macro when performing the port assignment. This is done for netlength, congestion as well as timing. The internal netlist of the macro is abstracted in such a way that the optimization of the external interconnect can be done in an efficient manner. Three levels of abstractions are described. A first level optimizes the top level interconnect, a second level optimizes the top level and macro interconnects, while a third level optimizes the top level timing. | 02-11-2010 |
20110113395 | Method, Electronic Design Automation Tool, Computer Program Product, and Data Processing Program for Creating a Layout for Design Representation of an Electronic Circuit and Corresponding Port for an Electronic Circuit - A method for creating a layout for design representation of an electronic circuit with at least one port. The method includes segmenting the at least one port in the design representation into different regions, classifying the different regions of the at least one port according to timing and/or electronic and/or layout characteristics, assigning a priority for each classified region of the at least one port according to rules based on the timing and/or electronic and/or layout characteristics, and routing the design representation by accessing at least one of the classified regions of the port according to an order of the assigned priorities. | 05-12-2011 |
20110154283 | Shaping Ports in Integrated Circuit Design - A mechanism is provided for performing a detailed routing of a net joining ports in an integrated circuit. Extended port regions are created for the ports of the net of the integrated circuit, the extended port regions being shaped in such a way as to guarantee routing access to the ports. A wire corresponding to the net is then placed and the extended port regions of the ports are trimmed, thus identifying essential port regions required for connecting the wire to the ports and dispensable port regions not required for connecting the wire to the ports. The wiring resources are then updated by releasing the dispensable port regions so that the dispensable port regions no longer constitute parts of the ports. | 06-23-2011 |
20120060139 | Using Port Obscurity Factors to Improve Routing - An integrated circuit characterized by a netlist may be routed using a routing priority list that may be created using port obscurity factors. A port obscurity factor may indicate how difficult it may be to route to that port and may be calculated as being inversely proportional to the number of routing tracks that may be connectable to that port. Routing priorities for the nets of the netlist may then be created using the port obscurity factors of the ports in the net. Routing may then be done in the order determined by the routing priority list and the generated layout information stored in a computer useable medium. In some cases, routing may be performed using multiple routing passes where a new routing priority list may be calculated for each routing pass. | 03-08-2012 |