Patent application number | Description | Published |
20130019469 | Thin Foil Semiconductor Package - The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages. | 01-24-2013 |
20130021055 | SCAN TESTING SYSTEM, METHOD AND APPARATUS - Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible. | 01-24-2013 |
20130021833 | DIFFERENTIAL PLATE LINE SCREEN TEST FOR FERROELECTRIC LATCH CIRCUITS - Non-volatile latch circuits, such as in memory cells and flip-flops, that are constructed for reliability screening. The non-volatile latch circuits each include ferroelectric capacitors coupled to storage nodes, for example at the outputs of cross-coupled inverters. Separate plate lines are connected to the ferroelectric capacitors of the complementary storage nodes. A time-zero test of the latch stability margin is performed by setting a logic state at the storage nodes, then programming the state into the ferroelectric capacitors by polarization. After power-down, the plate lines are biased with a differential voltage relative to one another, and the latch is then powered up to attempt recall of the programmed state. The differential voltage disturbs the recall, and provides a measure of the cell margin and its later-life reliability. | 01-24-2013 |
20130024738 | METHOD AND APPARATUS FOR DEVICE ACCESS PORT SELECTION - The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure. | 01-24-2013 |
20130024739 | SELECTIVELY ACCESSING TEST ACCESS PORTS IN A MULTIPLE TEST ACCESS PORT ENVIRONMENT - A TAP linking module ( | 01-24-2013 |
20130026043 | Foil Plating for Semiconductor Packaging - Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution. | 01-31-2013 |
20130027804 | WRITE DATA SWITCHING FOR MAGNETIC DISK DRIVES - One embodiment of the invention includes a system for writing data onto a magnetic disk. An output driver provides a first write current through a first output transistor in a first state and provides a second write current through a second output transistor in a second state. The first and second write currents can be provided to a disk write head to store opposing binary values, respectively. A bias current generator switches a first bias current between an intermediate voltage node in the second state and a first control node in the first state, and switches a second bias current between the intermediate voltage node in the first state and a second control node in the second state. The first and second bias currents can be provided to set a bias voltage at the first and second control nodes to bias the first and second output transistors, respectively. | 01-31-2013 |
20130029457 | TCE Compensation for Package Substrates for Reduced Die Warpage Assembly - A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages. | 01-31-2013 |
20130031435 | SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT - An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation. | 01-31-2013 |
20130034937 | Exposed Die Package for Direct Surface Mounting - A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB. | 02-07-2013 |
20130037413 | CLAM SHELL TWO-PIN WAFER HOLDER FOR METAL PLATING - A clam shell wafer holder includes a base and a lid pivotally connected with the base by an integral hinge. The base includes a rotatable wafer support, and the lid includes a universal frame and a pin holder attachment spaced inwardly from the frame. Only two contact pins are formed in a wafer-facing surface of the pin holder attachment. The contact pins are manually aligned with and contact two points on a wafer when the lid is closed against the base. A method for holding a wafer for plating is provided using the disclosed holder apparatus. | 02-14-2013 |
20130038365 | Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer - A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time. | 02-14-2013 |
20130038480 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-14-2013 |
20130040413 | SEMICONDUCTOR THERMOCOUPLE AND SENSOR - Conventional “on-chip” or monolithically integrated thermocouples are very mechanically sensitive and are expensive to manufacture. Here, however, thermocouples are provided that employ different thicknesses of thermal insulators to help create thermal differentials within an integrated circuit. By using these thermal insulators, standard manufacturing processes can be used to lower cost, and the mechanical sensitivity of the thermocouple is greatly decreased. Additionally, other features (which can be included through the use of standard manufacturing processes) to help trap and dissipate heat appropriately. | 02-14-2013 |
20130040449 | ULTRAVIOLET ENERGY SHIELD FOR NON-VOLATILE CHARGE STORAGE MEMORY - An integrated circuit with non-volatile memory cells shielded from ultraviolet light by a shielding structure compatible with chemical-mechanical processing. The disclosed shielding structure includes a roof structure with sides; along each side are spaced-apart contact posts, each with a width on the order of the wavelength of ultraviolet light to be shielded, and spaced apart by a distance that is also on the order of the wavelength of ultraviolet light to be shielded. The contact posts may be provided in multiple rows, and extending to a diffused region or to a polysilicon ring or both. The multiple rows may be aligned with one another or staggered relative to one another. | 02-14-2013 |
20130042159 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 02-14-2013 |
20130042160 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 02-14-2013 |
20130042161 | LOW POWER TESTING OF VERY LARGE CIRCUITS - Plural scan test paths ( | 02-14-2013 |
20130043552 | INTEGRATED INFRARED SENSORS WITH OPTICAL ELEMENTS AND METHODS - An infrared (IR) radiation sensor device ( | 02-21-2013 |
20130043899 | PARALLEL SCAN DISTRIBUTORS AND COLLECTORS AND PROCESS OF TESTING INTEGRATED CIRCUITS - An integrated circuit ( | 02-21-2013 |
20130043905 | GLITCH FREE CLOCK SWITCHING CIRCUIT - A glitch free clock switching circuit includes a first enable synchronization logic that generates a first clock enable in response to a first enable from a first enable generation logic. The clock switching circuit includes a second enable synchronization logic that generates a second clock enable in response to a second enable from a second enable generation logic. A logic gate is coupled to an output of the second enable synchronization logic that selects the second clock signal as a logic gate output if the second enable is logic high. A priority multiplexer receives a first clock signal, the first enable and the logic gate output. The multiplexer configured to select the first clock signal as the clock output if the first enable is logic high, irrespective of the logic gate output. | 02-21-2013 |
20130044536 | ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS - An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array. | 02-21-2013 |
20130047048 | AUTOMATABLE SCAN PARTITIONING FOR LOW POWER USING EXTERNAL CONTROL - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 02-21-2013 |
20130062711 | MICROELECTROMECHANICAL SYSTEM HAVING MOVABLE ELEMENT INTEGRATED INTO SUBSTRATE-BASED PACKAGE - A semiconductor-centered MEMS device ( | 03-14-2013 |
20130063170 | TEST CIRCUIT ALLOWING PRECISION ANALYSIS OF DELTA PERFORMANCE DEGRADATION BETWEEN TWO LOGIC CHAINS - A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter. | 03-14-2013 |
20130063470 | SYSTEM AND METHOD TO GENERATE MULTIPRIMARY SIGNALS - System and method for generating multiprimary signals with optimization for bit depth for use in display devices. A preferred embodiment comprises converting an input color signal into an output color signal, wherein the number of colors in the output color signal is less than a number of colors used in a display system, when a weighting of the input color signal is less than a specified threshold, and converting the input color signal into an output color signal, wherein the number of colors in the output color signal is equal to the number of colors used in the display system, when the weighting of the input color signal is greater than the specified threshold. The use of fewer colors eliminates low bit depth colors, allowing increased dither quality in dimmer images. | 03-14-2013 |
20130064007 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 03-14-2013 |
20130064400 | SILICON MICROPHONE WITH INTEGRATED BACK SIDE CAVITY - An integrated circuit containing a capacitive microphone with a back side cavity located within the substrate of the integrated circuit. Access holes may be formed through a dielectric support layer at the surface of the substrate to provide access for etchants to the substrate to form the back side cavity. The back side cavity may be etched after a fixed plate and permeable membrane of the capacitive microphone are formed by providing etchants through the permeable membrane and through the access holes to the substrate. | 03-14-2013 |
20130067291 | HIGH SPEED DOUBLE DATA RATE JTAG INTERFACE - A process and apparatus provide a JTAG TAP controller ( | 03-14-2013 |
20130069081 | Layout Method To Minimize Context Effects and Die Area - An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor. | 03-21-2013 |
20130069168 | SRAM LAYOUT FOR DOUBLE PATTERNING - An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns. | 03-21-2013 |
20130069170 | ILLUMINATION AND DESIGN RULE METHOD FOR DOUBLE PATTERNED SLOTTED CONTACTS - An integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. A method for forming an integrated circuit with long rectangular contacts to active where the active contact length is 2 times or more larger than the width and with short rectangular contacts to transistor gates where the transistor gate contact length is less than about 3 times the width. | 03-21-2013 |
20130072020 | Method For Ensuring DPT Compliance for Auto-Routed Via Layers - A method of generating an integrated circuit with a DPT compatible via pattern using a reduced DPT compatible via design rule set. A reduced DPT compatible via design rule set. A method of forming an integrated circuit using a via pattern generated from a reduced DPT compatible design rule set. | 03-21-2013 |
20130073915 | TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT - The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure. | 03-21-2013 |
20130073916 | DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS - Connection circuitry couples scan test port (STP) circuitry to test access port (TAP) circuitry. The connection circuitry has inputs connected to scan circuitry control output leads from the TAP circuitry, a select input lead, and a clock input lead. The connection circuitry has outputs connected to a scan enable (SE) input lead, a capture select (CS) input lead, and the scan clock (CK) input lead of the STP circuitry. The connection circuitry includes a multiplexer having a control input connected with a clock select lead from the TAP circuitry, an input connected with a functional clock lead, an input connected with the clock input lead, an input connected with a Clock-DR lead from the TAP circuitry, an OFF lead, and an output connected with the scan clock input lead. | 03-21-2013 |
20130073917 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 03-21-2013 |
20130074028 | METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS - A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set. | 03-21-2013 |
20130074029 | Method To Ensure Double Patterning Technology Compliance In Standard Cells - An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells. | 03-21-2013 |
20130075910 | MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS - A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N | 03-28-2013 |
20130077196 | ESD Robust Level Shifter - An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage. | 03-28-2013 |
20130077356 | DC-DC CONVERTERS - A DC-DC converter includes a waveform generator that generates an output waveform for the DC-DC converter based on a DC input voltage. A rectifier rectifies the output waveform from the waveform generator to generate a rectified voltage for the DC-DC converter. A tank circuit having an inductor and a capacitor can be configured to have a resonant frequency that is correlated with a frequency of the output waveform, wherein the capacitor of the tank circuit also functions as a filter for the DC-DC converter. | 03-28-2013 |
20130077696 | Method and System for Lossless Coding Mode in Video Coding - A method for coding a video sequence is provided that includes encoding a portion of a picture in the video sequence in lossless coding mode, and signaling a lossless coding indicator in a compressed bit stream, wherein the lossless coding indicator corresponds to the portion of a picture and indicates whether or not the portion of the picture is losslessly coded. A method for decoding a compressed video bit stream is provided that includes determining that lossless coding mode is enabled, decoding a lossless coding indicator from the compressed video bit stream, wherein the lossless coding indicator corresponds to a portion of a picture in the compressed video bit stream and indicates whether or not the portion of the picture is losslessly coded, and decoding the portion of the picture in lossless coding mode when the lossless coding indicator indicates the portion of the picture is losslessly coded. | 03-28-2013 |
20130077776 | Method, System and Computer Program Product for Acoustic Echo Cancellation - In response to a first signal, a first sound wave is output. A second sound wave is received that includes an acoustic echo of the first sound wave. In response to the second sound wave, a second signal is output that cancels an estimate of the acoustic echo. The estimate of the acoustic echo is iteratively adapted to increase a statistical independence between the first and second signals, irrespective of whether a first voice is present in the first sound wave, and irrespective of whether a second voice is present in the second sound wave. | 03-28-2013 |
20130080495 | SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE - A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle. | 03-28-2013 |
20130080850 | SERIAL SCAN CHAIN IN A STAR CONFIGURATION - A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase. | 03-28-2013 |
20130082624 | LED DRIVER SYSTEMS AND METHODS - A light-emitting diode (LED) driver system includes a control circuit that provides a waveform for driving a power transistor to generate a regulated current through one or more LEDs, and an error amplifier that generates an output compensation signal based on a comparison of a desired regulated current and an actual regulated current through the one or more LEDs. The output compensation signal is used to set an output compensation voltage that sets the duty cycle of the waveform. The LED driver system further comprises a dimming control device configured during a dimming control mode to alternate between dimming-on time periods and dimming-off time periods, and a sample and hold switch having a first state for holding the output compensation voltage fixed during each dimming-off time period, and a second state for restoring the error amplifier to its previous dimming-on operating state upon returning to each subsequent dimming-on time period. | 04-04-2013 |
20130083163 | Perceptual Three-Dimensional (3D) Video Coding Based on Depth Information - A method for encoding a multi-view frame in a video encoder is provided that includes computing a depth quality sensitivity measure for a multi-view coding block in the multi-view frame, computing a depth-based perceptual quantization scale for a 2D coding block of the multi-view coding block, wherein the depth-based perceptual quantization scale is based on the depth quality sensitive measure and a base quantization scale for the 2D frame including the 2D coding block, and encoding the 2D coding block using the depth-based perceptual quantization scale. | 04-04-2013 |
20130083202 | Method, System and Computer Program Product for Reducing a Delay From Panning a Camera System - For reducing a delay from panning a camera system, an estimate is received of a physical movement of the camera system. In response to the estimate, a determination is made of whether the camera system is being panned. In response to determining that the camera system is not being panned, most effects of the physical movement are counteracted in a video sequence from the camera system. In response to determining that the camera system is being panned, most effects of the panning are preserved in the video sequence, while concurrently the video sequence is shifted toward a position that balances flexibility in counteracting effects of a subsequent physical movement of the camera system. | 04-04-2013 |
20130083789 | Clock Synchronization and Distributed Guard Time Provisioning - Embodiments provide a method to accommodate clock drift and guard time in a distributed fashion. A first device is adapted to communicate with a second device. A clock in the first device is synchronized to a clock in the second device using beacon or/and acknowledgement frames from the second device. A nominal guard time is computed that accounts for clock drift in the first and second devices during a nominal synchronization interval. An additional guard time is computed that accounts for clock drift in the first and second devices during an additional interval beyond the nominal synchronization interval. An available transmission interval is determined within an allocation interval for transmissions between the devices, wherein the beginning and/or the end of the available transmission interval are selected by accounting for the nominal guard time and/or the additional guard time. One or more frames are transmitted within the available transmission interval. | 04-04-2013 |
20130083790 | Clock Synchronization and Centralized Guard Time Provisioning - Embodiments of the invention provide a method to accommodate clock drift and guard time in a centralized fashion. In one embodiment, a first device is adapted to communicate with a second device. A clock in the first device is synchronized to a clock in the second device using beacon or/and acknowledgement frames received from the second device. A centralized guard time is calculated by the second device between two neighboring allocation intervals. The centralized guard time accounts for clock drift in the first and second devices during a nominal synchronization interval. An interval at least as long as the centralized guard time is provisioned by the second device between two neighboring allocation intervals. One or more frames are transmitted between the devices within the allocation intervals. | 04-04-2013 |
20130083834 | Power-Indexed Look-Up Table Design of Digital Pre-Distortion for Power Amplifiers with Dynamic Nonlinearities - This invention is a method of power amplifier digital pre-distortion which measures a current power level of the power amplifier, stores in a look up table entries consisting of a power level and a corresponding set of digital pre-distortion coefficients, selects a set of digital pre-distortion coefficients corresponding to the measured power level. If the measured current power level is near a power level index, the digital pre-distortion coefficients correspond to the power level index. If the measured current power level is greater than the maximum power level entry, the digital pre-distortion coefficients is of the maximum power level entry. If the measured current power level is less than the minimum power level entry, the digital pre-distortion is of the minimum power level entry. If the measured current power level is not near a power level index, the digital pre-distortion coefficients are an interpolation. | 04-04-2013 |
20130083972 | Method, System and Computer Program Product for Identifying a Location of an Object Within a Video Sequence - In response to detecting a motion within a video sequence, a determination is made of whether the motion is a particular type of movement. In response to determining that the motion is the particular type of movement, a location is identified within the video sequence of an object that does the motion. | 04-04-2013 |
20130083994 | Semi-Global Stereo Correspondence Processing With Lossless Image Decomposition - A method for disparity cost computation for a stereoscopic image is provided that includes computing path matching costs for external paths of at least some boundary pixels of a tile of a base image of the stereoscopic image, wherein a boundary pixel is a pixel at a boundary between the tile and a neighboring tile in the base image, storing the path matching costs for the external paths, computing path matching costs for pixels in the tile, wherein the stored path matching costs for the external paths of the boundary pixels are used in computing some of the path matching costs of some of the pixels in the tile, and computing aggregated disparity costs for the pixels in the tile, wherein the path matching costs computed for each pixel are used to compute the aggregated disparity costs for the pixel. | 04-04-2013 |
20130087880 | MEMS DEVICE AND METHOD OF MANUFACTURE - A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch. | 04-11-2013 |
20130087900 | Thermally Enhanced Low Parasitic Power Semiconductor Package - A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly. | 04-11-2013 |
20130088123 | SOFT MECHANICAL STOPS TO LIMIT OVER-TRAVEL OF PROOF MASSES IN CANTILEVERED PIEZOELECTRIC DEVICES - A piezoelectric device is disclosed which has a built-in soft stop which serves for protection against excessive force. | 04-11-2013 |
20130089124 | ADAPTIVE TONE POWER CONTROL IN PLC NETWORKS - In a powerline communications (PLC) network having a first node and at least a second node on a PLC channel utilizing a band including a plurality of tones, based on at least one channel quality indicator (CQI), the first node allocates for a tone map response payload only a single (1) power control bit for each of a plurality of subbands having two or more tones. The power control bit indicates a first power state or a second power state. The first node transmits a frame including the tone map response payload to the second node. The second node transmits a frame having boosted signal power for the tones in the subbands which have the first power state compared to a lower signal power for the tones in the subbands which have the second power state. | 04-11-2013 |
20130089139 | SYSTEMS AND METHODS FOR QUANTIZATION OF VIDEO CONTENT - Several methods, systems, and computer program products for quantization of video content are disclosed. In an embodiment, the method includes determining by a processing module, motion information associated with a block of video data of the video content. A degree of randomness associated with the block of video data is determined by the processing module based on the motion information. A value of a quantization parameter (QP) associated with the block of video data is modulated by a quantization module based on the determined degree of randomness. | 04-11-2013 |
20130089140 | METHODS AND SYSTEMS FOR ENCODING OF MULTIMEDIA PICTURES - Several methods and systems for encoding of multimedia pictures are disclosed. In an embodiment, an occupancy level of a coded picture buffer (CPB) associated with a hypothetical reference decoder (HRD) is estimated at an instant of removal of an access unit corresponding to a multimedia picture from the CPB for decoding the access unit. A number of bits for encoding the multimedia picture is allocated based on the estimated occupancy level of the CPB. The multimedia picture is encoded based on the allocated number of bits. | 04-11-2013 |
20130089141 | METHODS AND SYSTEMS FOR ENCODING PICTURES ASSOCIATED WITH VIDEO DATA - Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. The method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size. | 04-11-2013 |
20130089143 | Method, System, and Apparatus for Intra-Prediction in a Video Signal Processing - According to an aspect of the present disclosure, a video encoder selects a block of intermediate size from a set of block sizes for intra-prediction estimation for encoding a video signal. A set of neighbouring blocks with the intermediate size are tested for combining. If the set of neighbouring blocks are determined to be combinable, the video encoder selects a larger block size formed by the tested neighbouring blocks for encoding. On the other hand, if the set of neighbouring blocks are determined to be not combinable, the video encoder selects a smaller block size from the set of tested neighbouring blocks for prediction. According to another aspect of the present disclosure, the best mode for intra-prediction is determined by first intra-predicting a block with intermediate modes in a set of modes. Then the intra-predictions are performed for the neighbouring modes of at least one intermediate mode. | 04-11-2013 |
20130089148 | DETERMINATION OF A FIELD REFERENCING PATTERN - Several methods and a system to perform determination of a field referencing pattern are disclosed. In one aspect, a method is disclosed. A motion vector of a previously coded frame is analyzed using a processor and a memory. A statistic is updated based on whether the motion vector includes one or more of a fractional pel vertical component, a half pel vertical component, and an integer pel vertical component. A field referencing pattern of a target field is determined based on the statistic and an exception protocol. | 04-11-2013 |
20130089212 | Method and System for Hybrid Noise Cancellation - From a first microphone, first microphone signals are received that represent first sound waves. From a second microphone, second microphone signals are received that represent second sound waves. In response to the first microphone signals, analog processing is performed to estimate noise in the first sound waves, and first analog signals are generated for cancelling at least some of the estimated noise in the first sound waves. In response to the second microphone signals, digital processing is performed to estimate noise in the second sound waves, and digital information is generated for cancelling at least some of the estimated noise in the second sound waves. The digital information is converted into second analog signals that represent the digital information. The first and second analog signals are combined into third analog signals for cancelling at least some of the estimated noise in the first and second sound waves. | 04-11-2013 |
20130089269 | Scene Adaptive Filter Design for Improved Stereo Matching - A method is provided that includes generating coefficients of a scene adaptive filter (SAF) based on differences between values of neighboring pixels in a representative two dimensional (2D) image, and applying the SAF to a plurality of corresponding 2D images. | 04-11-2013 |
20130091460 | Method, System and Computer Program Product for Receiving Information From a User - A window is displayed on a display device. The window includes at least first and second portions thereof. In response to a user selecting the first portion of the window on the display device, a first set of keys are displayed on the display device. The first set of keys are operable by the user to specify a first type of information within the first portion of the window. In response to the user selecting the second portion of the window on the display device, a second set of keys are displayed on the display device. The second set of keys are operable by the user to specify a second type of information within the second portion of the window. The second type of information includes at least some information that is unsupported by operation of the first set of keys. | 04-11-2013 |
20130093024 | STRUCTURE AND METHOD FOR INTEGRATING FRONT END SiCr RESISTORS IN HiK METAL GATE TECHNOLOGIES - An integrated circuit having a replacement HiK metal gate transistor and a front end SiCr resistor. The SiCr resistor replaces the conventional polysilicon resistor in front end processing and is integrated into the contact module. The first level of metal interconnect is located above the SiCr resistor. First contacts connect to source/drain regions. Second contacts electrically connect the first level of interconnect to either the SiCr resistor or the metal replacement gate. | 04-18-2013 |
20130093248 | INDUCTOR-BASED ACTIVE BALANCING FOR BATTERIES AND OTHER POWER SUPPLIES - A system includes multiple power supplies connected in series and an active balancing circuit. The active balancing circuit includes an LC resonance circuit and multiple switches configured to selectively couple different ones of the power supplies to the LC resonance circuit. The LC resonance circuit includes an inductor, a capacitor, and an additional switch. The inductor is configured to store energy to be transferred between two or more of the power supplies. The additional switch is configured to selectively create a resonance between the inductor and the capacitor in order to reverse a direction of a current flow through the inductor. The active balancing circuit can transfer energy between individual power supplies or groups of power supplies. | 04-18-2013 |
20130093395 | Capacitor-based active balancing for batteries and other power supplies - A system includes multiple power supplies connected in series and an active balancing circuit. The active balancing circuit includes an LC resonance circuit and multiple switches configured to selectively couple different ones of the power supplies to the LC resonance circuit. The LC resonance circuit includes a capacitor, an inductor, and an additional switch. The capacitor is configured to store energy to be transferred between two or more of the power supplies. The additional switch is configured to selectively create a resonance between the capacitor and the inductor in order to reverse a discharge current direction through the capacitor. | 04-18-2013 |
20130093455 | TSV TESTING METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for testing TSVs in a single die or TSV connections in a stack of die. | 04-18-2013 |
20130093480 | DIGITAL PHASE LOCKED LOOP - A phase locked loop circuit ( | 04-18-2013 |
20130093496 | POWER-SAVING RECEIVER CIRCUITS, SYSTEMS AND PROCESSES - An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit ( | 04-18-2013 |
20130094459 | Beacon Slot Allocation in Prime - Systems and methods for efficiently allocating beacon slot among multiple nodes on multiple levels within a power line communication network are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include performing, by a communications device, assigning beacon transmission times to nodes within the communication device's network. The assigned beacon transmission times comprise a beacon slot and frame pattern. The beacon slot and frame pattern ensure that each node does not transmit a beacon in a beacon slot that is adjacent to a beacon slot assigned to a parent or child node. A beacon transmission slot is reserved for a base node in every frame. The frames may be organized into thirty-two-frame superframes, wherein each frame comprises a base node beacon slot and four switch node beacon slots. | 04-18-2013 |
20130094552 | Communication on a Pilot Wire - Systems and methods are disclosed for communicating on a pilot wire between Electric Vehicle Service Equipment (EVSE) and an Electric Vehicle (EV). In an example embodiment, a modem is coupled to the pilot wire that couples the EVSE and the EV. The modem transmits both pulse width modulation (PWM) command signals and power line communication (PLC) signals to a remote device via the pilot wire. The modem interleaves the PWM and PLC signals on the pilot wire so that latency requirements for the PWM signals are maintained. The modem supports parallel protocol stacks in which PLC signals are processed in a first path and PWM signals are processed in a second path that bypasses the first path and provides the PWM signals directly to a MAC layer. The modem may create a modified frame for the PLC signals to maintain the latency requirements. | 04-18-2013 |
20130094592 | Virtual Memory Access Bandwidth Verification (VMBV) in Video Coding - A method is provided that includes determining a target picture virtual memory access (VMA) bandwidth rate, wherein the target picture VMA bandwidth rate indicates a maximum VMA bandwidth rate for motion compensation of a picture, and verifying the target picture VMA bandwidth rate for a compressed video bit stream. | 04-18-2013 |
20130094597 | Joining Process for G3 Networks - Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method performed by a PLC device, such as a PLC meter, may include identifying at least one bootstrapping agent and a personal area network (PAN) identifier for one or more networks that are operating within a personal operating space of the PLC device. The device selects a target bootstrapping agent to use for the join process with a target network. The target bootstrapping agent may be selected from a list of bootstrapping agents associated with the target PAN identifier. If the attempt to join the target network fails, then the device further determines if other bootstrapping agents are associated with the target PAN identifier. The device selects an alternate target bootstrapping agent from the other bootstrapping agents that are associated with the target PAN identifier and reattempts the join process. | 04-18-2013 |
20130094779 | Method and Apparatus for Prediction Unit Size Dependent Motion Compensation Filtering Order - A motion compensation method and apparatus. The method includes retrieving data relating to a reference bock, performing a transpose on the retrieved data, performing vertical filtering on the transposed retrieved data, performing one or more transpose on the vertically filtered data, performing horizontal filtering on the transposed vertically filtered dad, and generating an interpolated bock and storing the interpolated block. | 04-18-2013 |
20130095630 | THRESHOLD MISMATCH AND IDDQ REDUCTION USING SPLIT CARBON CO-IMPLANTATION - An integrated circuit containing MOS transistors may be formed using a split carbon co-implantation. The split carbon co-implant includes an angled carbon implant and a zero-degree carbon implant that is substantially perpendicular to a top surface of the integrated circuit. The split carbon co-implant is done at the LDD and halo implant steps. | 04-18-2013 |
20130097466 | REMOVABLE AND REPLACEABLE TAP DOMAIN SELECTION CIRCUITRY - Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains. | 04-18-2013 |
20130097467 | SCAN FRAME BASED TEST ACCESS MECHANISMS - Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation. | 04-18-2013 |
20130097468 | LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS - Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures. | 04-18-2013 |
20130099333 | MICRO-ELECTRO-MECHANICAL SYSTEM HAVING MOVABLE ELEMENT INTEGRATED INTO LEADFRAME-BASED PACKAGE - A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices. | 04-25-2013 |
20130100019 | ENHANCED PROJECTED IMAGE INTERFACE - An interactive display projection system, includes a pointing device which determines a location on the projected display indicated by the pointing device using a combination of a location signal in the display captured by the pointing device and optical mouse circuitry to determine motion of the pointing device when the pointing device is close to the projected display. In another embodiment, the pointing device also includes an inertial sensor and associated circuitry which detects linear accelerations and rotational rates to determine motion and orientation of the pointing device, which are also used to determine the location on the projected display indicated by the pointing device. | 04-25-2013 |
20130100125 | Method, System and Computer Program Product for Enhancing a Depth Map - A first depth map is generated in response to a stereoscopic image from a camera. The first depth map includes first pixels having valid depths and second pixels having invalid depths. In response to the first depth map, a second depth map is generated for replacing at least some of the second pixels with respective third pixels having valid depths. For generating the second depth map, a particular one of the third pixels is generated for replacing a particular one of the second pixels. For generating the particular third pixel, respective weight(s) is/are assigned to a selected one or more of the first pixels in response to value similarity and spatial proximity between the selected first pixel(s) and the particular second pixel. The particular third pixel is computed in response to the selected first pixel(s) and the weight(s). | 04-25-2013 |
20130100177 | SPATIALLY MULTIPLEXED PULSE WIDTH MODULATION - A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for every pixel intensity value to form display data codeword tables so that there are at least as many display data codeword tables as the number of display data bits with substantially equal time weights. The display pixel is subsequently operated in a digital manner according to the display data codeword in the selected display data codeword table to display a desired pixel intensity value. The display data codeword tables are configured so that immediately adjacent display pixels are operated so that identical pixel intensity values are displayed with different temporal sequences. | 04-25-2013 |
20130100281 | Method, System and Computer Program Product for Detecting an Obstacle with a Camera - For detecting an obstacle with a camera, a first image is viewed by the camera at a first location during a first time. Points on a surface would project onto first pixels of the first image. A second image is viewed by the camera at a second location during a second time. The points on the surface would project onto second pixels of the second image. Coordinates of the second pixels are identified in response to coordinates of the first pixels, in response to a displacement between the first and second locations, and in response to a distance between the camera and the surface. The obstacle is detected in response to whether the first pixels substantially match the second pixels. | 04-25-2013 |
20130100420 | SPECTRAL FILTERING OF PHOSPHOR COLOR WHEELS - A projection light source has a source of laser light of a first color. A first member has first and second phosphor material segments respectively configured to emit light of second and third colors when illuminated by the laser light of the first color. A second member has first and second dichroic filter segments respectively configured to pass the light of the second and third colors emitted by the first and second phosphor material segments, while blocking light of the others of the first, second and third colors. Relative placements of the first and second members are synchronized to periodically align the first member with the laser light source and the second member with the first member, so that the first dichroic filter segment will pass the second color along a path at first time intervals when the second color is emitted by the first phosphor material and the second dichroic filter segment will pass the third color along at least a same portion of the path at second time intervals when the third color is emitted by the second phosphor material. | 04-25-2013 |
20130101003 | Relative Phase Detection in Power Line Communications Networks - Systems and methods for relative phase detection and zero crossing detection for power line communications (PLC) are described. In some embodiments, both transmit and receive PLC devices detect a zero crossing on an AC mains phase. The devices start a phase detection counter (PDC) by generating a zero crossing pulse within 5% of the actual zero crossing time. When a frame is transmitted, the transmitting device includes a PDC value in the frame control header (FCH). The PDC value corresponds to the start time of the FCH. When the frame is received at the receive PLC device, the receive PLC device measures a local PDC value between the zero crossing and the start of the FCH. The receive device compares the local PDC value to the PDC value in the FCH of the received frame and determines if the devices are on the same phase. | 04-25-2013 |
20130101036 | Sample-Based Angular Intra-Prediction in Video Coding - A method for processing a prediction unit (PU) to generate predicted samples is provided that includes computing predicted samples for samples of the PU using sample-based angular intra-prediction (SAP) when lossless coding is enabled for the PU, and computing predicted samples for the samples of the PU using block-based angular intra-prediction when lossless coding is not enabled for the PU. Computation of the predicted using SAP includes determining an intra-prediction angle for the PU, and computing a predicted sample for each sample of the samples in the PU based on linear interpolation of two reference samples adjacent to the sample, wherein the two reference samples are selected according to the intra-prediction angle. | 04-25-2013 |
20130101055 | Sub-Band Power Scaling Reporting and Sub-Band Transmit Power Estimation - Systems and methods for routing protocols for power line communications (PLC) are described. In some embodiments, a method performed by a PLC device, such as a PLC meter, may include selecting one or more transmit sub-bands on which to transmit frames, where the transmit sub-bands comprise groups of six carrier frequencies. The PLC device then generates a frame comprising a tone map that indicates which transmit sub-bands are used to carry data for the frame. The tone map using two bits per transmit sub-band to indicate a status of each transmit sub-band. The PLC device then transmits the frame on the selected transmit sub-bands using OFDM. A resolution bit and a mode bit may be used to provide additional information about the transmit sub-bands, such as an amount of power adjustment that has been applied to carrier frequencies and whether dummy bits are transmitted on unused carrier frequencies. | 04-25-2013 |
20130101206 | Method, System and Computer Program Product for Segmenting an Image - A first depth map is generated in response to a first stereoscopic image from a camera. The first depth map includes first pixels having valid depths and second pixels having invalid depths. A second depth map is generated in response to a second stereoscopic image from the camera. The second depth map includes third pixels having valid depths and fourth pixels having invalid depths. A first segmentation mask is generated in response to the first pixels and the third pixels. A second segmentation mask is generated in response to the second pixels and the fourth pixels. In response to the first and second segmentation masks, a determination is made of whether the second stereoscopic image includes a change in comparison to the first stereoscopic image. | 04-25-2013 |
20130103995 | BLOCKING THE EFFECTS OF SCAN CHAIN TESTING UPON A CHANGE IN SCAN CHAIN TOPOLOGY - A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing. | 04-25-2013 |
20130103996 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 04-25-2013 |
20130104117 | Data Concentrator Initiated Multicast Firmware Upgrade - Systems and methods for implementing data concentrated initiated multicast firmware upgrade in power line communications (PLC) are described. In an illustrative embodiment, a method performed by a PLC device may include forming a group of PLC devices to receive a transmission of a data set, the group being organized according to a hierarchical structure, transmitting the data set to the group of PLC devices, determining whether a PLC device in the lowest level of the hierarchical structure is missing one or more portions of the data set, and retransmitting at least the missing portions of the data set until the lowest level of PLC devices each have the full data set. | 04-25-2013 |
20130113566 | VARIABLE GAIN AMPLIFIER - An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage). | 05-09-2013 |
20130113881 | Reducing Disparity and Depth Ambiguity in Three-Dimensional (3D) Images - A method for three dimensional (3D) image processing is provided that includes receiving an image, wherein each location in the image includes a value indicative of a depth of a pixel in a scene and wherein each value has an associated confidence measure, determining whether each similarity region of a plurality of non-overlapping similarity regions in the image is valid or invalid based on a number of values in the similarity region having sufficiently high confidence measures, wherein a similarity region includes contiguous locations in the image having similar values, and indicating that the values in a similarity region are invalid when the similarity region is determined to be invalid. | 05-09-2013 |
20130114528 | METHOD AND APPARATUS WITH ENHANCED CONTROL MESSAGES AND SEARCH SPACE - A method of mapping control information in a wireless communication system is disclosed (FIG. | 05-09-2013 |
20130114692 | Simplified Coefficient Scans for Non-Square Transforms (NSQT) in Video Coding - A method for encoding a video sequence is provided that includes applying a non-square transform to a non-square block of residual values to generate a non-square block of transform coefficients, quantizing the transform coefficients to generate a non-square block of quantized transform coefficients, dividing the non-square block of quantized transform coefficients into a plurality of square blocks of quantized transform coefficients, and entropy encoding the plurality of square coefficient blocks. | 05-09-2013 |
20130114697 | Method, System and Apparatus for Intra-Refresh in Video Signal Processing - A video codec for encoding a sequence of video frames divides a video frame area into number of row segments. The Video encoder selects a different set of row segments in each video frame in a set of video frames and encodes the selected set of row segments by intra-prediction. As a result, the selected part of the frame is intra-refreshed. The video codec limits the maximum value of the vertical global motion vector GMVy to zero and video codec adjust the number of row segments in the select set of row segments based on the height of the search range configured for the motion estimation. As a result, the video codec may not refer to a un-refreshed portion in the previous frame for encoding an already refreshed area of the current frame. | 05-09-2013 |
20130114715 | Delayed Duplicate I-Picture for Video Coding - A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture. | 05-09-2013 |
20130114737 | LOOP FILTERING MANAGING STORAGE OF FILTERED AND UNFILTERED PIXELS - A video encoder comprises a loop filter to filter luminance and chrominance pixel values, first and second loop filter working buffers accessible to the loop filter, and ping and pong loop filter data buffers accessible to the loop filter and to a direct memory access (DMA) engine. The loop filter filters pixels about a plurality of vertical edges and a plurality of horizontal edges for each macroblock in a video frame. The loop filter distributes partially filtered luma and chrominance pixel values across the first and second loop filter working buffers as well as the ping and pong loop filter data buffers, and does not save partially filtered luma and chrominance pixel values to external memory via the DMA engine. | 05-09-2013 |
20130114909 | Method and Apparatus for Image and Video Coding Using Hierarchical Sample Adaptive Band Offset - A method and apparatus for image coding using hierarchical sample adaptive band offset. The method includes decoding a signal of a portion of an image, determining a band offset type and offset of a portion of the image, utilizing the band offset type and offset to determine a sub-band, and reconstructing a pixel value according to the determined offset value. | 05-09-2013 |
20130116921 | VEHICLE NAVIGATION SYSTEM WITH DEAD RECKONING - A vehicle navigation system includes a GNSS position engine (GPE) that uses GNSS satellite measurements to compute a first position and velocity of a vehicle and a first quality metric associated with the position and velocity. The system also includes a dead reckoning engine (DRE) that operates parallel with the GPE that computes a second position and velocity and a second quality metric associated with the dead reckoning. The GPE is configured to use the second position and velocity to detect a set of outliers in an incoming GNSS measurement; use the second position and velocity as an initial estimate of its position and velocity for a particular time instant, which is then refined by GNSS measurements received at that particular time instant; and to replace the first position and velocity with the second position and velocity. | 05-09-2013 |
20130117343 | Unified Forward and Inverse Transform Architecture - Multiple transform sizes improve video coding efficiency, but also increase the implementation complexity. Furthermore, both forward and inverse transforms need to be supported in various consumer devices. Embodiments provide a unified forward and inverse transform architecture that supports computation of both forward and inverse transforms for multiple transforms sizes using shared hardware circuits. The unified architecture exploits the symmetry properties of forward and inverse transform matrices to achieve hardware sharing across different the transform sizes and also between forward and inverse transform computations. | 05-09-2013 |
20130120543 | Method, System and Computer Program Product for Adjusting a Convergence Plane of a Stereoscopic Image - First and second views of a stereoscopic image are received. In response to determining that the stereoscopic image has a predominance of foreground features, a convergence plane of the stereoscopic image is adjusted to improve a depth resolution of at least one foreground feature within the stereoscopic image for display to a human by a display device. In response to determining that the stereoscopic image has a predominance of background features, the convergence plane is adjusted to position at least most of the stereoscopic image as background features for display to the human by the display device. | 05-16-2013 |
20130121357 | LASER DIODE WITH WAVE-SHAPE CONTROL - An optical disk drive system associated with a laser diode is described. The optical disk drive system comprises a current generator for receiving input signals; a current switch coupled to receive timing signals; a current driver coupled to receive output signals from the current switch and the current generator, the current driver further comprising a driver with wave shape control selected from the group consisting of a laser diode read driver and a laser diode write driver, wherein the driver with shape control is operative for transmitting at least one output signal that is a scaled version of at least one of the output signals received from the current generator, wherein the current driver is operative for transmitting at least one output signal driving the laser diode. | 05-16-2013 |
20130121425 | Coexistence Method by Requesting Access to the Channel - Systems and methods for implementing coexistence by requesting access to a channel in power line communications (PLC) are described. In an illustrative embodiment, a method performed by a PLC device, such as a PLC meter, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, determining whether a threshold back-off duration has been reached, and transmitting a channel access request in response to a determination that the threshold back-off duration has been reached. | 05-16-2013 |
20130121427 | SCALED POWER LINE BASED NETWORK - A power line communication network includes a first power line communication sub-network, a second power line communication sub-network, and an isolation filter disposed between first and second power line communication sub-networks. The isolation filter is configured to pass electrical power signals between the first and second power line communication sub-networks, and to block passage of data communication signals from the first power line communication sub-network to the second power line communication sub-network. | 05-16-2013 |
20130121561 | Method, System and Computer Program Product for Detecting an Object in Response to Depth Information - First information is about respective depths of pixel coordinates within an image. Second information is about respective depths of the pixel coordinates within a ground plane. In response to comparing the first information against the second information, respective markings are generated to identify whether any one or more of the pixel coordinates within the image has significant protrusion from the ground plane. In response to a particular depth of a representative pixel coordinate within the image, a window of pixel coordinates is identified that is formed by different pixel coordinates and the representative pixel coordinate. In response to the respective markings, respective probabilities are computed for the pixel coordinates, so that the respective probability for the representative pixel coordinate is computed in response to the respective markings of all pixel coordinates within the window. In response to the respective probabilities, at least one object is detected within the image. | 05-16-2013 |
20130121562 | Method, System and Computer Program Product for Identifying Locations of Detected Objects - First and second objects are detected within an image. The first object includes first pixel columns, and the second object includes second pixel columns. A rightmost one of the first pixel columns is adjacent to a leftmost one of the second pixel columns. A first equation is fitted to respective depths of the first pixel columns, and a first depth is computed of the rightmost one of the first pixel columns in response to the first equation. A second equation is fitted to respective depths of the second pixel columns, and a second depth is computed of the leftmost one of the second pixel columns in response to the second equation. The first and second objects are merged in response to the first and second depths being sufficiently similar to one another, and in response to the first and second equations being sufficiently similar to one another. | 05-16-2013 |
20130121607 | Elegant Solutions for Fingerprint Image Enhancement - This invention includes image processing techniques directed to achieve feature enhancement and background-foreground enhancement in fingerprint images. The image is divided into plural segments depending on the ridge-valley directions. Each segment is separately filtered with a directional filter generally perpendicular to the corresponding ridge-valley direction. Background-foreground detection employs edge detection to identify edge pixels. These edge pixels are averaged to determine a threshold. The threshold is applied to the original image to determine background and foreground pixels. The background and foreground pixels are filtered via a watershed fill filter with separate connectivity for background and foreground pixels. | 05-16-2013 |
20130122654 | Package Substrate Having Die Pad with Outer Raised Portion and Interior Recessed Portion - A method of forming an electronic assembly includes dispensing a die attach material on a substrate into a recessed portion that includes an inner recessed portion of including a die pad. The die attach material is not dispensed on an outer raised flat portion of the die pad. A semiconductor die is attached directly on the outer raised flat portion and affixed to the die pad with said die attach material in said interior recessed portion but not on said outer raised flat portion. | 05-16-2013 |
20130124129 | Magnetormeter Calibration for Navigation Assistance - Visual codes are scanned to assist navigation. The visual code may be a Quick Response (QR) code that contains information useful to calibrating a variety of navigation-based sensors such as gyroscopes, e-compasses, and barometric pressure sensors. Embodiments describe methods for magnetometer calibration and computing sensor orientation relative to users' local frame of reference. The embodiments use an initial yaw estimate, accelerometer, and gyroscope measurements along with other readily available information (the earth's magnetic field intensity, inclination angle, and declination angle). | 05-16-2013 |
20130124895 | MICROPROCESSOR BASED POWER MANAGEMENT SYSTEM ARCHITECTURE - An electronic system is disposed on a single integrated circuit including a plurality of power domains and a power control manager. Each power domain may be independently powered. The power control manager includes a set of control registers storing individual control bits, a power switch for each power domain and a programmable microprocessor. The programmable microprocessor controls the digital state of individual bits within the control registers thereby controlling the ON and OFF state of the corresponding power domain. | 05-16-2013 |
20130124935 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 05-16-2013 |
20130124936 | TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS - An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation. | 05-16-2013 |
20130128238 | Display Systems and Methods for Mobile Devices - Display systems and methods for mobile devices and mobile devices are disclosed. In one embodiment, a display system for a mobile device is provided. The mobile device is handheld and includes a primary display screen. The display system includes an auxiliary screen and a connecting device coupled to the auxiliary screen and attachable to the mobile device. An image from the mobile device is producible on the auxiliary screen. The display system is removable from the mobile device. | 05-23-2013 |
20130128952 | Method and Apparatus for SSIM-Based Bit Allocation - A method and an encoder for SSIM-based bits allocation. The encoder includes a memory and a processor utilized for allocating bits based on SSIM, wherein the processor estimates the model parameter of SSIM-based distortion model for the current picture and determines allocates bits based on the SSIM estimation. | 05-23-2013 |
20130129035 | PROGRAMMABLE RING OSCILLATOR USED AS A TEMPERATURE SENSOR - A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold. | 05-23-2013 |
20130129123 | Plurality of Mobile Communication Devices for Performing Locally Collaborative Operations - A system to reproduce multi channel sound. A first wireless transceiver wirelessly receives audio data and acoustically reproduces a front center channel. A second wireless transceiver wirelessly receives the audio data and acoustically reproduces a front right channel. A third wireless transceiver wirelessly receives the audio data and acoustically reproduces a front left channel. A fourth wireless transceiver wirelessly receives the audio data and acoustically reproduces a rear right channel. And a fifth wireless transceiver wirelessly receives the audio data and acoustically reproduces a rear left channel. | 05-23-2013 |
20130130411 | Interleaf for Leadframe Identification - A method of making an IC device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets. The interleaf members include indicia that identifies the leadframes sheets. The stack of leadframe sheets is loaded onto an assembly machine. A first interleaf member is removed from the first leadframe sheet. The first leadframe sheet is transferred onto a mounting surface of the assembly machine. Semiconductor die are attached to leadframes on the first leadframe sheet. The method can include reading the indicia from the first interleaf member to determine a part number and lead finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified. | 05-23-2013 |
20130130450 | LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 05-23-2013 |
20130131983 | Low-Complexity Tightly-Coupled Integration Filter for Step Detection in a Sensor-Assisted GNSS Receiver - Embodiments of the invention provide a step detection. An accelerometer measurement in the form of a multi-dimensional acceleration vector is obtained. The magnitude of the accelerometer measurement is filtered using a low pass filter. A threshold for a down-crossing is provided as is a threshold for an up-crossing. A step detection is triggered if the magnitude of the accelerometer measurement is greater than or equal to the threshold for an up-crossing. | 05-23-2013 |
20130139017 | 1149.1 TAP LINKING MODULES - IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations. | 05-30-2013 |
20130141110 | METHODS AND APPARATUS FOR CONTINUOUS GROUND FAULT SELF-TEST - Methods and apparatus for continuous ground fault self-test are disclosed. An example ground fault detection device includes a sense coil to detect current in a line conductor and a neutral conductor, the sense coil comprising a winding influenced by a current difference between the line conductor and the neutral conductor. The example ground fault detection device also includes a current bypass to facilitate a continuous current imbalance detected by the sense coil, and a ground fault detector circuit to detect at least one of the continuous current imbalance in the sense coil or a ground fault current imbalance. | 06-06-2013 |
20130145226 | BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL MEMORIES - An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path. | 06-06-2013 |
20130146978 | TRANSISTOR ASSISTED ESD DIODE - An integrated circuit includes a diode/bipolar ESD protection device. The diode/bipolar ESD device includes at least one gate separated ESD diode and at least one gate spaced ESD bipolar transistor coupled in parallel between a fixed voltage and an input/output pin. | 06-13-2013 |
20130148416 | SRAM CELL HAVING AN N-WELL BIAS - An integrated circuit containing SRAM cells. Each SRAM cell has a PMOS driver transistor, a PMOS passgate transistor, and at least two separate n-wells. The integrated circuit also has an n-well bias control circuit that is configured to independently bias the n-wells of an addressed SRAM cell. Moreover, a process of operating an integrated circuit that contains SRAM cells. The process includes writing a low data bit value, writing a high data bit value, and reading a data bit value of an addressed SRAM cell. | 06-13-2013 |
20130148431 | ON-CHIP MEMORY TESTING - An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array. | 06-13-2013 |
20130148651 | INTEGRATED CIRCUITS, SYSTEMS, APPARATUS, PACKETS AND PROCESSES UTILIZING PATH DIVERSITY FOR MEDIA OVER PACKET APPLICATIONS - In one form of the invention, a process of sending real-time information from a sender computer ( | 06-13-2013 |
20130148746 | Scheduling for Charger and Electric Vehicle Communication in Power Line Communication System - Systems and methods for establishing scheduling for charger and electric vehicle communication in a PLC system are described. In an illustrative embodiment, a method performed by a PLC device. In a further embodiment, the PLC device may be configured to operate according to a narrow-band PLC communication protocol. In a further embodiment, the narrow-band PLC communications between PLC devices in the charger and the electric vehicle are conducted over a pilot wire coupling the charger to the electric vehicle. In still a further embodiment, the pilot wire may be one of a standard set of existing wires in a standard cable used for connecting the charger to the electric vehicle. | 06-13-2013 |
20130149799 | WAFER TEMPERATURE CORRECTION SYSTEM FOR ION IMPLANTATION DEVICE - To provide an ion implantation device capable of correcting the temperature of the wafer. The ion implantation device of the present invention has: an irradiation means that radiates ions; a retention means that includes a disk | 06-13-2013 |
20130149829 | DUAL NSD IMPLANTS FOR REDUCED RSD IN AN NMOS TRANSISTOR - In an embodiment of the invention, a method of forming an NMOS (n-type metal-oxide semiconductor) transistor is disclosed. A dual mask pattern is used to ion-implant source/drain regions of the NMOS transistor. The first mask allows first doses of As (arsenic), P (phosphorous) and N (Nitrogen) to be ion-implanted. After these doses are ion-implanted, a high temperature (900-1050 C) spike anneal is performed to activate the formed source/drains. A second mask allows a second dose of phosphorus to be implanted in the source/drain regions. The second dose of the phosphorus is typically higher than the first dose of phosphorus. The second dose of phosphorus lowers the Rsd (resistance of the source and drain regions) and dopes n-type poly-silicon blocks. | 06-13-2013 |
20130149849 | COMBINING ZTCR RESISTOR WITH LASER ANNEAL FOR HIGH PERFORMANCE PMOS TRANSISTOR - An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal. | 06-13-2013 |
20130151916 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 06-13-2013 |
20130151917 | IP CORE DESIGN SUPPORTING USER-ADDED SCAN REGISTER OPTION - An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port | 06-13-2013 |
20130153896 | SCAN TESTABLE THROUGH SILICON VIAs - The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs. | 06-20-2013 |
20130155320 | PERCEPTUAL VIDEO QUALITY IMPROVEMENT FOR VIDEOS CONTAINING BLACK BARS - A method of improving the perceptual video quality of video sequences containing black bars. Horizontal or vertical black bars caused by a missmatch between the aspect ratio of the encoded video and the display device. The presence of black bars is detected, and the encoding process is adjusted to eliminate visual depredation of the reproduced video. | 06-20-2013 |
20130155956 | ENABLING COORDINATED MULTI-POINT RECEPTION - This invention measures the propagation delay τ | 06-20-2013 |
20130155988 | Allocation and Logical to Physical Mapping of Scheduling Request Indicator Channel in Wireless Networks - A method for allocating resources for a scheduling request indicator (SRI) is disclosed. An SRI cycle period for use by user equipment (UE) within a cell is transmitted from a NodeB in a cell to UE within the cell. The NodeB transmits a specific SRI subframe offset and an index value to the particular UE within the cell. The specific SRI subframe offset and the index value enable the UE to determine a unique combination of cyclic shift, RS orthogonal cover, data orthogonal cover, and resource block number for the UE to use as a unique physical resource for an SRI in the physical uplink control channel (PUCCH). | 06-20-2013 |
20130156016 | WIRELESS NETWORK SYSTEMS - Several wireless network systems are disclosed. In an embodiment, a wireless network system includes at least two access points and a distributed set of devices communicatively associated with the at least two access points. Each device from among the distributed set of devices comprises a pair of wireless stations and each wireless station from among the pair of wireless stations is configured to transmit data associated with an alert situation to a distinct access point from among the at least two access points. A communication between one or more access points from among the at least two access points and one or more wireless stations from among the pairs of wireless stations corresponding to the distributed set of devices is synchronized based on a timing synchronization information shared by at least two basic service sets (BSSs) corresponding to the at least two access points. | 06-20-2013 |
20130156097 | Adaptive Loop Filtering (ALF) for Video Coding - A method for adaptive loop filtering of a reconstructed picture in a video encoder is provided that includes determining whether or not sample adaptive offset (SAO) filtering is applied to the reconstructed picture, and using adaptive loop filtering with no offset for the reconstructed picture when the SAO filtering is determined to be applied to the reconstructed picture. | 06-20-2013 |
20130156214 | Method and System for Active Noise Cancellation According to a Type of Noise - Microphone signals are received from a microphone. The microphone signals represent first sound waves. A determination is made about a type of noise that likely exists in the first sound waves. In response to the type of noise, cancellation signals are generated by filtering the microphone signals with at least one of: a first filter in response to the type of noise indicating that a first type of noise likely exists in the first sound waves; and a second filter in response to the type of noise indicating that a second type of noise likely exists in the first sound waves. In response to the cancellation signals, second sound waves are output from a speaker for cancelling at least some noise in the first sound waves. | 06-20-2013 |
20130157424 | Method for improved mobility using hybrid orientaion technology (HOT) in conjunction with - A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. | 06-20-2013 |
20130157429 | HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN - An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations. | 06-20-2013 |
20130159801 | ADAPTING SCAN ARCHITECTURES FOR LOW POWER OPERATION - Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer. | 06-20-2013 |
20130161639 | DRAIN INDUCED BARRIER LOWERING WITH ANTI-PUNCH-THROUGH IMPLANT - An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions. | 06-27-2013 |
20130164933 | HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. | 06-27-2013 |
20130170437 | NETWORK MIMO REPORTING, CONTROL SIGNALING AND TRANSMISSION - A coordinated multipoint transmitter is for use with a network MIMO super-cell and includes a coordination unit configured to provide joint link processing to coordinate a multipoint transmission corresponding to a set of transmission points. Additionally, the coordinated multipoint transmitter also includes a transmission unit configured to transmit the multipoint transmission using the set of transmission points. Additionally, a coordinated transmission receiver is for use with a network MIMO super-cell and includes a reception unit configured to receive a multipoint transmission corresponding to a set of transmission points. The coordinated transmission receiver also includes a processing unit configured to process the multipoint transmission from the set of transmission points. | 07-04-2013 |
20130173868 | Generation of Activation List for Memory Translation and Memory Access Protection in Industrial Ethernet Standard - The invention relates to an EtherCAT fieldbus system, a master and a slave for the system and a method. The slave is configured to be coupled to the EtherCAT fieldbus. A first configurable memory of the slave stores a first activation list indicating for consecutive bytes of data of an EtherCAT datagram a corresponding fieldbus memory management information or synchronization management information. | 07-04-2013 |
20130175072 | REDUCING THERMAL GRADIENTS TO IMPROVE THERMOPILE PERFORMANCE - With infrared (IR) sensors, repeatability and accuracy can become an issue when there are thermal gradients between the sensor and an underlying printed circuit board (PCB). Conventionally, a large thermal mass is included in the sensor packaging to reduce the effect from such thermal gradients, but this increase costs and size of the sensor. Here, however, a PCB is provided that includes an isothermal cage included therein that generally ensures that the temperature of the underlying PCB and sensor are about the same by including structural features (namely, the isothermal cage) that generally ensure that the thermal time constant for a path from a heat source to the thermopile (which is within the sensor) is approximately the same as thermal time constants for paths through the PCB. | 07-11-2013 |
20130176155 | APPARATUS AND SYSTEM TO SUPPRESS ANALOG FRONT END NOISE INTRODUCED BY CHARGE-PUMP THROUGH EMPLOYMENT OF CHARGE-PUMP SKIPPING - An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output. | 07-11-2013 |
20130176639 | PROXIMITY SENSING SYSTEM - A data storage system for detecting a location of a head relative to a magnetic media is described. This system comprises arms, a preamplifier circuit coupled to the arms for controlling the arms, a proximity sensing system positioned within the preamplifier circuit, the proximity sensing system comprising: an input stage for transmitting an input sense signal; a programmable gain stage coupled to receive the input sense signal and operative for transmitting a gain signal in response to receiving the input sense signal; a multiplexer coupled to receive the gain signal and at least one control signal, the multiplexer operative for transmitting a multiplexed signal; a detector coupled to receive the multiplexed signal and a second control signal, the detector operative for transmitting an output signal; wherein an amplitude associated with the output signal enables detecting the location of the head. | 07-11-2013 |
20130176772 | Electrical Screening of Static Random Access Memories at Varying Locations in a Large-Scale Integrated Circuit - A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing, are disclosed. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed. | 07-11-2013 |
20130176809 | SELF CLOCKING FOR DATA EXTRACTION - A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. | 07-11-2013 |
20130177026 | Unified Programmable Interface for Real-Time Ethernet - This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance | 07-11-2013 |
20130177069 | Context Adaptive Binary Arithmetic Coding (CABAC) with Scalable Throughput and Coding Efficiency - A method for encoding a video sequence is provided that includes entropy encoding syntax elements representative of transform coefficients generated as the video sequence is processed, wherein entropy encoding syntax elements representative of a transform coefficient includes binarizing the syntax elements representative of the transform coefficient to generate a plurality of binary symbols (bins), coding a portion of the plurality of bins in context coding mode, and coding a remaining portion of the plurality of bins in bypass coding mode. The method further includes reducing the number of bins that are coded in context coding mode for each transform coefficient in a plurality of subsequent transform coefficients that are entropy encoded after a specified number of transform coefficients have been entropy encoded. | 07-11-2013 |
20130177253 | Multi-Pass Video Noise Filtering - A method of noise filtering of a digital video sequence is provided that includes computing a motion image for a frame, wherein the motion image includes a motion value for each pixel in the frame, and wherein the motion values are computed as differences between pixel values in a luminance component of the frame and corresponding pixel values in a luminance component of a reference frame, applying a first spatial noise filter to the motion image to obtain a final motion image, computing a blending factor image for the frame, wherein the blending factor image includes a blending factor for each pixel in the frame, and wherein the blending factors are computed based on corresponding motion values in the final motion image, generating a filtered frame, wherein the blending factors are applied to corresponding pixel values in the reference frame and the frame, and outputting the filtered frame. | 07-11-2013 |
20130179619 | TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS - A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design. | 07-11-2013 |
20130179701 | SEPARATE DEBUG POWER MANAGEMENT - The power consumption of embedded debug functions in ultra low power SoC sytems is minimized by seggregating the debug logic into separate power domains, and allocating separate power pins to the debug power sources. Debug power may be supplied from an external power source, from the system power source or from a functional communication interface such as USB, JTAG or cJTAG. | 07-11-2013 |
20130179715 | SYSTEMS AND METHODS FOR REDUCING ENERGY CONSUMPTION IN SENSOR NETWORKS - A system includes a volatile memory and state information management logic. The volatile memory includes a plurality of volatile storage locations. The state information management logic includes memory write tracking circuitry coupled to the volatile memory. The memory write tracking circuitry is configured to identify locations of the memory written subsequent to restoration of state information to the volatile memory on exit of a low-power mode of operation, and to store indicia of the identified locations. | 07-11-2013 |
20130179743 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS - A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols. | 07-11-2013 |
20130179744 | DIRECT SCAN ACCESS JTAG - The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller. | 07-11-2013 |
20130181535 | WIRELESS POWER TRANSFER - A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can include a shield residing on a given side of a substrate spaced apart from the transmitting coil. The shield can be configured to filter an electric field induced by the transmitting coil. | 07-18-2013 |
20130181539 | ADAPTIVE WIRELESS POWER TRANSFER SYSTEM AND METHOD - A system for wireless power transfer is provided. The system includes a monitoring function to monitor control parameters and an input source that supplies power to a wireless power transmitter, wherein the wireless power transmitter operates with a wireless power receiver to supply a charging current to a load. A controller can be configured to receive the control parameters from the monitoring function and to control an adjustable operating point for the wireless power transmitter which controls the charging current delivered to the load via the wireless power receiver, wherein the controller commands a maximum power operating point for the wireless power transmitter when the input source is detected at or above a predetermined threshold and commands a reduced power operating point for the wireless power transmitter when the input source to the wireless power transmitter is detected below the predetermined threshold. | 07-18-2013 |
20130181635 | LED Driver with Primary Side Sensing - The disclosed switching regulator, including a controller for a switching regulator, is adaptable to supplying, or controlling the supply of, regulated current to a load that is isolated from a source of input power by a flyback transformer, and includes: (a) detecting, after transistor SW | 07-18-2013 |
20130182304 | SPECKLE REDUCTION IN LASER SCANNING DISPLAY SYSTEMS - Speckle effect in scanning display systems that employs polarized phase-coherent light is reduced by depolarizing the phase-coherent light using a depolarizer and scanning the depolarized light for producing desired images. | 07-18-2013 |
20130182492 | 10T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY - An integrated circuit including an array of SRAM cells containing a write port with a write word line and two read buffers with read word lines. The write port includes passgate transistors connected to each data node of the SRAM cell. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are biased during a read operation. A process of operating the integrated circuit in which source nodes of read buffer driver transistors are floated during a read operation. A process of operating the integrated circuit in which the write port and the read ports share data lines and the source nodes of read buffer driver transistors are floated during a write operation. | 07-18-2013 |
20130182569 | Link Adaptation for LTE Uplink - A detailed design of an LTE Link Adaptation function for LTE uplink is disclosed. A new approach for adapting SINR backoff in OLLA is used when serving non-time-sensitive radio bearers without target BLER constraint. A sub-optimal scheduler is also disclosed wherein the SINR measurements at the ILLA input are updated on each TTI for the UEs scheduled in that sub-frame for future UL transmission with a fresher interference measurement from the sub-frame preceding by 8 ms the actual transmission sub-frame. This allows for exploitation of a correlation peak of the interference resulting from HARQ retransmissions. A schedule incorporating these features improves upon, with a minor complexity increase, the spectral efficiency performance of a low-complexity baseline scheduler only based on SINR updates at SRS rate. | 07-18-2013 |
20130182664 | Resource Configuration for EPDCCH - A system and method for providing both localized and distributed transmission modes for EPDCCH is disclosed, where one EPDCCH comprises of one or multiple CCEs. Localized versus distributed transmission may be defined in terms of the EPDCCH to CCE resource mapping. In a localized transmission CCEs are restricted to be contained within one PRB. In a distributed transmission a CCE spans over multiple PRBs. A UE can be configured to either receive the EPDCCH only in localized or only in distributed transmissions. A UE can also be configured to expect EPDCCH transmissions in both localized and distributed transmissions. In each PRB configured by the higher layer as an EPDCCH resource, 24 REs that may be used for any DMRS transmission are always reserved and not used for EPDCCH transmission. | 07-18-2013 |
20130182719 | Adaptive Sub-Band Algorithm for Point-To-Point Communication in PLC Networks - Embodiments of methods and systems for adaptive sub-band point-to-point communication are presented. In one embodiment a method includes performing functions using a power line communication (PLC) transmitter device. The method may include generating a first data packet having a first adaptive sub-band information set, the first sub-band information set comprising information to be used by a PLC receiver for determining a sub-band hopping pattern. The method may also include transmitting the first data packet on a first PLC sub-band. Additionally, the method may include hopping to a second PLC sub-band, and generating a second data packet having a second adaptive sub-band information set, the second sub-band information set comprising information to be used by the PLC receiver for determine the sub-band hopping pattern. The method may further include transmitting the second data packet on the second PLC sub-band. | 07-18-2013 |
20130182759 | Method and Apparatus for Sample Adaptive Offset Parameter Estimation in Video Coding - A method for sample adaptive offset (SAO) filtering in a video encoder is provided that includes estimating SAO parameters for color components of a largest coding unit (LCU) of a picture, wherein estimating SAO parameters includes using at least some non-deblock-filtered reconstructed pixels of the LCU to estimate the SAO parameters, performing SAO filtering on the reconstructed LCU according to the estimated SAO parameters, and entropy encoding SAO information for the LCU in a compressed video bit stream, wherein the SAO information signals the estimated SAO parameters for the LCU. | 07-18-2013 |
20130185239 | Accelerated Decision Tree Execution - A method for accelerated decision tree execution in a processor of a digital system is provided that includes receiving at least some attribute values of a plurality of attribute values of a query for the decision tree in a pre-processing component, evaluating the received attribute values in the pre-processing component according to first early termination conditions corresponding to a first decision to determine whether or not the received attribute values fulfill first early termination conditions, and querying the decision tree with the plurality of attribute values when the received attribute values do not fulfill the first early termination conditions. | 07-18-2013 |
20130185617 | WIRELESS BACKHAUL COMMUNICATION - A method for wireless backhaul communication comprising receiving, by a wireless backhaul transmitter, a data stream in a bit format and generating, by the wireless backhaul transmitter using a single-carrier block transmission scheme, a radio frame to include a plurality of physical data channel (PDCH) blocks, a pilot signal (PS) block and a physical control channel (PCCH) block with each block type pre-appended with a cyclic prefix (CP). A length of the PS block in symbols, a length of the PCCH block in symbols and a length of the PDCH block in symbols is determined by a frequency band, a bandwidth, and a channel condition. The wireless backhaul transmitter then transmits the radio frame. | 07-18-2013 |
20130185675 | DATA CAPTURE DESIGN TOOL FOR DESIGNING AND CONFIGURING SYSTEMS WITH ANALOG FRONT ENDS - A method of configuring a system includes a selectable analog output device and an analog front end (AFE). The method includes selecting, via a graphical user interface (GUI), an analog output device that provides an analog output signal, the selected device having predetermined characteristics. The method further includes selecting an operating condition for the system and a performance criterion for the system. The method also includes providing a configuration value for programming the AFE based on the selected operating condition and performance criterion. | 07-18-2013 |
20130185703 | SYSTEMS AND METHODS FOR SOFTWARE INSTRUCTION TRANSLATION FROM A HIGH-LEVEL LANGUAGE TO A SPECIALIZED INSTRUCTION SET - A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language. | 07-18-2013 |
20130187227 | FLATBAND SHIFT FOR IMPROVED TRANSISTOR PERFORMANCE - An integrated circuit includes MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. An integrated circuit includes MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and DEMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the DEMOS transistor gate overlying the DEMOS transistor channel. A method of forming an integrated circuit with MOS and LDMOS transistors with at least one of indium, carbon, nitrogen, and a halogen dopant raising the threshold voltage of a portion of the LDMOS transistor gate overlying the DEMOS transistor channel. | 07-25-2013 |
20130187252 | BONDPAD INTEGRATED THEROMELECTRIC COOLER - An integrated circuit has thermoelectric cooling devices integrated into bondpads. A method for operating the integrated circuit includes turning a thermal switch to a thermoelectric cooler operate position when the integrated circuit is powered up, turning the thermal switch to a thermoelectric cooler operate position to allow the thermoelectric cooler to operate when the integrated circuit powers down, and turning the thermal switch to a thermoelectric cooler off position when a predetermined integrated circuit chip temperature is reached. | 07-25-2013 |
20130187456 | Sourcing and Securing Dual Supply Rails of Tamper Protected Battery Backed Domain - This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification. | 07-25-2013 |
20130188667 | APPARATUS AND METHOD TO TEST EMBEDDED THERMOELECTRIC DEVICES - An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device. An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device composed of thermoelectric elements and at least one switch to disconnect at least one thermoelectric element from the thermoelectric device. Methods for testing embedded thermoelectric devices. | 07-25-2013 |
20130188704 | Scalable Prediction Type Coding - A method for encoding a video sequence is provided that includes signaling in the compressed bit stream that a subset of a plurality of partitioning modes is used for inter-prediction of a portion of the video sequence, using only the subset of partitioning modes for prediction of the portion of the video sequence, and entropy encoding partitioning mode syntax elements corresponding to the portion of the video sequence, wherein at least one partitioning mode syntax element is binarized according to a pre-determined binarization corresponding to the subset of partitioning modes, wherein the pre-determined binarization differs from a pre-determined binarization for the least one partitioning mode syntax element that would be used if the plurality of partitioning modes is used for inter-prediction. | 07-25-2013 |
20130188762 | Clock Data Recovery With Out-Of-Lock Detection - The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data. | 07-25-2013 |
20130189814 | Method for Fabricating Array-Molded Package-on-Package - a An improved semiconductor device package is manufactured by attaching semiconductor chips ( | 07-25-2013 |
20130191069 | Adaptive Step Detection - A pedometer with a three-axis accelerometer provides reliable step counts while worn on the wrist. Three-axis accelerometer data is combined into a single combined data stream. Each positive slope region around an inflection point in the combined data stream that has positive slope, a magnitude that exceeds an amplitude threshold value and that spans a time period that exceeds a time threshold value is identified. Each negative slope region around an inflection point in the combined data stream that has negative slope, a magnitude that exceeds an amplitude threshold value and that spans a time period that exceeds a time threshold value is identified. A step count is incremented for each occurrence of an identified positive slope region that is separated by an identified negative slope region as a step. | 07-25-2013 |
20130191532 | NETWORK APPLICATION PROXY SYSTEMS AND METHODS - Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The NAP-extended API function call provides parameter values associated with a host off-loadable packet exchange sequence. Using the parameter values, a NAP module intercepts and responds to one or more incoming network packets associated with the host off-loadable packet exchange sequence while the host processor is in a sleep mode state or is transitioning between sleep mode states. | 07-25-2013 |
20130192655 | THERMOELECTRIC DEVICE EMBEDDED IN A PRINTED CIRCUIT BOARD - A circuit board with an embedded thermoelectric device with hard thermal bonds. A method of embedding a thermoelectric device in a circuit board and forming hard thermal bonds. | 08-01-2013 |
20130193502 | MEDIUM VOLTAGE MOSFET DEVICE - A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches. | 08-01-2013 |
20130193852 | LED MATRIX MANAGER - Circuits for controlling a plurality of LEDs connected in series are disclosed herein. The circuit includes a plurality of switches, wherein each switch is connectable between the anode and cathode of one of the plurality of LEDs. Each of the switches has a first state wherein current does not pass through the switch and a second state wherein current passes through the switch. The circuit also includes an input for receiving data to program the switches and a data line for transferring data between a circuit controlling second LEDs that are connected in parallel with the first LEDs and the circuit. In addition, the circuit includes a data output for transferring data to other circuits controlling third LEDs that are connected in series with the first LEDs. | 08-01-2013 |
20130193938 | DEAD-TIME COMPENSATION IN A POWER SUPPLY SYSTEM - One embodiment includes a power supply system. The system includes a pulse-width modulation (PWM) system configured to generate a PWM signal. The system also includes a power stage comprising a gate driver, a high-side switch, and a low-side switch. The gate driver can be configured to alternately activate the high-side and low-side switches to provide an output signal to a load in response to the PWM signal, and to provide an activation dead-time between the alternate activation of the high-side and low-side switches. The system further includes a digital delay system configured to measure the activation dead-time and to add the measured activation dead-time to the activation of the high-side switch. | 08-01-2013 |
20130194112 | METHOD OF PROCESSING DATA SAMPLES AND CIRCUITS THEREFOR - The present invention relates to data manipulation and in particular incrementing, decrementing and comparing binary coded numbers, notably the manipulation of thermometer codes and the performance of arithmetic operations thereon. A method of processing data is provides which comprises receiving a series of data samples, each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N−1 bits represent the magnitude of the data sample and executing a predetermined sequence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples. | 08-01-2013 |
20130194935 | CIRCUIT TESTING ARRANGEMENT FOR SERIALISER/DESERIALISER - The present invention relates to a test arrangement for a serdes ip block and in particular provides a serdes test chip comprising a serdes instance to be tested and further instances of said serdes, said further instances constitution a data transfer path for data with which said serdes is to be tested. The data may come from a programmable gate array and enables the testing of data transfer schemes yet to be embodied in an integrated circuit ip block. | 08-01-2013 |
20130194975 | Switch Table Update using Demotion Command in PRIME - Embodiments of methods and systems for switch table update using demotion command in PRIME are presented. In one embodiment, the method is performed by a power line communication (PLC) device. For example, the PLC device may be a data concentrator. In such an embodiment, the method may include receiving a request for registration from a node in a PLC network. The method may also include determining whether the node was previously included in the network according to an alternate network topology configuration. Additionally, the method may include issuing a notification to a group of switch nodes in the network instructing the switch nodes to update respective switch tables in response to a determination that the node was previously included in the network according to an alternate network topology configuration. | 08-01-2013 |
20130195048 | Simultaneous Transmission in Multiple Timing Advance Groups - Systems and methods for specifying UE power control allocation for simultaneous transmission of PRACH in a secondary serving cell and PUCCH/PUSCH/SRS in a different serving cell in another timing advance group are disclosed. Rules are provided for prioritizing transmission of PRACH and/or other UL channels/signals. Additionally, UE power allocation is controlled for misaligned subframes across different timing advance groups. Latency of UL synchronization for a secondary serving cell is reduced by prioritizing PRACH retransmission. | 08-01-2013 |
20130195231 | AUTOMATIC GAIN CONTROL - The present invention relates to receiver circuitry and methods for the reception of serial data and in particular to the setting of a gain within such circuitry so that the data may be successfully received. It provides a data receiver that comprises an amplifier connected to receive a data waveform and to amplify it, the amplifier having a controllable gain, a test sampler connected to sample the amplified data waveform to a 1 or 0 based on a reference level, to provide a set of test bits and a gain adjusting circuit responsive to the number of test bits that are one of 1 or 0 in the set of the test bits. | 08-01-2013 |
20130196479 | DEFECT PREVENTION ON SRAM CELLS THAT INCORPORATE SELECTIVE EPITAXIAL REGIONS - An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions. | 08-01-2013 |
20130198418 | TRACE PROTOCOL EFFICIENCY - This invention controls data transmission from a data source to a sink. The data source buffers the data. T he data source signaling to transmit data upon storing a burst amount of data. The data source may include a plurality of data sources. A merge unit merges data by receiving and retransmitting data from each data source which signals to transmit and inserting a source identity block each time the merged data is received from a different source. | 08-01-2013 |
20130198579 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 08-01-2013 |
20130200253 | MULTIPLEXED READ-OUT ARCHITECTURE FOR CMOS IMAGE SENSORS - This invention targets improvement in CMOS sensors using a multiplexed read-out architecture in which pixels are output at the pixel V | 08-08-2013 |
20130200474 | Low Frequency CMUT with Vent Holes - A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves. | 08-08-2013 |
20130200936 | PHASE INTERPOLATOR WITH INDEPENDENT QUADRANT ROTATION - The present invention provides an improvement of a 4-quadrant clock phase interpolator design to allow independent rotation of the output clocks in steps of 90°. This feature is useful in clock/data recovery where the 90° “jumps” can be used as a coarse control to re-align the data capture clock to achieve any desired data word alignment and/or receive bus clock alignment. The phase interpolator has a switching circuit comprising a single level of switches; a set of four transistor loads; and a set of four current sources operable to be switched by the switching circuit through to any of the set of four transistor loads. | 08-08-2013 |
20130200954 | BEMF MONITOR GAIN CALIBRATION STAGE IN HARD DISK DRIVE SERVO INTEGRATED CIRCUIT - A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved. | 08-08-2013 |
20130201586 | Electrostatic Discharge Protection Apparatus - An electrostatic discharge (ESD)-triggered protection apparatus includes a first circuit and a second circuit. The first circuit includes an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse; a first ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to the ground rail; a control circuit that generates a control signal in response to the switching pulse. The second circuit includes at least one trigger cell buffer that is configured to receive the control signal and to control a second ESD discharge device such that the current generated by the ESD pulse is transferred to the ground rail. | 08-08-2013 |
20130202014 | DSSS Preamble Detection for Smart Utility Networks - Embodiments of the invention provide a method to detect DSSS preambles in smart utility networks. A DSSS signal is received by a receiver and a digital sequence of samples is formed. A difference value is calculated between pairs of samples in the digital sequence of samples to form a sequence of differential values. A known preamble differential value sequence is correlated with the sequence of differential values to form a sequence of correlation values. A location of the preamble is located in the digital sequence of samples corresponding to a peak in the sequence of correlation values that exceeds a threshold value. | 08-08-2013 |
20130202051 | Sub-Pictures for Pixel Rate Balancing on Multi-Core Platforms - A method for decoding a compressed video bit stream in a video decoder to recover a video sequence, the video decoder including a plurality of decoder processing cores is provided. The method includes determining that a picture is encoded in the compressed bit stream as a pre-determined number of independently encoded sub-pictures, and dispatching a first encoded sub-picture of the pre-determined number of sub-pictures to a first decoder processing core of the plurality of decoder processing cores and a second encoded sub-picture of the pre-determined number of sub-pictures to a second decoder processing core of the plurality of decoder processing cores, wherein the first encoded sub-picture and the second encoded sub-picture are independently decoded in parallel on the respective first and second decoder processing cores. | 08-08-2013 |
20130202072 | Data Transfer Clock Recovery for Legacy Systems - The present invention provides method and apparatus for adapting a relatively high data rate second order serdes receiver to receive relatively low data rate serial data, the receiver having jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the serdes receiver for frame realignment; and supplying to an output of the serdes receiver one of the bits of said same value from each frame at the low data rate. | 08-08-2013 |