Patent application number | Description | Published |
20110007262 | EYEGLASS WITH ENHANCED BALLISTIC RESISTANCE - An eyeglass is provided that can comprise a frame, a lens, and at least one retention component that can secure the lens relative to the frame. The frame can be configured to support at least one lens in a field of view of a wearer. The frame can include a first ear stem and a second ear stem that allows the frame to be worn on the wearer's head. The at least one retention component can be supported by the frame and/or the lens and can be movable or fixed relative to the frame and/or the lens. The retention component can engage an engagement portion of the frame and/or the lens for preventing the lens from separating from the frame in response to a ballistic event. | 01-13-2011 |
20120218504 | EYEGLASS WITH ENHANCED BALLISTIC RESISTANCE - An eyeglass is provided that can comprise a frame, a lens, and at least one retention component that can secure the lens relative to the frame. The frame can be configured to support at least one lens in a field of view of a wearer. The frame can include a first ear stem and a second ear stem that allows the frame to be worn on the wearer's head. The at least one retention component can be supported by the frame and/or the lens and can be movable or fixed relative to the frame and/or the lens. The retention component can engage an engagement portion of the frame and/or the lens for preventing the lens from separating from the frame in response to a ballistic event. | 08-30-2012 |
20140063437 | EYEWEAR HAVING MULTIPLE VENTILATION STATES - Eyewear is disclosed that can have multiple ventilation states providing different amounts of ventilation through the eyewear. The eyewear can include a lens and a frame. In some embodiments, the lens can be movable with respect to the frame to provide the multiple ventilation states. In some embodiments, the eyewear can include a gasket that removably attaches to the frame. In some embodiments, the gasket can be movable with respect to the frame to provide the multiple ventilation states. | 03-06-2014 |
20140063438 | EYEWEAR HAVING MULTIPLE VENTILATION STATES - Eyewear is disclosed that can have multiple ventilation states providing different amounts of ventilation through the eyewear. The eyewear can include a lens and a frame. In some embodiments, the lens can be movable with respect to the frame to provide the multiple ventilation states. In some embodiments, the eyewear can include a gasket that removably attaches to the frame. In some embodiments, the gasket can be movable with respect to the frame to provide the multiple ventilation states. | 03-06-2014 |
20150026858 | ADJUSTABLE FACIAL PROTECTION SYSTEMS AND METHODS OF MAKING AND USING THE SAME - Devices, systems, and methods, etc., that provide, in certain aspects, a two-point, adjustable, partially pliable, and releasable tensioning suspension that supports an anti-blunt-force frame connected to a protective helmet. The protective devices herein can be, for example, “sport-level” and “military/law enforcement-level.” The anti-blunt-force frame is positioned and balanced on the wearer's face by an impact absorbing face padding system, including a chin strap, cup or pad comprised of an impact protection material. Thus, in one aspect, the present devices, systems, methods, etc., include an adjustable facial protection system for a human comprising a crescent-shaped face protection element configured to withstand blunt force impact and a ballistic material element to prevent the penetration of ballistic and fragmentation projectiles at various force levels to meet different ballistic hazards. The systems can also include a protective helmet. | 01-29-2015 |
Patent application number | Description | Published |
20090323408 | METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 12-31-2009 |
20110085375 | METHODS FOR DETERMINING RESISTANCE OF PHASE CHANGE MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 04-14-2011 |
20110242878 | METHODS FOR OPERATING MEMORY ELEMENTS - Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 10-06-2011 |
20130141960 | METHODS AND SYSTEMS FOR OPERATING MEMORY ELEMENTS - Methods and systems for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into specific memory ranges can be accomplished. Furthermore, storage and/or display of this information may allow for the creation of resistance distribution histograms for modeling of one or more memory arrays. | 06-06-2013 |
20140269118 | INPUT BUFFER APPARATUSES AND METHODS - Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled between the first output signal and the second output signal. Additional apparatuses and methods are described. | 09-18-2014 |
20150077182 | APPARATUSES AND METHODS FOR INPUT BUFFER HAVING COMBINED OUTPUT - Apparatuses and methods are disclosed, including an apparatus that includes a first differential amplifier to amplify a difference between an input signal and a reference signal, and a second differential amplifier to amplify the difference between the input signal and the reference signal. The apparatus may further include an inverter circuit to receive an output signal of the first differential amplifier and another inverter circuit to receive an output signal of the second differential amplifier. The apparatus may include an output circuit to combine the outputs of the inverter circuits. The inverter circuits may each include an inverter and a shunt resistance. Additional apparatuses and methods are described. | 03-19-2015 |
20150116034 | INPUT BUFFER APPARATUSES AND METHODS - Apparatuses and methods are disclosed, including an apparatus with a first differential amplifier to amplify an input signal into a first output signal, a second differential amplifier to amplify the input signal into a second output signal that is complementary to the first output signal, and a feedback resistance coupled between the first output signal and the second output signal. Additional apparatuses and methods are described. | 04-30-2015 |
Patent application number | Description | Published |
20090273969 | CAPACITIVE DIVIDER SENSING OF MEMORY CELLS - The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell. | 11-05-2009 |
20100067286 | MEMORY SENSING DEVICES, METHODS, AND SYSTEMS - The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents. | 03-18-2010 |
20100067287 | TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device. | 03-18-2010 |
20100214821 | CAPACITIVE DIVIDER SENSING OF MEMORY CELLS - The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance variable memory cell, and a capacitive divider configured to generate multiple reference levels in association with the at least one resistance variable memory cell. | 08-26-2010 |
20110205791 | TEMPERATURE COMPENSATION IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes devices, methods, and systems for temperature compensation in memory devices, such as resistance variable memory, among other types of memory. One or more embodiments can include a memory device including a table with an output that is used to create a multiplication factor for a current to compensate for temperature changes in the memory device, where the output depends on an operating temperature of the memory device and a difference in the current between a highest specified operating temperature and a lowest specified operating temperature of the memory device. | 08-25-2011 |
20110310661 | MEMORY SENSING DEVICES, METHODS, AND SYSTEMS - The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents. | 12-22-2011 |
Patent application number | Description | Published |
20110055106 | INDUSTRY STANDARDS MODELING SYSTEMS AND METHODS - A method of developing a repeatable customer-specific software solution model includes creating a single industry standard model around an industry standard; creating a single industry software solution model from the industry standard model; and creating at least one customer-specific software solution model from the industry software solution model. The step of creating at least one customer-specific model is repeatable to create additional, different customer-specific software models. | 03-03-2011 |
20110055107 | INDUSTRY STANDARDS MODELING SYSTEMS AND METHODS - A method of developing a repeatable customer-specific software solution model includes creating a single industry standard model around an industry standard; creating a single industry software solution model from the industry standard model; and creating at least one customer-specific software solution model from the industry software solution model. The step of creating at least one customer-specific model is repeatable to create additional, different customer-specific software models. | 03-03-2011 |
20110055801 | INDUSTRY STANDARDS MODELING SYSTEMS AND METHODS - A method of developing a repeatable state-specific Medicaid management information system model includes creating a single Medicaid IT Architecture (MITA) Framework model around a Medicaid IT Architecture standard; creating a single Medicaid management information system model from the MITA Framework model; and creating at least one state-specific Medicaid management information system model from the Medicaid management information system model. The step of creating at least one customer-specific model is repeatable to create additional, different customer-specific software models. | 03-03-2011 |
20110055802 | INDUSTRY STANDARDS MODELING SYSTEMS AND METHODS - A method of developing a repeatable state-specific Medicaid management information system model includes creating a single Medicaid IT Architecture (MITA) Framework model around a Medicaid IT Architecture standard; creating a single Medicaid management information system model from the MITA Framework model; and creating at least one state-specific Medicaid management information system model from the Medicaid management information system model. The step of creating at least one customer-specific model is repeatable to create additional, different customer-specific software models. | 03-03-2011 |
Patent application number | Description | Published |
20090009792 | PRINTER FORMATTER IN A REMOVABLE CARD - A method and system for integrating a printer controller with a PC card. This system includes an office machine and a removable PC card that can be operationally coupled with the office machine. The office machine has a rendering engine for rendering images and a PC card slot for operationally coupling to a removable PC card and for receiving print engine ready data (PERD). The PC card slot is coupled to the print engine for providing the PERD thereto. The PC card has a printer formatter for receiving printer formatter ready data and for converting it into PERD and providing printer formatter functions. When the PC card is operationally coupled to the PC card slot, the print engine ready data can be selectively transferred from the PC card to the office machine. | 01-08-2009 |
20090013229 | BUILT-IN SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 01-08-2009 |
20090190176 | EFFICIENT PRINTER CONTROL ELECTRONICS - An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC. | 07-30-2009 |
20100047001 | MULTI-FUNCTION DEVICE ARCHITECTURE - Embodiments of the present invention provide a multi-function device including a housing, a printing assembly disposed within the housing, the printing assembly being configured to print a document, and a copying assembly comprising a complementary metal-oxide-semiconductor (CMOS) image sensor and an illumination source disposed within the housing, the copying assembly further including a substantially flat transparent surface disposed in an optical path of the CMOS image sensor, the substantially flat transparent surface to support an object for image capture by the CMOS image sensor, wherein the illumination source is configured to provide illumination during image capture. Other embodiments may be described and/or claimed. | 02-25-2010 |
20110138241 | BUILT-IN SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 06-09-2011 |
20110279868 | EFFICIENT PRINTER CONTROL ELECTRONICS - An apparatus (such as a printer) including a combination engine controller circuit board having a integrated circuit (IC) chip configured to process (format) incoming data as well as to control the operations of the apparatus is disclosed. The IC chip is adapted to receive and process data as well as to control the operations of the apparatus. For this reason, the IC chip is referred to as a combined controller IC. | 11-17-2011 |
20120036396 | Built-in-Self-Test Using Embedded Memory and Processor in an Application Specific Integrated Circuit - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 02-09-2012 |
20130080835 | BUILT-IN-SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTERGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC. | 03-28-2013 |
20140068333 | BUILT-IN-SELF-TEST USING EMBEDDED MEMORY AND PROCESSOR IN AN APPLICATION SPECIFIC INTERGRATED CIRCUIT - A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC. | 03-06-2014 |
Patent application number | Description | Published |
20090245009 | 256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. | 10-01-2009 |
20110261628 | 256 Meg dynamic random access memory - A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes. | 10-27-2011 |
Patent application number | Description | Published |
20090040194 | System and method of projecting an image on a physical substrate using a virtual image and a virtual plane - A method of projecting an image on a physical substrate using a virtual image and a virtual plane includes generating a virtual two dimensional plane and locating a position and orientation of a wand with respect to the virtual plane. The method further includes creating a virtual image on the virtual plane with the wand. An image can be projected on the physical substrate. The projected image corresponds to the virtual image created on the virtual plane. An associated image projection system includes a virtual two dimensional plane. A wand is configured to create a virtual image on the virtual two dimensional plane. The image projection system also has a physical substrate configured to receive a projected image. The projected image corresponds to the virtual image generated using the wand and the virtual two dimensional plane. | 02-12-2009 |
20090043913 | Cloning Hand Drawn Images - A method for cloning hand drawn images includes identifying, within an environment, a position of a wand with respect to each of a first plurality of user selected physical points. A virtual plane identified by the first plurality of points is defined. The virtual plane corresponds to a first marking surface. An electronic page is associated with the first virtual plane. A motion of the wand is tracked. The motion corresponds to a use of the wand to draw a first mark on the first marking surface. A path traced across the first virtual plane is identified. The path is defined by the tracked motion. The electronic page is updated to include a digital image representative of the path. The digital image is a clone of the mark. | 02-12-2009 |
20090135442 | SCANNING DEVICE HAVING VIRTUAL TRAYS INTO WHICH MEDIA SHEETS ARE LOADED FOR PRINTING COPY JOBS INITIATED AT THE SCANNING DEVICE - A scanning device receives selection of a given tray in relation to which a copy job is to be printed. The given tray is associated with attributes of media sheets loaded thereinto, and is associated with specific printing capabilities of a printing device of which the given tray is physically a part. The given tray is selected from a group of trays including at least virtual trays. Each virtual tray corresponds to a physical tray of a printing device other than the scanning device. The scanning device receives selection of characteristics of the copy job. The characteristics are selected from a group of characteristics encompassing all characteristics supported by the given tray. The scanning devices scans media sheets loaded thereinto to yield a file. The scanning device causes the file to be printed based on the characteristics selected. The file is printed on media sheets loaded into the given tray. | 05-28-2009 |
20100302150 | PEER LAYERS OVERLAPPING A WHITEBOARD - A method for displaying edits overlapping a whiteboard comprising creating peer layers overlapping the whiteboard for a peer and peers coupled to the peer and sending or receiving metadata of edits for updating one or more of the peer layers on the peer and the coupled peers in response to any of the peer layers being edited. | 12-02-2010 |
20110134148 | Systems And Methods Of Processing Touchpad Input - Systems and methods for processing touchpad input are disclosed. An example method comprises: translating a first position of an object relative to a touchpad into a second position within a selected fixed size input area of a plurality of fixed size input areas; and selecting the fixed input area responsive to an indication of a new input area. | 06-09-2011 |
Patent application number | Description | Published |
20090159560 | SELECTIVE ETCH CHEMISTRIES FOR FORMING HIGH ASPECT RATIO FEATURES AND ASSOCIATED STRUCTURES - An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as Si | 06-25-2009 |
20090176375 | Method of Etching a High Aspect Ratio Contact - Methods and an etch gas composition for etching a contact opening in a dielectric layer are provided. Embodiments of the method use a plasma generated from an etch gas composed of C | 07-09-2009 |
20090200614 | Transistors, Semiconductor Devices, Assemblies And Constructions - Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material. | 08-13-2009 |
20110316091 | Semiconductor Devices, Assemblies And Constructions - Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material. | 12-29-2011 |
20120068366 | SELECTIVE ETCH CHEMISTRIES FOR FORMING HIGH ASPECT RATIO FEATURES AND ASSOCIATED STRUCTURES - An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as Si | 03-22-2012 |
Patent application number | Description | Published |
20090291545 | PROCESS FOR ENHANCING SOLUBILITY AND REACTION RATES IN SUPERCRITICAL FLUIDS - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate. | 11-26-2009 |
20090318061 | SYSTEMS AND PADS FOR PLANARIZING MICROELECTRONIC WORKPIECES AND ASSOCIATED METHODS OF USE AND MANUFACTURE - Planarizing systems and methods of planarizing microelectronic workpieces using mechanical and/or chemical-mechanical planarization are disclosed herein. In one embodiment, a planarizing system includes a platen having a support surface carrying a planarizing pad. The planarizing pad includes an optically transmissive window extending through the planarizing pad that forms a continuous segment of the planarizing pad. The system also includes a workpiece carrier configured to move the workpiece relative to the planarizing pad and an optical monitor positioned proximate to the platen. The optical monitor emits light through the window and detects reflected light from the workpiece through the window. | 12-24-2009 |
20120015524 | Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate. | 01-19-2012 |
20120276725 | METHODS OF SELECTIVELY FORMING METAL-DOPED CHALCOGENIDE MATERIALS, METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SAME - Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide. | 11-01-2012 |
20130005153 | Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate. | 01-03-2013 |