Patent application number | Description | Published |
20090321932 | Coreless substrate package with symmetric external dielectric layers - A thin die Package Substrate is described that may be produced using existing chemistry. In one example, a package substrate is built over a support material. A dry film photoresist layer is formed over the package substrate. The support material is removed from the package substrate. The dry film photoresist layer is removed from the substrate and the substrate is finished for use with a package. | 12-31-2009 |
20110147933 | MULTIPLE SURFACE FINISHES FOR MICROELECTRONIC PACKAGE SUBSTRATES - Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask. | 06-23-2011 |
20120074209 | ELECTROLYTIC DEPOSITON AND VIA FILLING IN CORELESS SUBSTRATE PROCESSING - Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed. | 03-29-2012 |
20120077054 | ELECTROLYTIC GOLD OR GOLD PALLADIUM SURFACE FINISH APPLICATION IN CORELESS SUBSTRATE PROCESSING - Electronic assemblies including coreless substrates having a surface finish, and their manufacture, are described. One method includes electrolytically plating a first copper layer on a metal core in an opening in a patterned photoresist layer. A gold layer is electrolytically plated on the first copper layer in the opening. An electrolytically plated palladium layer is formed on the gold layer. A second copper layer is electrolytically plated on the palladium layer. After the electrolytically plating the second copper layer, the metal core and the first copper layer are removed, wherein a coreless substrate remains. Other embodiments are described and claimed. | 03-29-2012 |
20120161330 | DEVICE PACKAGING WITH SUBSTRATES HAVING EMBEDDED LINES AND METAL DEFINED PADS - Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing. | 06-28-2012 |
20130285242 | PIN GRID INTERPOSER - An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips. | 10-31-2013 |
20130320547 | ENABLING PACKAGE-ON-PACKAGE (POP) PAD SURFACE FINISHES ON BUMPLESS BUILD-UP LAYER (BBUL) PACKAGE - A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of the BBUL integrated circuit package has a surface finish that can be palladium, nickel-palladium, nickel-gold, nickel-palladium-gold, or palladium-nickel-palladium-gold. In some embodiments, the PoP pad surface finish can be formed using either an electroless or electrolytic process. | 12-05-2013 |
20140004361 | SUBSTRATE CORES FOR LASER THROUGH HOLE FORMATION | 01-02-2014 |
20140061927 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 03-06-2014 |
20140151875 | CROSSTALK POLARITY REVERSAL AND CANCELLATION THROUGH SUBSTRATE MATERIAL TUNING - Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s). | 06-05-2014 |
20140160707 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 06-12-2014 |
20140174808 | REDUCED CAPACITANCE LAND PAD - A land grid array (LGA) land pad having reduced capacitance is disclosed. The conductive portion of a land pad that overlaps a parallel ground plane within the substrate is reduced by one or more non-conductive voids though the thickness of the conductive portion of the land pad. The voids may allow the contact area of the land pad, as defined by the perimeter of the land pad, to remain the same while reducing the conductive portion that overlaps the parallel ground plane. Capacitance between the land pad and the parallel ground plane is reduced by an amount proportional to the reduction in overlapping conductive area. | 06-26-2014 |
20150021778 | CHIP PACKAGE INCORPORATING INTERFACIAL ADHESION THROUGH CONDUCTOR SPUTTERING - This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an insulator material, the insulator layer positioned with respect to a first conductive line, forming a second conductive line with respect to the insulator layer, wherein the insulator layer is positioned between the first conductive line and the second conductive line, forming a opening in the insulator layer between the first conductive line and the second conductive line, at least some of the insulator material within the opening being exposed, and chemically bonding a conductor to the at least some of the insulator material within the opening, wherein the conductor electrically couples the first conductive line to the second conductive line. | 01-22-2015 |