Patent application number | Description | Published |
20090055634 | COMPILING METHOD, APPARATUS, AND PROGRAM - Brings response time of a Web server and the like closer to a targeted value. A controller controlling the average response time elapsed between reception by information processing apparatus of a processing request and response of information processing apparatus to the processing request. The controller including: a section for obtaining a response time goal which is a target value of the average response time; a section for calculating a predicted response time which is a predicted value of the average response time at the time point when a predetermined reference period has elapsed from setting an operation mode in the information processing apparatus, the operation mode being any of a plurality of operation modes which provide different throughputs; and a section for setting the operation mode in the information processing apparatus if predicted response time calculated by the predicted response time calculating section is less than goal. | 02-26-2009 |
20090064112 | TECHNIQUE FOR ALLOCATING REGISTER TO VARIABLE FOR COMPILING - The present invention relates to allocating registers to variables in order to compile a program. In an embodiment of the present invention a compiler apparatus stores interference information indicating an interference relationship between variables, selects a register and allocates the register to each variables in accordance with a predetermined procedure, without allocating the same register to a set of variables having interference relationships. The compiler further replaces multiple variables having the same register allocated thereto with a new variable and generates an interference relationship by merging the interference relationships each concerning one of multiple variables. The compiler further updates interference information according to the generated interference relationship and allocates to each variable in the program using the new variable a register, selected in accordance with the predetermined procedure without allocating the same register to a set of variables having the interference relationships, based on the updated interference information. | 03-05-2009 |
20090077351 | Information processing device and compiler - Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas. | 03-19-2009 |
20100005457 | METHOD OF REDUCING LOGGING CODE IN A COMPUTING SYSTEM - A computing system for reducing logging code includes a virtual machine configured to control the flow of operations in the computing system and a compiler configured to receive bytecode instructions from the virtual machine and convert the bytecode instructions into machine instructions. The computing system also includes a compilation store configured to receive and store the machine instructions from the compiler and a recompilation store configured to receive and store recompiled machine instructions from the compiler. The system also includes a software transactional memory engine configured to receive instructions from the compilation store or, in the event that the recompilation store has recompiled machine instructions stored therein, from the recompilation store. | 01-07-2010 |
20110047364 | Recovering from an Error in a Fault Tolerant Computer System - A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed. | 02-24-2011 |
20130305231 | Profile-Based Global Live-Range Splitting - A system is provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph. | 11-14-2013 |
20130305232 | Profile-Based Global Live-Range Splitting - A computer program product is provided for splitting a live-range of a variable in frequently executed regions of program instructions. The live-range of a variable is split into multiple sub-ranges, each of which can be assigned to a different register or spilled into memory. The amount of spill code is reduced in frequently used regions of code by coalescing the live ranges based on profile information obtained after splitting the live ranges at every join and fork point in a control flow graph. | 11-14-2013 |
20150268941 | Globally Inline a Callee with High Cost-Effectiveness on the Basis Only of Profile Information in a Call Graph - A mechanism is provided to globally inline a callee with high cost-effectiveness on the basis only of profile information in a call graph, without looking through all call-graph edges. The mechanism provides a technique for inlining. An inline cost-effectiveness ratio for the callee reachable from a caller to be compiled is calculated. Calculating the inline cost-effectiveness ration includes using a ratio of a frequency of calls to the callee to a total of call frequencies as effectiveness and using a ratio of a code size of the callee to a total size of inlinable code as cost. A determination is made as to whether to inline the callee by comparing the inline cost-effectiveness ratio with a predetermined threshold. The callee is inlined into a source code in response to determining that the callee method is to be inlined. | 09-24-2015 |