Patent application number | Description | Published |
20080282119 | MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME - A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory. | 11-13-2008 |
20090129155 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell. | 05-21-2009 |
20090129156 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit. | 05-21-2009 |
20110055465 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device capable of storing a plurality of bits of data in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data to each threshold voltage of the memory cell, wherein in a first write operation that processes data in the first unit, the logic of one of the higher-order bit and the lower-order bit is fixed, and two pieces of multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the one memory cell in a pseudo binary state, and in a second write operation that processes data in a second unit larger than the first unit, a plurality of bits of input data is stored in the one memory cell in a multivalued state, and parity data for error correction in the second unit is stored in the memory cell. | 03-03-2011 |
20110228605 | NONVOLATILE MEMORY - A nonvolatile memory includes a memory cell array comprising an object block which includes a first data bit region capable of storing input data and a first flag bit region capable of storing first flag information, a redundant block which includes a second data bit region capable of storing input data and a second flag bit region capable of storing second flag information, and a special block including a special bit region capable of storing an object block address of the object block. The nonvolatile memory includes an object block retention part which retains the object block address. The nonvolatile memory includes an object block flag storage part which stores the first flag information therein. The nonvolatile memory includes a redundant block flag storage part which stores the second flag information. The nonvolatile memory includes a coincidence detection circuit which detects whether a block address which is input coincides with the object block address retained in the object block retention part. The nonvolatile memory includes a block changeover circuit which controls selection of one of the object block and the redundant block on the basis of the first and second flag information when the coincidence detection circuit has detected that the input block address coincides with the object block address. | 09-22-2011 |
20120063229 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 03-15-2012 |
20120155169 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device storing plural data bits in one memory cell by assigning multivalued data having a higher-order bit selected from one of a pair of data in a first unit and a lower-order bit selected from the other of the pair of data. In a first write operation processing data in the first unit, logic of one of the higher-order and the lower-order bit is fixed, and two multivalued data that maximize the difference between the threshold voltages are assigned, thereby storing one bit of input data in the memory cell in a pseudo binary state. In a second write operation processing data in a second unit larger than the first unit, plural input data bits in a multivalued state and parity data for error correction in the second unit are stored in the memory cell. | 06-21-2012 |
20120243320 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a plurality of memory cells, a logic gate chain, and a counter. The memory cells are capable of retaining data and are associated with the columns. The logic gate chain includes a plurality of logic gates associated with the columns. Each of the logical gates outputs a logical level to a next-stage logical gate in the series connection. The logic level indicates presence or absence of verify-failure in the associated column. The counter counts the number of output times of the logic level indicating the presence of the verify-failure in a final-stage logic gate of the series connection. A content indicated by the logic level output from each of the logic gates is inverted at a boundary of the logic gate associated with the column having the verify-failure in the logic gate chain. | 09-27-2012 |
20120246422 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding. | 09-27-2012 |
20130024606 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a first memory block and a second memory block, and a control circuit. In read operation, when a read target block is the first memory block, the control circuit determines whether the first memory block is single-level or multi-level according to a first flag, and stores a first determination result thereof. While the read target block is the first memory block, the control circuit reads the first memory block as single-level or multi-level according to the first determination result. When the read target block is changed from the first memory block to the second memory block, the control circuit erases the first determination result. | 01-24-2013 |