Tae Kyun Kim
Tae Kyun Kim, Seongnam-Si KR
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20080303874 | THERMAL INKJET PRINTHEAD - A thermal inkjet printhead that includes a substrate, a chamber layer stacked on the substrate, an ink chamber formed in the chamber layer, a heater to heat ink filled in the ink chamber to generate bubbles, and a nozzle layer stacked on the chamber layer, and including a nozzle formed in the nozzle layer, wherein a ratio of the volume of ink ejected through the nozzle with respect to the sum of the volumes of the ink chamber and the nozzle is in the range of approximately 40 to 60%. | 12-11-2008 |
20090174711 | APPARATUS AND METHOD FOR SIMPLIFYING THREE-DIMENSIONAL MESH DATA - An apparatus and method for simplifying 3-Dimensional (3D) mesh data are disclosed. The method includes measuring discrete curvature at each point of received 3D mesh data, calculating an error based on distance-curvature error metrics including the discrete curvature, first sorting a low curvature one of the calculated error values in a heap in ascending order, selecting a minimum error among the calculated errors, determining if the minimum error is less than a threshold, contracting an edge if the selected minimum error is greater than the threshold, and recalculating an error of a surface neighboring to a surface on which the contracted edge belongs and re-sorting the calculated error values. | 07-09-2009 |
20090195578 | INK CARTRIDGE, IMAGE FORMING APPARATUS, AND METHOD TO MANUFACTURE INK CARTRIDGE - An ink cartridge to prevent image degradation due to a misalignment of nozzles in a transfer direction of a printing medium and a transverse direction includes a print head substrate, a first head unit including at least one first print head chip which is disposed on the print head substrate and includes a plurality of first nozzles arranged in plural lines in a second direction perpendicular to a first direction which is a transfer direction of a printing medium, thereby forming a first line in the second direction, and a second head unit including at least one second print head chip which is disposed on the print head substrate and which has an ink jetting area overlapping a predetermined area of the first line, thereby forming an overlapping area, and which includes a plurality of second nozzles arranged in plural lines in the second direction, thereby forming a second line spaced from the first line, and dots formed by the first and the second nozzles, which neighbor each other in the overlapping area when jetting ink, have a gap with respect to the first and the second directions within a range satisfying the following equation: | 08-06-2009 |
20090237451 | INKJET PRINT HEAD AND MANUFACTURING METHOD THEREOF - An inkjet print head including a substrate and a first film member stacked on the substrate to form an ink path, and a manufacturing method thereof. The first film member includes a path-defining layer made of a photosensitive material and formed with the ink path, and an adhesive layer made of a photosensitive material and used to stably bond the path-defining layer to the substrate. With this configuration, the path-defining layer and the adhesive layer can be simultaneously stacked on the substrate and also, can be patterned simultaneously. | 09-24-2009 |
20100008692 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus including a power supply unit which supplies high voltage AC power, a developing unit having at least one developing roller to receive first AC power from the power supply unit to supply a developer to an image receptor, and an erasing unit to receive second AC power to attenuate high frequency noise of the developing unit. | 01-14-2010 |
20100285642 | Method of Doping Impurity Ions in Dual Gate and Method of Fabricating the Dual Gate using the same - A method of doping impurity ions in a dual gate includes doping first conductivity type impurity ions in a gate conductive layer over a semiconductor substrate having a first region and a second region, wherein the doping is performed with a concentration gradient so that a doping concentration in an upper portion of the gate conductive layer is higher than that in a lower portion; doping second conductivity type impurity ions in a portion of the gate conductive layer in the second region using a mask for opening the portion of the gate conductive layer in the second region; and diffusing the first conductivity type impurity ions and the second conductivity type impurity ions by performing heat treatment. | 11-11-2010 |
20110306192 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 12-15-2011 |
20120217570 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line. | 08-30-2012 |
20130288442 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 10-31-2013 |
20140348299 | X-RAY IMAGING APPARATUS AND METHOD - The present disclosure provides an X-ray imaging apparatus and method. When capturing an X-ray image using an automatic exposure request signal generated through detection of X-rays emitted from an X-ray generator, the X-ray imaging apparatus and method may verify validity of the automatic exposure request signal, thereby preventing unintentional generation of the automatic exposure request signal due to vibration, temperature change, noise, etc. | 11-27-2014 |
Tae Kyun Kim, Daejeon KR
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20100106338 | OPTIMIZED SYSTEM VOLTAGE CONTROL METHOD THROUGH COORDINATED CONTROL OF REACTIVE POWER SOURCE - Provided is an optimized system voltage control method through coordinated control of reactive power source, which analyzes the location for reactive power compensation and the effect of applying compensation equipment by calculating the reactive power and voltage sensitivity of a power system, thus improving the voltage quality of the power system. | 04-29-2010 |
20100179800 | MONITORING SYSTEM USING REAL-TIME SIMULATOR - A monitoring system using a real-time simulator, providing a simulation environment of a real electric power system that enables testing of a new electric power system control facility. The operation of the new electric power system control facility and effects thereof on a real electric power system can be evaluated before actual installation. The monitoring system includes a test piece installed in an electric power system; a simulator connected to the test piece, and deriving electric power system simulation data by simulating the electric power system with respect to the test piece; a multimedia interface (MMI) platform interworking with the simulator, providing the simulator with electric power system status data for simulating the electric power system, and receiving the electric power system simulation data from the simulator; and an MMI client interworking with the MMI platform to display the electric power system simulation data from the MMI platform. | 07-15-2010 |
20130234240 | SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity. | 09-12-2013 |
Tae Kyun Kim, Ichon-Si KR
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20100156487 | DLL CIRCUIT - A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal. | 06-24-2010 |
20110221496 | DLL CIRCUIT - A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal. | 09-15-2011 |
20120119357 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having stacked first and second chips includes a first through line of the first chip configured to receive a first coding signal and be electrically connected to a first through line of the second chip; a second through line of the first chip configured to receive a second coding signal; and a second through line of the second chip configured to be electrically connected to the first through line of the first chip and receive the first coding signal. | 05-17-2012 |
Tae Kyun Kim, Kyoungki-Do KR
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20080247256 | REFRESH SIGNAL GENERATOR OF SEMICONDUCTOR MEMORY DEVICE - A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a corresponding signal of a plurality of temperature sensing signals in response to a temperature sense driving signal, a power supply selecting unit for driving a driving voltage supply terminal to one of different voltage levels according to the plurality of temperature sensing signals, and an internal refresh signal generating unit for receiving a driving voltage from the power supply selecting unit and producing internal refresh signals at a constant interval. | 10-09-2008 |
20100093144 | SEMICONDUCTOR DEVICE UTILIZING A METAL GATE MATERIAL SUCH AS TUNGSTEN AND METHOD OF MANUFACTURING THE SAME - Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier. | 04-15-2010 |
Tae Kyun Kim, Uiwang-Si KR
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20090321687 | Electroconductive Thermoplastic Resin Composition and Plastic Article Including the Same - Disclosed herein are an electrically conductive thermoplastic resin composition and a plastic article including the same. The electrically conductive thermoplastic resin composition comprises about 80 to about 99.9 parts by weight of a thermoplastic resin, about 0.1 to about 10 parts by weight of carbon nanotubes, about 0.1 to about 10 parts by weight of an impact modifier, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes, and about to about 10 parts by weight of conductive metal oxide, based on a total of about 100 parts by weight of the thermoplastic resin and the carbon nanotubes. | 12-31-2009 |
Tae Kyun Kim, Chungcheongnam-Do KR
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20140037293 | HIGH SPEED OPTICAL TRANSCEIVER MODULE - Disclosed herein is a high speed optical transceiver module, which makes it possible to prevent a wavelength shift and thus to achieve low power and high efficiency by forming a hole with a predetermined depth in a stem heat sink for dissipating heat generated in an LD through a lower portion of a stem and putting a micro heater in the hole, thereby compensating for the temperature of the LD in order to prevent wavelength shift caused by the influence of the ambient temperature on an LD chip in a transistor outline (TO) when an un-cooled optical transceiver module is driven at low temperature and to prevent the communication from being impossible when the ambient temperature is lowered during the communication using a CWDM scheme. | 02-06-2014 |
Tae Kyun Kim, Seongnam-Si Gyeonggi-Do KR
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20130288441 | METHOD FOR FORMING IMPURITY REGION OF VERTICAL TRANSISTOR AND METHOD FOR FABRICATING VERTICAL TRANSISTOR USING THE SAME - A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region. | 10-31-2013 |
Tae Kyun Kim, London GB
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20140363047 | ESTIMATOR TRAINING METHOD AND POSE ESTIMATING METHOD USING DEPTH IMAGE - An estimator training method and a pose estimating method using a depth image are disclosed, in which the estimator training method may train an estimator configured to estimate a pose of an object, based on an association between synthetic data and real data, and the pose estimating method may estimate the pose of the object using the trained estimator. | 12-11-2014 |
20140363076 | ESTIMATOR TRAINING METHOD AND POSE ESTIMATING METHOD USING DEPTH IMAGE - An estimator training method and a pose estimating method using a depth image are disclosed, in which the estimator training method may train an estimator configured to estimate a pose of an object, based on an association between synthetic data and real data, and the pose estimating method may estimate the pose of the object using the trained estimator. | 12-11-2014 |
Tae Kyun Kim, Hwaseong-Si KR
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20150191478 | FUSED RING COMPOUND CONTAINING FURAN OR SALT THEREOF AND PHARMACEUTICAL COMPOSITION COMPRISING SAME - The present invention provides a fused ring compound containing furan or a pharmaceutically acceptable salt thereof, a method for preparing same, a pharmaceutical composition comprising same, and a use thereof. The fused ring compound containing furan or a pharmaceutically acceptable salt thereof inhibits the activity of phosphatidylinositol 3-kinase (PI3K) and can therefore be used in a pharmaceutical composition for treating and preventing respiratory diseases, inflammatory diseases, proliferative diseases, cardiovascular diseases, or central nervous system diseases which occur due to the over-activation of PI3K. | 07-09-2015 |
Tae-Kyun Kim, Suwon-Si KR
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20090174732 | IMAGE DISPLAY CONTROLLING METHOD AND APPARATUS OF MOBILE TERMINAL - An image display controlling apparatus and method, which can automatically divide an image signal according to the size of a screen in a mobile terminal. The image display controlling method includes generating frames having inner and outer edges based on an image signal; measuring a ratio of the size of each generated frame to the size of a display area; adjusting a number of frames to be displayed on the display area according to the measured ratio; and displaying a frame image corresponding to the adjusted number of frames on the display area. | 07-09-2009 |
20150061074 | MIM Capacitors with Diffusion-Blocking Electrode Structures and Semiconductor Devices Including the Same - A semiconductor device includes a MIM capacitor on a substrate. The MIM capacitor includes a dielectric region and first and second electrodes on opposite sides of the dielectric region. At least one of the first and second electrodes, e.g., an upper electrode, includes an oxygen diffusion blocking material, e.g., oxygen atoms, at a concentration that decreases in a direction away from the dielectric region. The at least one of the first and second electrodes may include a first layer having a first concentration of the oxygen diffusion blocking material and a second layer on the first layer and having a second concentration of the oxygen diffusion blocking material less than the first concentration. The at least one of the first and second electrodes may further include a third layer on the second layer and having a concentration of the oxygen diffusion blocking material less than the second concentration. | 03-05-2015 |
Tae-Kyun Kim, Gyeonggi-Do KR
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20100052748 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay locking unit configured to output an internal clock by delaying a reference clock as much as a first delay amount in response to a phase comparison result of comparing a phase of the reference clock with a phase of a feedback clock that is generated based on delay modeling of a semiconductor memory device, and a noise sensor configured to control variation of the first delay amount caused by an external noise to be less than a second delay amount after locking the internal clock. | 03-04-2010 |
20100164577 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data. | 07-01-2010 |
20100258861 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-14-2010 |
20110291727 | DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. | 12-01-2011 |
20120025878 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data. | 02-02-2012 |
20120064704 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED BIT LINES - A method for fabricating a semiconductor device includes forming a plurality of bodies isolated by trenches by etching a substrate, forming a buried bit line gap-filling a portion of each trench, forming an etch stop layer on an upper surface of the buried bit line; and forming a word line extended in a direction crossing the buried bit line over the etch stop layer. | 03-15-2012 |
20120218834 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a signal processing unit configured to generate a control signal corresponding to burst length information and an output controlling unit configured to control an output of a data strobe signal in response to the control signal. | 08-30-2012 |
20120261748 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-18-2012 |
20120262210 | CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes a delay unit configured to delay a reference input signal and generate a reference output signal and a storage unit configured to store a plurality of input signals in response to the reference input signal and output the stored signals in response to the reference output signal. | 10-18-2012 |
20130093484 | DELAY CIRCUIT AND METHOD FOR DRIVING THE SAME - A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal. | 04-18-2013 |
20130111081 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF | 05-02-2013 |
20130294133 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an I/O circuit configured to input/output a data signal; a plurality of internal circuits configured to transmit and receive the data signal to/from the I/O circuit; and a path provider configured to select one of a direct path to a target internal circuit or an indirect path to the target internal circuit that is longer than the direct path in response to one or more path control signals and use the selected path when the data signal is transmitted between the I/O circuit and the plurality of internal circuits. | 11-07-2013 |
20130331377 | DIAMINOPYRIMIDINE DERIVATIVES AND PROCESSES FOR THE PREPARATION THEREOF - The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT | 12-12-2013 |
20130338179 | DIAMINOPYRIMIDINE DERIVATIVES AND PROCESSES FOR THE PREPARATION THEREOF - The present invention provides a diaminopyrimidine derivative or its pharmaceutically acceptable salt, a process for the preparation thereof, a pharmaceutical composition comprising the same, and a use thereof. The diaminopyrimidine derivative or its pharmaceutically acceptable salt functions as a 5-HT | 12-19-2013 |
20140048841 | POLYAMIDE COMPOSITION HAVING HIGH THERMAL CONDUCTIVITY - The present invention relates to a composition based on a polyamide matrix having a high thermal conductivity and comprising specific proportions of alumina and of graphite and also a flame-retardant system. This composition may in particular be used for producing components for lighting devices comprising light-emitting diodes. | 02-20-2014 |
Tae-Kyun Kim, Seoul KR
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20100211461 | System for Displaying and Managing Information on Webpage Using Indicator - Disclosed is a system for displaying and managing information on a webpage using an indicator in which, a memo and so forth can be recorded in the desired contents of the webpage through the indicator and the URL of the webpage can be stored with the indicator to call out them at anytime, whereby providing a convenience in terms of search and manage of information. The system having a client server and a system server comprises an indicator displayed on a surface of specific contents of each webpage with reference to coordinate values corresponding to the specific contents of each webpage and for classifying and elaborating on the specific contents; an indicator generation module for generating the indicator comprising a block setting portion for predicting a width of the specific contents of the pertinent webpage, a coordinate setting portion for grasping the coordinate value of a webpage area corresponding to the specific contents predicted by the block setting portion, an input portion for inputting information to be recorded in the indicator, a storage portion for storing the coordinate value of the coordinate setting portion, an URL (uniform resource locator) of the pertinent webpage, and the input information of the input portion, and an output portion for outputting the indicator to the specific contents of the pertinent webpage based on the information stored in the storage portion; and an indicator database stored in the system server through the storage portion and collected according to a specific classification. | 08-19-2010 |
20150110245 | METHOD AND APPARATUS FOR OBTAINING X-RAY IMAGE OF REGION OF INTEREST OF OBJECT - A method of obtaining an X-ray image, the method including: obtaining a first image of an object; receiving a determination whether the first image includes an entirety of a region of interest (ROI); and obtaining a second image of the object, the second image including a portion of the ROI which is absent in the first image. | 04-23-2015 |
Tae-Kyun Kim, Ansan-Si KR
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20090166593 | Antistatic Thermoplastic Resin Composition - An antistatic thermoplastic resin composition includes a thermoplastic resin, an anionic antistatic agent, and a conductive metal oxide. The antistatic thermoplastic resin composition has enough antistatic properties to form various shapes of product, and it is particularly applicable for the production of housings of electro-electronic products or delivery trays for manufacturing an electro-electronic product. | 07-02-2009 |
Tae-Kyun Kim, Goyang-Si KR
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20090029738 | DIGITAL DEVICE AND METHOD FOR PROVIDING ADDITIONAL SERVICE BY USING THE SAME - A digital processing device capable of receiving an additional service is disclosed. In one aspect, a digital processing device includes i) an input unit, inputting a signal, ii) a subscriber identity unit, storing an identity code of a communication operator and generating a communication network access request message, iii) an additional service identity unit, storing an identity code of an additional service operator and generating an additional service request message and v) a control unit, generating a control signal allowing one of the subscriber identity unit and the additional service identity unit to be selectively driven. In accordance with at least one inventive embodiment, a user of the digital processing device can receive an additional service without his or her subscription to a specific communication operator and use various additional services in addition to the additional services provided by the subscribed communication operator. | 01-29-2009 |
20130225131 | DIGITAL DEVICE AND METHOD FOR PROVIDING ADDITIONAL SERVICE BY USING THE SAME - A digital processing device capable of receiving an additional service is disclosed. In one aspect, a digital processing device includes i) an input unit, inputting a signal, ii) a subscriber identity unit, storing an identity code of a communication operator and generating a communication network access request message, iii) an additional service identity unit, storing an identity code of an additional service operator and generating an additional service request message and v) a control unit, generating a control signal allowing one of the subscriber identity unit and the additional service identity unit to be selectively driven. In accordance with at least one inventive embodiment, a user of the digital processing device can receive an additional service without his or her subscription to a specific communication operator and use various additional services in addition to the additional services provided by the subscribed communication operator. | 08-29-2013 |
20140155035 | DIGITAL DEVICE AND METHOD FOR PROVIDING ADDITIONAL SERVICE BY USING THE SAME - A digital processing device capable of receiving an additional service is disclosed. In one aspect, a digital processing device includes i) an input unit, inputting a signal, ii) a subscriber identity unit, storing an identity code of a communication operator and generating a communication network access request message, iii) an additional service identity unit, storing an identity code of an additional service operator and generating an additional service request message and v) a control unit, generating a control signal allowing one of the subscriber identity unit and the additional service identity unit to be selectively driven. In accordance with at least one inventive embodiment, a user of the digital processing device can receive an additional service without his or her subscription to a specific communication operator and use various additional services in addition to the additional services provided by the subscribed communication operator. | 06-05-2014 |
Tae-Kyun Kim, Ichon KR
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20080278206 | DLL CIRCUIT - A DLL circuit can enable a semiconductor integrated circuit to perform a stable data processing operation. The DLL circuit includes a phase splitter that controls the phase of a delay clock, thereby generating a rising clock and a falling clock, an amplifying unit that performs differential amplification on the rising clock and the falling clock in response to first and second duty control signals, thereby generating an amplified rising clock and an amplified falling clock, and a duty cycle control unit that detects the duty rates of the amplified rising clock and the amplified falling clock, thereby generating the first and second duty control signals. | 11-13-2008 |
Tae-Kyun Kim, Taejeon KR
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20100004440 | Novel acyclic nucleoside phosphonate derivatives, salts thereof and process for the preparation of the same - The present invention relates to an acyclic nucleoside phosphonate derivative which is useful as an antiviral agent (particularly, against hepatitis B virus), pharmaceutically acceptable salts, stereoisomers, and a process for the preparation thereof. | 01-07-2010 |
Tae-Kyun Kim, Gyeong-Gi-Do KR
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20140235770 | POLYAMIDE COMPOSITION HAVING HIGH THERMAL CONDUCTIVITY - The present invention relates to a composition containing a polyamide matrix having high thermal conductivity, and including a nitride and a metal oxide, as well as, optionally, a flame-retardant system. Said composition can be used in particular for producing components for lighting apparatuses including light-emitting diodes. | 08-21-2014 |
Tae-Kyun Kim, Yongin-Si KR
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20090231385 | METHOD AND APPARATUS OF DOT COUNTING IN AN IMAGE FORMING APPARATUS - A method and apparatus of dot counting. The apparatus includes a nozzle portion having a length corresponding to a width of a printing medium, a dot counting unit to group head nozzles by position and to count a discharged dot count per line for each group, a control unit to determine whether the group has been used to print using the discharged dot count per line, a counter to count a number of times that the group is used to print based on the determination result, and a memory to store a sum of the counted numbers of times, in which the control unit controls the counter to count the number of times that the group is used to print with respect to each line of image data when the image data is created by a head chip, and a sum of the counted number of times is stored in the memory. | 09-17-2009 |
20110165768 | Semiconductor Device Having a Modified Recess Channel Gate and a Method for Fabricating the Same - A semiconductor device having a modified recess channel gate includes active regions defined by a device isolation layer and arranged at regular intervals on a semiconductor substrate, each active region extending in a major axis and a minor axis direction, a trench formed in each active region, the trench including a stepped bottom surface in the minor axis direction of the active region, and a recess gate formed in the trench. | 07-07-2011 |