Patent application number | Description | Published |
20130042215 | Methods and Apparatuses for Automated Circuit Design - Methods and apparatuses to automatically synthesize circuits. In one aspect of an embodiment, a method implemented on a data processing system for circuit synthesis comprises determining a Read Only Memory (ROM) of a design of a circuit, the ROM having predefined data when the circuit is initialized, and automatically generating an initialization circuit and a Random Access Memory (RAM) to implement the ROM, the initialization circuit to load the predefined data into the RAM when the circuit is initialized. | 02-14-2013 |
20130085738 | EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION - One embodiment of the present invention provides systems and techniques to execute a hardware simulation and verification solution on a multiprocessor system. The hardware simulation and verification solution can be partitioned into different modules which can include a simulation kernel to simulate changes in signal values, a value change dump module to store the changes in the signal values on a computer-readable storage medium, a functional coverage module to check functionality, a toggle coverage module to check signal toggling, an assertion engine to check complex behaviors, and a testbench module to generate test scenarios. Embodiments of the present invention can execute different modules on different processors, thereby improving performance. | 04-04-2013 |
20130086535 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system. | 04-04-2013 |
20130091480 | PARASITIC EXTRACTION FOR SEMICONDUCTORS - Parasitic extraction is a useful tool for analyzing and improving timing and other characteristics of semiconductor chips. Parasitic resistance and capacitance values are determined and stored in arrays. The parasitic values are extracted for multiple corners with a single analysis of the layout. Multi-corner analysis is performed using the parasitic values thereby optimizing the timing across various temperature and process operating points. | 04-11-2013 |
20130131857 | MODELING MASK ERRORS USING AERIAL IMAGE SENSITIVITY - One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent on the local and/or long-range pattern density. In some embodiments, the mask error modeling term can include an edge bias term and a corner rounding term. The edge bias term can be based on the sensitivity of the aerial image intensity to an edge bias, and the corner rounding term can be based on the sensitivity of the aerial image intensity to a corner rounding adjustment. | 05-23-2013 |
20130132564 | Electronic Device, System on Chip and Method for Monitoring a Data Flow - An electronic device is provided which comprises a plurality of processing units (IP | 05-23-2013 |
20130135933 | RFID TAG HAVING NON-VOLATILE MEMORY DEVICE HAVING FLOATING-GATE FETS WITH DIFFERENT SOURCE-GATE AND DRAIN-GATE BORDER LENGTHS - Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length. | 05-30-2013 |
20130145331 | SEQUENTIAL SIZING IN PHYSICAL SYNTHESIS - Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell. | 06-06-2013 |
20130145338 | MODELING TRANSITION EFFECTS FOR CIRCUIT OPTIMIZATION - Systems and techniques are described for determining a transition-effect model for a timing arc of a library cell. A transition-effect model can be determined for each library cell that is used during an optimization process. The transition-effect models enable an optimization system to estimate the impact of a change in the transition at an output of a driver gate on the delays of downstream gates without requiring to propagate the change in the transition to the downstream gates. Once determined, the transition-effect models can be used to compute one or more transition-induced penalties during circuit optimization. An optimization system can then use the one or more transition-induced penalties to determine whether or not to accept an optimizing transformation, or to discretize a solution obtained from a numerical solver. | 06-06-2013 |
20130145339 | EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION - Techniques and systems are described for improving the efficiency of timing calculations in numerical sequential cell sizing and for improving the efficiency of incremental slack margin propagation. Some embodiments cache timing-related information associated with a source driver that drives an input of a sequential cell that is being sized, and/or timing-related information for each output of the sequential cell that is being sized. The cached timing-related information for the source driver can be reused when sizing a different sequential cell. The cached timing-related information for the outputs of the sequential cell can be reused when evaluating alternatives for replacing the sequential cell. Some embodiments incrementally propagate slack margins in a lazy fashion (i.e., only when it is necessary to do so for correctness or accuracy reasons) while sizing gates in the circuit design in a reverse-levelized processing order. | 06-06-2013 |
20130152031 | METHOD AND APPARATUS FOR MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN - A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed. | 06-13-2013 |
20130159958 | EQUATION BASED TRANSIENT CIRCUIT OPTIMIZATION - Circuit simulation can be performed on digital, analog, and mixed signal types of circuitry. Phases of operation are identified for a circuit and transient behavior is analyzed. Multiple time points are identified and the circuit is replicated for those time points with evaluation of the circuitry performed at those various time points. Simultaneous optimization is performed across the time points. Transistors and other devices can have their lengths, widths, and number of fingers optimized. Simulation can include determining Kirchhoff current law equations for various nodes within the circuit. Equations describing device operation can include non-convex signomial equations and convex polynomial equations. | 06-20-2013 |
20130162326 | HIGH-VOLTAGE SWITCH USING THREE FETS - Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that provides the differentially switched high-voltage output signal includes two differentially coupled chains, each having at least three serially coupled FETs. The chains receive the high supply voltage and switch it to output the differential high-voltage output signal. A control/bias circuit provides a control voltage to at least one of the FETs in the chains, responsive to the control signal. | 06-27-2013 |
20130171548 | Patterning A Single Integrated Circuit Layer Using Automatically-Generated Masks And Multiple Masking Layers - A multiple mask and a multiple masking layer technique can be used to pattern an IC layer. A RET can be used to define one or more fine-line patterns in a first masking layer. Portions of the fine-line features are then removed or designated for removal using a mask. This removal/designation can include accessing a desired layout (with at least one layout feature including a fine-line feature and a coarse feature) and expanding layout features only in directions along critical dimensions of those layout features. Another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. Coarse feature(s) can be derived from the desired layout using a shrink/grow operation performed only in directions orthogonal to a critical dimension of the fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers. | 07-04-2013 |
20130174115 | MODELING OF CELL DELAY CHANGE FOR ELECTRONIC DESIGN AUTOMATION - An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V | 07-04-2013 |
20130187801 | GAIN AND DITHER CAPACITOR CALIBRATION IN PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES - A switching scheme is used during a calibration mode for determining calibration coefficients of each calibrated stage of a pipeline analog-to-digital converter (ADC). A calibrated stage of the pipeline ADC includes an amplifier for amplifying a residue voltage of the stage and a sampling capacitor comprising a plurality of sub-capacitors. The plurality of sub-capacitors have a first terminal connected to an input of amplifier and a second terminal connected to one or more switches that selectively couple the second terminal to the input terminal of the stage, a first reference voltage or a second reference voltage lower than the first reference voltage. During foreground calibration, a number of measurements are taken at an output of the amplifier to determine the calibration coefficient of the calibrated stage. | 07-25-2013 |
20130187802 | PIPELINE ANALOG-TO-DIGITAL CONVERTER STAGES WITH IMPROVED TRANSFER FUNCTION - A connection scheme is used to selectively connect a dither capacitor included in a calibrated stage of a pipeline analog-to-digital converter (ADC) in a way that reduces the output voltage swing of the stage. A first terminal of the dither capacitor is coupled to an input of the amplifier. A second terminal of the dither capacitor is coupled to either a first or second reference voltage dependent on a bit value in a Pseudo-Random Binary Sequence (PRBS) if a voltage received by the stage is within a first voltage range. If the stage received voltage is within a second range, the second terminal is coupled to the first reference voltage independent of the PRBS. If the stage received voltage is within a third range, the second terminal is coupled to the second reference voltage independent of the PRBS. | 07-25-2013 |
20130191346 | SIMULATION CONTROL TECHNIQUES - Simulation control techniques include shutting down peer processes and user code modules, storing an image of a simulation as a checkpoint after the peer processes and user code modules are shutdown, and re-starting user code modules and peer processes after storing an image of the simulation. The resulting checkpoint and processes can be used for restoring from a checkpoint or restarting a new simulation environments having peer processes such as debuggers coupled to the simulation. | 07-25-2013 |
20130200945 | STRUCTURES AND METHODS FOR OPTIMIZING POWER CONSUMPTION IN AN INTEGRATED CHIP DESIGN - Various methods and apparatuses are described for a power distribution structure. In an embodiment, an integrated circuit contains power gating cells that each contain Metal Oxide Semiconductor (MOS) device switches located relative in the power distribution structure to power up and down a block of logic containing a plurality of individual cells using these MOS device switches. The MOS device switches can be tuned to requirements of a target block of logic in order to meet its optimal voltage drop requirements during its active operational state while minimizing leakage current in its off state. | 08-08-2013 |
20130212566 | COORDINATING AND CONTROLLING DEBUGGERS IN A SIMULATION ENVIRONMENT - A simulation environment, in one embodiment, includes a debugger server, one or more debuggers, and one or more debugger adapters. Each debugger adapter couples a corresponding debugger to the debugger server. The debugger server coordinates the run mode of the debugger adapters. Each debugger adapter controls the run mode of its corresponding debugger. | 08-15-2013 |