Patent application number | Description | Published |
20080294282 | USE OF LOGICAL LOTS IN SEMICONDUCTOR SUBSTRATE PROCESSING - In some embodiments, a method of processing substrates is provided that includes (1) grouping substrates in a plurality of substrate carriers as a logical lot; (2) processing the logical lot as if the substrates were stored in a single substrate carrier; and (3) performing metrology on a representative subset of substrates in the logical lot. Numerous other embodiments are provided. | 11-27-2008 |
20090202336 | METHODS AND APPARATUS FOR AN EFFICIENT HANDSHAKE BETWEEN MATERIAL HANDLING AND MATERIAL PROCESSING DEVICES FOR SAFE MATERIAL TRANSFER - Methods and systems are provided. The invention includes performing a handshake directly between a load port associated with process equipment and material handling equipment; and transferring a carrier between the material handling equipment and the load port based on the handshake. Numerous other aspects are provided. | 08-13-2009 |
20100179683 | METHODS, SYSTEMS AND APPARATUS FOR RAPID EXCHANGE OF WORK MATERIAL - Systems, apparatus and methods for the rapid exchange of work material in a facility processing substrates (e.g., LCD panels, solar panels, semiconductor wafers, or the like) are disclosed. The system may include load ports associated with a process tool, local storage units, and a work material exchange apparatus adapted to rapidly exchange work material at the ports, units, or other exchange locations. The work material exchange apparatus may include two or more end effectors coupled to one or more actuator members and which may be adapted to rapidly exchange two or more carriers containing work material at an exchange location. | 07-15-2010 |
20130039734 | ROBOT SYSTEMS, APPARATUS, AND METHODS ADAPTED TO PROCESS SUBSTRATES IN MULTIPLE TIERS - Substrate transport systems, apparatus, and methods are described. In one aspect, the systems are disclosed having vertically stacked transfer chamber bodies. In one embodiment, a common robot apparatus services process chambers or load lock chambers coupled to upper and lower transfer chamber bodies. In another embodiment, separate robot apparatus service the process chambers and/or load lock chambers coupled to upper and lower transfer chamber bodies, and an elevator apparatus transfers the substrates between the various elevations. Degassing apparatus are described, as are numerous other aspects. | 02-14-2013 |
20140262035 | SEMICONDUCTOR DEVICE MANUFACTURING PLATFORM WITH SINGLE AND TWINNED PROCESSING CHAMBERS - A transfer chamber for semiconductor device manufacturing includes (1) a plurality of sides that define a region configured to maintain a vacuum level and allow transport of substrates between processing chambers, the plurality of sides defining a first portion and a second portion of the transfer chamber and including (a) a first side that couples to two twinned processing chambers; and (b) a second side that couples to a single processing chamber; (2) a first substrate handler located in the first portion of the transfer chamber; (3) a second substrate handler located in the second portion of the transfer chamber; and (4) a hand-off location configured to allow substrates to be passed between the first portion and the second portion of the transfer chamber using the first and second substrate handlers. Method aspects are also provided. | 09-18-2014 |
20150045961 | SUBSTRATE PROCESSING SYSTEMS, APPARATUS, AND METHODS WITH FACTORY INTERFACE ENVIRONMENTAL CONTROLS - Electronic device processing systems including environmental control of the factory interface are described. One electronic device processing system has a factory interface having a factory interface chamber, a load lock apparatus coupled to the factory interface, one or more substrate carriers coupled to the factory interface, and an environmental control system coupled to the factory interface and operational to monitor or control one of: relative humidity, temperature, an amount of oxygen, or an amount of inert gas within the factory interface chamber. In another aspect, purge of a carrier purge chamber within the factory interface chamber is provided. Methods for processing substrates are described, as are numerous other aspects. | 02-12-2015 |
Patent application number | Description | Published |
20090020754 | Test structure for determining gate-to-body tunneling current in a floating body FET - In one disclosed embodiment, the present test structure for determining gate-to-body current in a floating body FET includes a floating body FET situated over a semiconductor layer, where the floating body FET includes a first gate and first and second source/drain regions. The floating body test structure further includes a second gate and a first contact situated over the first source/drain region. A gate-to-channel current measured between the second gate and the first contact is utilized to determine the gate-to-body tunneling current. The gate-to-body tunneling current can be determined by subtracting the gate-to-channel current from twice a source/drain current of the floating body FET. The test structure may also include a second contact situated on a doped region in the semiconductor layer, where a diode current flow through the doped region determines a body voltage for the floating body FET. | 01-22-2009 |
20090021280 | Method and test system for determining gate-to-body current in a floating body FET - In one disclosed embodiment, the present method for determining a gate-to-body current for a floating body FET comprises measuring at least three unique gate-to-body currents corresponding to at least three unique body-tied FET structures, determining at least three unique relationships between the at least three unique gate-to-body currents and at least three gate-to-body current density components for the at least three unique body-tied FET structures, and utilizing those at least three unique relationships to determine the at least three gate-to-body current density components; wherein one of the gate-to-body current density components is used to determine the gate-to-body current for the floating body FET. In one embodiment, a test structure implements a method for determining a gate-to-body current in a floating body FET. The determined gate-to-body current may be used to predict hysteresis in the floating body FET. | 01-22-2009 |
20090076750 | INTEGRATED CIRCUIT TESTER INFORMATION PROCESSING SYSTEM - A method for operating an integrated circuit tester information processing system includes measuring current information from test structures for an integrated circuit having dual stress liners; selecting currents from the current information or stored current information; deriving a scaling factor with the currents for a stress contribution based on an active area of a circuit element in the integrated circuit; and correlating the stress contribution with the integrated circuit. | 03-19-2009 |