Patent application number | Description | Published |
20090190387 | Semiconductor device - A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region. | 07-30-2009 |
20090207654 | Semiconductor device including plurality of parallel input/output lines and methods of fabricating and using the same - Provided are semiconductor devices and methods for fabricating and using the semiconductor devices, wherein the semiconductor devices may include a first element, a second element, and a plurality of parallel IO lines connecting the first element with the second element. The plurality of IO lines may have different lengths and the shortest IO line from among the plurality of the IO lines may be adjacent to a longest IO line from among the plurality of the IO lines. | 08-20-2009 |
20100059856 | Method of configuring a semiconductor integrated circuit involving capacitors having a width equal to the length of active resistors - A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell. | 03-11-2010 |
20110192655 | Laundry weight sensing method - A laundry weight sensing method. A motor is consecutively turned on and off plural times, the number of pulses output from a counter electromotive force detector according to counter electromotive force of the motor when the motor is finally turned off is counted, and a laundry weight is sensed using the counted number of pulses. | 08-11-2011 |
20110296876 | Pulsator device for washing machines and washing machine having the same - A pulsator device in which a second pulsator performs different movements according to rotating directions of a first pulsator so as to reduce water consumption and improve washing performance. | 12-08-2011 |
20120146119 | Semiconductor Device - A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region. | 06-14-2012 |
20130242643 | SEMICONDUCTOR MEMORY DEVICE INCLUDING POWER DECOUPLING CAPACITOR - A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer. | 09-19-2013 |
20130294141 | MEMORY DEVICE INCLUDING ANTIFUSE MEMORY CELL ARRAY AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE - A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows. | 11-07-2013 |
20130299890 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING CAPACITOR - A semiconductor device includes: a second transistor having a second conductive type formed on a first well region having a first conductive type; a first transistor having a first conductive type formed on a second well region having a second conductive type; a first well guard ring having the first conductive type, the first well guard ring including at least a first portion formed between the first transistor and the second transistor; a second well guard ring having the first conductive type, the second well guard ring including at least a first portion formed between the first transistor and the second transistor; and a first capacitor formed on at least one of the first well region and the second well region, and located between the first portion of the first well guard ring and the first portion of the second well guard ring. | 11-14-2013 |
20130322150 | MEMORY DEVICE INCLUDING PROGRAMMABLE ANTIFUSE MEMORY CELL ARRAY - A memory device includes a memory cell array, a column decoder, and a row decoder. The memory cell array includes a plurality of antifuse memory cells arranged in rows and columns, each of the antifuse memory cells connected to one of a plurality of word lines, one of a plurality of high-voltage lines, and one of a plurality of bit lines. The column decoder is arranged at a first side of the memory cell array and configured to select one bit line among the bit lines. The row decoder is arranged parallel to the column decoder in a first direction, and configured to select one word line among the word lines. | 12-05-2013 |