Patent application number | Description | Published |
20120250587 | FULL DUPLEX COMMUNICATION CIRCUIT AND METHOD THEREFOR - Duplex communications are facilitated. In connection with various example embodiments, current sources are used to drive transistor-based circuits coupled across a first resistive circuit, to send signals on a communications medium. While driving the transistor-based circuits, the current sources are used to drive reference transistor-based circuits coupled across a second resistive circuit. A differential output signal based upon a power-related value across the first resistive circuit, less a power-related value across the second resistive circuit. This differential output signal characterizes a power-related value corresponding to a received signal on the communications medium, as gleaned from a total signal corresponding to both transmitted and received signals, less a signal corresponding to the transmitted signal. | 10-04-2012 |
20130070613 | SYSTEM AND METHOD FOR TESTING A COMMUNICATIONS NETWORK HAVING A CENTRAL BUS GUARDIAN (CBG) TO DETECT A FAULTY CONDITION ASSOCIATED WITH THE CBG - Systems and methods for testing a communications network having a central bus guardian (CBG) to detect a faulty condition associated with the CBG are described. In one embodiment, a method for testing a communications network having a CBG to detect a faulty condition associated with the CBG includes supplying a communications schedule to the CBG, causing test data to be transmitted between different buses that are connected to the CBG according to the communications schedule, and determining the faulty condition associated to with the CBG based on whether or not the test data is received according to the communications schedule. Other embodiments are also described. | 03-21-2013 |
20130070782 | SYSTEM AND METHOD FOR ENCODING A SLOT TABLE FOR A COMMUNICATIONS CONTROLLER - Systems and methods for encoding a slot table for a communications controller of a communications network are described. In one embodiment, a method for encoding a slot table for a communications controller of a communications network includes classifying branches of the communications network that are connected to the communications controller into at least one group, where each of the at least one group includes multiple branches, and generating a slot table entry for a time slot for accessing the communications network through the communications controller based on the at least one group. Other embodiments are also described. | 03-21-2013 |
20130070783 | SYSTEM AND METHOD FOR CREATING A SLOT TABLE ENTRY ADDRESS FOR A COMMUNICATIONS DEVICE - An invention for generating a slot table entry address for a communications device of a communications network includes a method that involves processing a slot counter value according to a configuration setting value to produce a processed slot counter value, the slot counter value identifying a time slot of data communications of the communications network, masking a cycle counter value according to the configuration setting value to generate a masked cycle counter value, where the cycle counter value identifies a communications cycle containing the time slot, and processing the processed slot counter value and the masked cycle counter value to generate a slot table entry address such that a corresponding slot table entry of the time slot of the communications cycle in a slot table is accessed by the communications device at the slot table entry address. | 03-21-2013 |
20130073764 | CENTRAL BUS GUARDIAN (CBG) AND METHOD FOR OPERATING CBG - Central bus guardians (CBGs) and methods for operating a CBG are described. In one embodiment, a method for operating a CBG includes performing race arbitration among the buses connected to the CBG to select a winner bus for a time slot, and selectively forwarding data received at the CBG from the winner bus to a destination bus in the time slot based on whether the winner bus or the destination bus has a connection to an external network with respect to the application network and whether a communications device connected to the winner bus or the destination bus performs a critical function. Other embodiments are also described. | 03-21-2013 |
20130094603 | DEVICE AND METHOD FOR ENCODING BITS TO SYMBOLS FOR A COMMUNICATION SYSTEM - A device and method for encoding bits to symbols for a communication system are described. In one embodiment, a method for encoding bits to symbols for a communication system includes receiving a set of N-bit data to be transmitted, where N is an integer, generating side scrambling values using a polynomial, scrambling the set of N-bit data using the side scrambling values to produce scrambled data, mapping the scrambled data to a particular set of M symbols from a plurality of sets of M symbols, where M is an integer and M is smaller than N, and outputting the particular set of M symbols for transmission over a transmission medium. Other embodiments are also described. | 04-18-2013 |
20140003223 | NETWORK COMMUNICATION APPARATUS, SYSTEM AND METHOD | 01-02-2014 |
20140003253 | COMMUNICATIONS APPARATUS, SYSTEM AND METHOD WITH SCHEDULE CHECKING | 01-02-2014 |
20140003447 | COMMUNICATIONS APPARATUS, SYSTEM AND METHOD WITH ERROR MITIGATION | 01-02-2014 |
20140023132 | COMMUNICATIONS WITH ADAPTIVE EQUALIZATION - Signal equalization is facilitated in a manner that provides for feedback operation with desirable equalization operation. As consistent with one or more embodiments, a sign is assigned to received signals by generating an output that is an absolute value of the received signals, and a comparator processes the output and to generate a signal having a voltage level limited to a predetermined value. A sign of a signal output by an equalizer is detected and used to assign a sign to the output of the comparator. A summation circuit sums the output of the equalizer with the output of the comparator, and provides the sum to the equalizer as an error signal. The equalizer modifies a frequency component of received signals based on the error signal. | 01-23-2014 |
20140334291 | COMMUNICATIONS APPARATUS, SYSTEM AND METHOD WITH ERROR MITIGATI - Data communications are effected over one or more network branches to ensure appropriate receipt of data at different devices on the network. In accordance with an example embodiment, time-based communications are effected for a plurality of different network devices, at least two of which are connected to a common wired network link, with each network device being assigned to communicate during different time slots within a communication cycle. Each communication received on the common wired network link is assessed as being error-indicative or not error-indicative. In response to a received communication on the common wired network link being assessed as being error-indicative, the common wired network link is operated to corrupt data received on the branch, such as by driving the branch during a time slot in which the error-indicative communication is received, therein ensuring that other network devices disregard the data received during that time slot. | 11-13-2014 |
20140348276 | SYSTEM AND METHOD FOR OPERATING A FILTER FOR ECHO CANCELLATION - Systems and methods for operating a filter for echo cancellation are described. In one embodiment, a method for operating a filter for echo cancellation involves monitoring at least one of a filter coefficient of the filter and an echo cancellation error to generate a monitoring result and, in response to the monitoring result, adjusting at least one of delay elements and filter taps of the filter to vary an impulse response of the filter. Other embodiments are also described. | 11-27-2014 |
20140362893 | SYSTEM AND METHOD FOR BIT PROCESSING IN A CENTRAL NETWORK COMPONENT - A central network component, a FlexRay-compatible central network component, and a method for bit processing in a central network component are described. In one embodiment, a central network component for facilitating communication among communication nodes includes a bit oversampling module configured to oversample bits received from a first communication node of the communication nodes with an oversampling factor to generate oversampled bit streams, a time point selection module configured to select time points in the oversampled bit streams, where the time points correspond to inner samples of the oversampled bit streams with respect to the oversampling factor, and a bit outputting module configured to output the inner samples to a second communication node of the communication nodes between the time points. Other embodiments are also described. | 12-11-2014 |
20150074631 | DATA ERROR SUSCEPTIBLE BIT IDENTIFICATION - As consistent with one or more embodiments, electronic circuitry is characterized to provide an indication of susceptibility of the circuitry to error. As consistent with one or more embodiments, bits corresponding to a circuit component of a circuit design are evaluated using a software program that characterizes a hardware description language representing the circuit components and their interconnectivity. A noise power value is calculated for each bit, and bits are identified as being susceptible to data error based upon the noise power value and a signal-to-noise (SNR) ratio reference value. A characterization of the circuit components (e.g., a quality factor) is provided based upon a number of bits susceptible to data errors. | 03-12-2015 |