Patent application number | Description | Published |
20130233599 | SUBSTRATE FOR POWER MODULE - Disclosed herein is a substrate for a power module. The substrate may include a metal base substrate, an insulating layer formed on the metal base substrate and including a plurality of insulating adhesion layers and a ceramic filler layer formed on a joining interface between the plurality of insulating adhesion layers, and a circuit layer formed on the insulating layer. | 09-12-2013 |
20130270687 | DOUBLE SIDE COOLING POWER SEMICONDUCTOR MODULE AND MULTI-STACKED POWER SEMICONDUCTOR MODULE PACKAGE USING THE SAME - Disclosed herein is a double side cooling power semiconductor module including: a first cooler having a concave part formed in one surface thereof in a thickness direction; a first semiconductor chip mounted on the concave part of the first cooler; a second cooler having one surface and the other surface and formed on one surface of the first cooler so that one surface thereof contacts the first semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor chip mounted on the circuit board; and a flexible substrate having a circuit layer electrically connecting the first and second semiconductor chips to each other. | 10-17-2013 |
20130343002 | HEAT DISSIPATION SYSTEM FOR POWER MODULE - Disclosed herein is a heat dissipation system for a power module, including: first cooling medium flow parts and second cooling medium flow parts allowing cooling media to flow in first and second directions, respectively. | 12-26-2013 |
20140098586 | GATE DRIVING CIRCUIT AND INVERTER HAVING THE SAME - There is provided an inverter including: an inverter unit including at least one inverter arm having a plurality of switches, and switching the input power according to control to output an alternating current power; at least one driving unit including at least one high voltage gate driving unit having a plurality high voltage gate drivers connected to one another in series between an input terminal of an instruction signal instructing a switching control of an inverter unit and an output terminal of a control signal controlling switching of the inverter unit to control switching driving of a high side switch and including at least one low voltage gate driver to control switching driving of a low side switch; and at least one bootstrap unit charging/discharging and dividing a voltage generated at the time of switching the plurality of switches according to switching control of the driving unit. | 04-10-2014 |
20140152208 | POWER FACTOR CORRECTION DEVICE, POWER SUPPLY, AND MOTOR DRIVER - There is provided a power factor correction device including, a first switch switching input power to adjust a phase difference between a current and a voltage of the input power, a second switch switched on before the first switch is switched on to form a transfer path for residual power in the first switch, a first inductor charging and discharging energy according to switching of the first switch, and a second inductor adjusting an amount of current flowing through the second switch according to switching of the second switch, wherein the first inductor and the second inductor are inductively coupled. | 06-05-2014 |
20140160817 | POWER FACTOR CORRECTION CIRCUIT AND POWER SUPPLY INCLUDING THE SAME - There are provided a power factor correction circuit, and a power supply including the same, the power factor correction circuit including a main switch adjusting a phase difference between a current and a voltage of input power, a main inductor storing or discharging the power according to switching of the main switch, a snubber circuit unit including a snubber switch forming a transfer path for surplus power present before the main switch is turned on and a snubber inductor adjusting an amount of a current applied to the snubber switch, and a reduction circuit unit including an auxiliary inductor inductively coupled to the snubber inductor and an auxiliary resistor consuming power induced from the snubber inductor through the auxiliary inductor. | 06-12-2014 |
Patent application number | Description | Published |
20130069569 | POWER FACTOR CORRECTION CIRCUIT, AND POWER SUPPLY DEVICE AND MOTOR DRIVING DEVICE HAVING THE SAME - There are provided a power factor correction circuit capable of transferring extra power to a ground before performing switching for a power factor correction to thereby reduce a switching loss generated in switching for a power factor correction, and a power supply device and a motor driving device having the same. The power factor correction circuit includes: a main switch switching input power to adjust a phase difference between a current and a voltage of the input power; and an auxiliary switch switched on before the main switch is switched on, to thereby form a transmission path for extra power of the main switch. | 03-21-2013 |
20130270689 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR MODULE, AND MOUNTING STRUCTURE THEREOF - Provided are a semiconductor package capable of packaging and modularizing power semiconductor devices which are difficult to integrate due to heat generation, a semiconductor package module using the same, and a mounting structure thereof. The semiconductor package includes: a common connection terminal formed to have a flat plate shape; first and second electronic devices respectively bonded to both surfaces of the common connection terminals; first and second connection terminals having a flat plate shape and bonded to the first electronic device; and a third connection terminal having a flat plate shape and bonded to the second electronic device. | 10-17-2013 |
20130341782 | SEMICONDUCTOR PACKAGE MODULE - There is provided a semiconductor package module, and more particularly, a semiconductor package module constituted by modularizing power semiconductor devices incapable of being able to be easily integrated due to heat generated therefrom. To this end, the semiconductor package module includes a plurality of semiconductor packages; and a plurality of semiconductor packages; and a heat dissipation member having a pipe shape including a flow channel formed therein and including at least one or more through holes into which the semiconductor packages are inserted. | 12-26-2013 |
20140001619 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME | 01-02-2014 |
20140003107 | GATE DRIVER CIRCUIT FOR INDUCTIVE LOAD, INVERTER MODULE, AND INVERTER APPARATUS HAVING THE SAME | 01-02-2014 |
20140015003 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed herein are a semiconductor device, and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a base region formed on an upper region of an inside of the semiconductor substrate, at least one gate electrode that penetrates through the base region and has an inverted triangular shape, a gate insulating film formed to enclose an upper portion of the semiconductor substrate and the gate electrode, an inter-layer insulating film formed on an upper portion of the gate electrode and the gate insulating film, an emitter region formed inside the base region and on both sides of the gate electrode, an emitter metal layer formed on an upper portion of the base region and inter-layer insulating film, and a buffer region formed to enclose a lower portion of the gate electrode and to be spaced apart from the base region. | 01-16-2014 |
20140084693 | GATE DRIVING CIRCUIT AND INVERTER HAVING THE SAME - An inverter includes an inverter unit including at least one inverter arm having at least one high side switch and at least one low side switch connected to each other in series between a ground and an input power terminal providing input power having a preset voltage level, and switching the input power to output AC power; and a high voltage gate driving circuit unit including at least one high voltage gate driving unit having a plurality of high voltage gate drivers connected in series between an input terminal of an instruction signal requesting a switching control of the inverter unit and an output terminal of a control signal controlling switching of the inverter unit, such that switching of the high side switch is controlled, and voltage generated at the time of switching the high side switch is divided and applied to the plurality of high voltage gate drivers. | 03-27-2014 |
20140092563 | HEAT RADIATING SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a heat radiating substrate including: a heat radiating plate including a plurality of holes having a predetermined depth and formed in a lower portion of one side thereof; a conductor pattern layer formed on the heat radiating plate and including a mounting pad on which a control device and a power device are mounted and a circuit pattern; and an insulating layer formed between the heat radiating plate and the conductor pattern layer. | 04-03-2014 |
20140110156 | HEAT RADIATING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a heat radiating substrate including: a heat radiating plate having a step formed so that one side and the other side thereof have thicknesses different from each other; a conductor pattern layer formed over the heat radiating plate and including a mounting pad on which a control device and a power device are mounted and a circuit pattern; and an insulating layer formed between the heat radiating plate and the conductor pattern layer. | 04-24-2014 |
20140117408 | UNIT POWER MODULE AND POWER MODULE PACKAGE COMPRISING THE SAME - Disclosed herein is a unit power module including: a first semiconductor chip having one surface on which a 1-1-th electrode and a 1-2-th electrode spaced apart from the 1-1-th electrode are formed and the other surface on which a 1-3-th electrode is formed, a second semiconductor chip having one surface on which a 2-1-th electrode is formed and the other surface on which a 2-2-th electrode is formed, a first metal plate contacting the 1-1-th electrode of the first semiconductor chip and the 2-1-th electrode of the second semiconductor chip, a second metal plate contacting the 1-2-th electrode of the first semiconductor chip and spaced apart from the first metal plate, a third metal plate contacting the 1-3-th electrode of the first semiconductor chip and the 2-2-th electrode of the second semiconductor chip, and a sealing member formed to surround the first metal plate, the second metal plate, and the third metal plate. | 05-01-2014 |
20140117524 | POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - There are provided a power semiconductor module and a manufacturing method thereof, the power semiconductor module including: a lead frame; a base substrate including a circuit wiring formed on an insulating layer thereof; a plurality of power semiconductor devices disposed to contact the circuit wiring; and a multilayer substrate formed by stacking a plurality of substrates and electrically connecting the power semiconductor devices and the lead frame to one another using a connection line formed therein and having conductivity. | 05-01-2014 |
20140118956 | ALL-IN-ONE POWER SEMICONDUCTOR MODULE - Disclosed herein is an all-in-one power semiconductor module including a plurality of first semiconductor devices formed on a substrate; a housing molded and formed to include bridges formed across upper portions of the plurality of first semiconductor devices; and a plurality of lead members integrally formed with the housing and electrically connecting the plurality of first semiconductor devices and the substrate. | 05-01-2014 |
20140118961 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a base substrate; a post having one end and the other end, the one end being formed on the base substrate; and a case formed on the base substrate such that it covers a lateral surface and an upper surface of the base substrate, and spaced apart from the upper surface of the base substrate. | 05-01-2014 |
20140119070 | POWER FACTOR CORRECTION CIRCUIT AND METHOD FOR CONTROLLING POWER FACTOR CORRECTION - Disclosed herein is a power factor correction circuit, including: a boost converter circuit in which a plurality of boost circuits including a boost inductor, a rectifying diode, and a boost switch are connected with each other; and a snubber circuit including a snubber inductor and a snubber switch so as to snubber the boost converter circuit. The snubber inductor is controlled so as to be turned on before the boost inductor is turned on to apply zero voltage to the boost inductor. It is possible to reduce switching loss occurring when the boost switch is turned on and increase efficiency of an AC-DC power supply apparatus. | 05-01-2014 |
20140119079 | POWER FACTOR CORRECTION CIRCUIT AND POWER SUPPLY DEVICE INCLUDING THE SAME - There are provided an interleaved power factor correction circuit and a power supply device including the same, the power factor correction circuit including: a main switching unit including a first main switch and a second main switch; an auxiliary switching unit including a first auxiliary switch and a second auxiliary switch; an inductor unit positioned between an input power terminal to which the input power is applied and the main switching unit and storing or discharging power according to the switching operations of the main switching unit; and an auxiliary inductor adjusting an amount of current flowing in the auxiliary switching unit when the auxiliary switching unit performs switching operations. | 05-01-2014 |
20140152271 | POWER FACTOR CORRECTION APPARATUS AND METHOD FOR CORRECTING POWER FACTOR USING THE SAME - There are provided a power factor correction device and a method for controlling power factor correction using the same. The power factor correction device includes a power factor correction circuit and a control circuit. The power factor correction circuit includes first and second inductors connected to an input power source stage and first and second main switches performing a switching operation on the first and second inductors, respectively. The control circuit may provide control signals to the first and second main switches, respectively, and when phase currents flowing in the respective first and second inductors are unbalanced, the control circuit may change a phase of at least one of the first and second main switches to correct an imbalance of the phases. | 06-05-2014 |
20140153299 | POWER FACTOR CORRECTION DEVICE - There is provided a power factor correction device including: a main switching unit including a first main switch and a second main switch performing a switching operation with predetermined phase differences; an auxiliary switching unit including a first auxiliary switch and a second auxiliary switch forming a transmission path for surplus power existing before the first main switch and the second main switch are turned on, respectively; an inductor unit positioned between a power input unit to which AC power is applied and the main switching unit and accumulating or discharging energy according to a switching operation of the main switching unit; and an auxiliary inductor unit regulating an amount of current flowing in the auxiliary switching unit in the event of a switching operation of the auxiliary switching unit. | 06-05-2014 |
20140153307 | DRIVER DEVICE FOR POWER FACTOR CORRECTION CIRCUIT - There is provided a driver device for a power factor correction circuit including first and second main switches that are switched on and off with a phase difference therebetween, and first and second auxiliary switches that provide conduction paths of surplus voltage in the first and second main switches before the first and second main switches are switched on, the driver device including: an input unit receiving a plurality of input signals; and an output unit outputting a first control signal for the first main switch, a second control signal for the second main switch, a third control signal for the first auxiliary switch, and a fourth control signal for the second auxiliary switch based on a plurality of input signals. | 06-05-2014 |
20140160815 | POWER FACTOR CORRECTION CIRCUIT - There is provided a power factor correction circuit including: a main switching unit including a first main switch and a second main switch performing a switching operation to regulate a phase difference between a current and a voltage of input power, respectively; a main inductor unit including a first main inductor and a second main inductor accumulating or discharging energy according to a switching operation of each of the first main switch and the second main switch; a snubber switching unit including a first snubber switch and a second snubber switch providing zero-voltage turn-on conditions to the first main switch and the second main switch, respectively; and a controller controlling a switching operation of the main switching unit and the snubber switching unit. | 06-12-2014 |
20140160816 | POWER FACTOR CORRECTION CIRCUIT AND POWER SUPPLY INCLUDING THE SAME - There are provided a power factor correction circuit and a power supply including the same, the power factor correction circuit including a main switch adjusting a phase difference between a current and a voltage of input power, a main inductor storing or discharging the power according to switching of the main switch, a snubber circuit unit including a snubber switch forming a transfer path for surplus power present before the main switch is turned on and a snubber inductor adjusting an amount of a current applied to the snubber switch, and a reduction circuit unit reducing excessive power imposed on the snubber switch by varying inductance of the snubber inductor. | 06-12-2014 |
20140167123 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a power semiconductor device including: a body region having a first conductivity; a well formed in an upper portion of the body region and having a second conductivity; and a conductive via formed in the body region while traversing the well. | 06-19-2014 |
20140167239 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a substrate including a metal layer, a first insulation layer formed on the metal layer, a first circuit pattern formed on the first insulation layer and including a first pad and a second pad spaced apart from the first pad, a second insulation layer formed on the first insulation layer to cover the first circuit pattern, and a second circuit pattern formed on the second insulation layer and including a third pad formed on a location corresponding to the first pad and a fourth pad spaced apart from the third pad; a semiconductor chip mounted on the second circuit pattern; one end being electrically connected to the semiconductor chip, and another end protruding from the outside, wherein the first pad and the third pad, and the second pad and the fourth pad have different polarities. | 06-19-2014 |
20140177288 | FLYBACK CONVERTER - There is provided a flyback converter, including: a power supply unit supplying input power; a transformer unit including first and second transformers converting first and second primary current from the power supply unit into first and second secondary current, respectively; a main switch unit including first and second main switches respectively intermitting the first and second primary current flowing in respective primary windings of the first and second transformers; an auxiliary switch unit including first and second auxiliary switches forming respective transfer paths for dump power present before the first and second main switches are switched on; and an auxiliary inductor unit including first and second auxiliary inductors respectively adjusting the amount of current flowing in the first and second auxiliary switches during the switching operation thereof, wherein the first and second main switches perform a switching operation while having a predetermined phase difference therebetween. | 06-26-2014 |
20140183717 | SEMICONDUCTOR MODULE PACKAGE - Disclosed herein is a semiconductor module package, including: a first module including a first heat radiation substrate and one or more first semiconductor elements and having a first N terminal and a first P terminal formed at one end thereof; a second module including a second heat radiation substrate and one or more second semiconductor elements, having a second N terminal and a second P terminal formed at one end thereof, and disposed so as to face the first module; and a first output terminal formed by electrically connecting the first module to the second module. | 07-03-2014 |
20140184175 | DRIVING APPARATUS FOR DRIVING POWER FACTOR CORRECTION CIRCUIT - There is provided a driving apparatus for driving an interleaved power factor correction circuit including a first main switch and a second main switch performing a switching operation with a predetermined phase difference and a first auxiliary switch and a second auxiliary switch forming a transformation path for surplus power existing before an ON operation of the first main switch and a second main switch, respectively, including: an input unit obtaining an input signal; a current sensing unit obtaining information regarding a current of the interleaved power factor correction circuit; and an output unit outputting a first control signal with respect to the first main switch, a third control signal with respect to the second main switch, a second control signal with respect to the first auxiliary switch, and a fourth control signal with respect to the second auxiliary switch, based on the input signal and the current information. | 07-03-2014 |
20140185242 | POWER SEMICONDUCTOR MODULE - There is provided a power semiconductor module in which power semiconductor elements, integration of which may be difficult due to heating, are modularized. The power semiconductor module includes: a heat dissipation substrate electrically connected to a common connection terminal; and a plurality of electronic elements disposed on the heat dissipation substrate, wherein the electronic elements have varying spaces therebetween. | 07-03-2014 |
20140285972 | HOUSING AND POWER MODULE HAVING THE SAME - There are provided a housing capable of evenly distributing stress generated at the time of assembly thereof and a power module having the same. The housing for a power module according to an embodiment of the invention includes: a body part having a space formed therein, the space receiving a module substrate having electronic devices mounted thereon; a plurality of fastening parts protruded from sides of the body part; and a fastening member having a leaf spring form and having both ends coupled to two of the fastening parts, respectively, wherein the fastening member includes: a coupling portion coupled to a fixing member; and elastic portions extending from both edges of the coupling portion to be coupled to the fastening parts and elastically deformed when the coupling portion is fastened to a heat radiating substrate to provide elastic force to the fastening parts. | 09-25-2014 |
20140286066 | GATE DRIVING DEVICE AND INVERTER HAVING THE SAME - There is provided a gate driving device, including: an inverter arm including a high-side switch and a low-side switch; a gate driving unit receiving an instruction signal to provide switching control to the inverter arm, outputting a control signal to control switching of the inverter arm, and including a plurality of gate drivers; and a balancing unit causing voltage applied to the plurality of gate drivers to be divided to be supplied to respective gate drivers among the plurality of gate drivers, according to the switching of the inverter arm based on the control signal. | 09-25-2014 |
Patent application number | Description | Published |
20120241793 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes: a substrate, a light-emitting layer disposed on a surface of the substrate and including a first type semiconductor layer, an active layer, and a second type semiconductor layer, a first bump disposed on the first type semiconductor layer and a second bump disposed the second type semiconductor layer, a protective layer covering at least the light-emitting layer, and a first bump pad and a second bump pad disposed on the protective layer and connected to the first bump and the second bump, respectively. | 09-27-2012 |
20130026518 | WAFER LEVEL LED PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are a wafer level LED package and a method of fabricating the same. The method of fabricating a wafer level LED package includes: forming a plurality of semiconductor stacks on a first substrate, each of the semiconductor stacks comprising a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active region disposed between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer; preparing a second substrate comprising first lead electrodes and second lead electrodes arranged corresponding to the plurality of semiconductor stacks; bonding the plurality of semiconductor stacks to the second substrate; and cutting the first substrate and the second substrate into a plurality of packages after the bonding is completed. Accordingly, the wafer level LED package is provided. | 01-31-2013 |
20130221372 | LIGHT EMITTING DIODE ASSEMBLY AND METHOD FOR FABRICATING THE SAME - The present invention is directed to a light emitting diode (LED) assembly and a method for fabricating the same. According to the present invention, there is provided an LED assembly comprising an LED comprising at least an N-type semiconductor layer and a P-type semiconductor layer; and bumps provided on the LED and electrically connected to the semiconductor layers, wherein the bump comprises a first region made of a gold (Au) compound including tin (Sn) and a second region made of gold. | 08-29-2013 |
20140284650 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING SAME - Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity. | 09-25-2014 |
20150044101 | Air Purifying Apparatus Having Shuntable Air Duct - An air purifying apparatus according to an embodiment includes a body having first and second conduits through which a flow of air is generated from an air inlet to an air outlet, an ultraviolet light emitting diode part and a first filter part disposed within the first conduit, and a second filter part disposed within the second conduit. | 02-12-2015 |
20150064064 | MOBILE DISINFECTOR USING UV LED - A mobile disinfector using UV LEDs can include: a case forming an exterior structure of the disinfector; a cover including two parts coupled to respective sides of the case and including openings formed on the cover; and LED units exposed to outside through the openings formed on the cover. Since the cover is coupled to the case such that an angle between the cover and the case is adjusted, an irradiation angle of light emitted to the outside from the LED units is controlled. | 03-05-2015 |
Patent application number | Description | Published |
20110219207 | RECONFIGURABLE PROCESSOR AND RECONFIGURABLE PROCESSING METHOD - A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane. | 09-08-2011 |
20120124117 | FUSED MULTIPLY-ADD APPARATUS AND METHOD - A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero. | 05-17-2012 |
20130151815 | RECONFIGURABLE PROCESSOR AND MINI-CORE OF RECONFIGURABLE PROCESSOR - A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected. | 06-13-2013 |
20130246856 | VERIFICATION SUPPORTING APPARATUS AND VERIFICATION SUPPORTING METHOD OF RECONFIGURABLE PROCESSOR - A verification supporting apparatus and a verification supporting method of a reconfigurable processor is provided. The verification supporting apparatus includes an invalid operation determiner configured to detect an invalid operation from a result of scheduling on a source code, and a masking hint generator configured to generate a masking hint for the detected invalid operation. | 09-19-2013 |
20130318324 | MINICORE-BASED RECONFIGURABLE PROCESSOR AND METHOD OF FLEXIBLY PROCESSING MULTIPLE DATA USING THE SAME - A minicore-based reconfigurable processor and a method of flexibly processing multiple data using the same are provided. The reconfigurable processor includes minicores, each of the minicores including function units configured to perform different operations, respectively. The reconfigurable processor further includes a processing unit configured to activate two or more function units of two or more respective minicores, among the minicores, that are configured to perform an operation of a single instruction multiple data (SIMD) instruction, the processing unit further configured to execute the SIMD instruction using the activated two or more function units. | 11-28-2013 |
20140331031 | RECONFIGURABLE PROCESSOR HAVING CONSTANT STORAGE REGISTER - A reconfigurable processor configured to include a constant storage register to store a constant is provided, thereby improving efficiency in the use of a memory space. Specifically, a reconfigurable processor includes a plurality of Functional Units (FUs), a configuration memory configured to store configuration information, and a constant storage register configured to store a constant that is used as an operand for an operation in the plurality of FUs. | 11-06-2014 |
Patent application number | Description | Published |
20110156830 | Microelectromechanical system device and method of manufacturing the microelectromechanical system device - Provided is a microelectromechanical system (MEMS) that includes a first structure and second structure. The first structure and second structure may each include a first substrate and a second substrate. The first substrate of each structure may have first and second surfaces that face each other. The first substrate may include a via etching hole pattern penetrating the first surface and the second surface and a first non-via etching hole pattern penetrating the first surface. The second substrate of each structure may have third and fourth surfaces that face each other. The second substrate may include a second non-via etching hole pattern penetrating the third surface in a position corresponding to the via etching hole pattern of the first substrate. In the microelectromechanical system (MEMS) the second surface of the first substrate and the third surface of the second substrate may be bonded together. | 06-30-2011 |
20130070459 | OPTICAL DEVICES AND METHODS OF CONTROLLING PROPAGATION DIRECTIONS OF LIGHT FROM THE OPTICAL DEVICES - An optical device may include a substrate, a metal layer on the substrate, at least one first nano-structure in the layer, and at least one second nano-structure in the layer. The at least one first nano-structure may include a light source. The at least one first and second nano-structures may be spaced apart. A method of controlling a propagation direction of light output from an optical device that includes a metal layer on a substrate may include disposing first and second nano-structures in the layer; disposing at least one light source in the first nano-structure; and controlling the propagation direction of the light output from the at least one light source by changing at least one of a shape of the first nano-structure, a shape of the second nano-structure, a size of the first nano-structure, a size of the second nano-structure, and an interval between the first and second nano-structures. | 03-21-2013 |
20130193804 | SLIP-STICK PIEZOELECTRIC ACTUATOR - A piezoelectric actuator includes a fixed body, a movable body arranged to face the fixed body, and a plurality of piezoelectric elements arranged between the fixed body and the movable body and operating in a shearing mode. Each piezoelectric element having one end fixed to the fixed body and another end contacting the movable body, wherein a direction of polarization of each of the plurality of piezoelectric elements is different from each other. | 08-01-2013 |
20140182020 | VERTICALLY MOUNTED SAMPLE STAGE FOR MICROSCOPY AND SCANNING PROBE MICROSCOPE USING THE SAMPLE STAGE - A sample stage for microscopy includes a sample holder including a body in which a sample-mounting part and a seating part are provided on a bottom of the body and a grip part for a mounting unit is provided on a top of the body, a sample rack, on which the sample holder is mounted, including a supporter supporting the seating part of the sample holder, and an elastic element provided on the sample rack, providing the sample holder with a pressing force inclined with respect to a vertical direction and fastening the sample holder to the sample rack while the seating part is being supported by the supporter. The sample stage may be vertically mounted. | 06-26-2014 |
20140287601 | MAGNETIC CONNECTION DEVICE - A magnetic connection device including a first connector including a first housing and a plurality of first electrodes mounted on the first housing in a state of being partially exposed and having magnetic substances; and a second connector including a second housing, a plurality of second electrodes mounted on the second housing and having magnetic substances, and elastic members for elastically supporting the plurality of second electrodes, wherein an end portion of each of the plurality of second electrodes is located in the second housing due to an elasticity of the elastic members in a state where a magnetic attraction is not applied from the plurality of first electrodes, and protrudes out of the second housing to be electrically connected to each of the plurality of first electrodes when there is the magnetic attraction applied from the plurality of first electrodes. | 09-25-2014 |
20140320547 | IMAGE DISPLAY DEVICE AND METHOD AND APPARATUS FOR IMPLEMENTING AUGMENTED REALITY USING UNIDIRECTIONAL BEAM - An image display device includes a display panel unit having a plurality of optical elements configured to generate and emit unidirectional lights in an array and a control unit configured to control the plurality of optical elements according to image information. The image display device is located very close to the eyes of a user and displays an additional information image added to a real image, thereby implementing augmented reality. | 10-30-2014 |
Patent application number | Description | Published |
20130292011 | High-Strength Steel Sheet Having Superior Toughness at Cryogenic Temperatures, and Method for Manufacturing Same - According to one aspect, provided is a high-strength steel sheet having superior toughness at cryogenic temperature, comprising, in weight percentage, 0.02 to 0.06% of C, 0.1 to 0.35% of Si, 1.0 to 1.6% of Mn, 0.02% or less (but not 0%) of Al, 0.7 to 2.0% of Ni, 0.4 to 0.9% of Cu, 0.003 to 0.015% of Ti, 0.003 to 0.02% of Nb, 0.01% or less of P, 0.005% or less of S, the remainder being Fe and unavoidable impurities, wherein the high-strength steel sheet satisfies the condition of [Mn]+5.4[Si]+26[Al]+32.8[Nb]<4.3 where [Mn], [Si], [Al], and [Nb] indicate contents of Mn, Si, Al, and Nb in weight percentage, respectively. The steel sheet secures toughness when used as structural steel materials for ships, offshore structures, or the like, or steel materials for tanks for storing and carrying liquefied gases, which are exposed to an extreme low temperature environment. | 11-07-2013 |
20140261918 | ENHANCED WEAR RESISTANT STEEL AND METHODS OF MAKING THE SAME - Improved steel compositions and methods of making the same are provided. The present disclosure provides advantageous wear resistant steel. More particularly, the present disclosure provides high manganese (Mn) steel having enhanced wear resistance, and methods for fabricating high manganese steel compositions having enhanced wear resistance. The advantageous steel compositions/components of the present disclosure improve one or more of the following properties: wear resistance, ductility, crack resistance, erosion resistance, fatigue life, surface hardness, stress corrosion resistance, fatigue resistance, and/or environmental cracking resistance. In general, the present disclosure provides high manganese steels tailored to resist wear and/or erosion. | 09-18-2014 |
20150020928 | AUSTENITIC STEEL HAVING EXCELLENT MACHINABILITY AND ULTRA-LOW TEMPERATURE TOUGHNESS IN WELD HEAT-AFFECTED ZONE, AND METHOD OF MANUFACTURING THE SAME - Provided are an austenitic steel having excellent machinability and ultra-low temperature toughness in a weld heat-affected zone including 15 wt % to 35 wt % of manganese (Mn), carbon (C) satisfying 23.6C+Mn≧28 and 33.5C−Mn≦23, 5 wt % or less (excluding 0 wt %) of copper (Cu), chromium (Cr) satisfying 28.5C+4.4Cr≦57 (excluding 0 wt %), and iron (Fe) as well as other unavoidable impurities as a remainder, wherein a Charpy impact value of a weld heat-affected zone at −196° C. is 41 J or more, and a method of manufacturing the steel. | 01-22-2015 |
Patent application number | Description | Published |
20120200666 | BROADCAST RECEIVER AND 3D VIDEO DATA PROCESSING METHOD THEREOF - Abstract: A broadcast receiver and a 3D video data processing method are disclosed. The method includes receiving a broadcast signal including system information and video data, parsing system information of a program, and determining whether the program provides a 3D broadcast service from the system information, extracting, if the program provides a 3D broadcast service, broadcast data of the program, and processing video data of broadcast data according to the system information. The broadcast receiver includes a receiving unit receiving a broadcast signal including system information and video data, an SI processor parsing system information of a program, and determining whether the program provides a 3D broadcast service from the system information, a demultiplexer extracting, if the program provides a 3D broadcast service, broadcast data of the program, and a video processor processing video data of the broadcast data according to system information. | 08-09-2012 |
20120320155 | BROADCASTING RECEIVER AND METHOD FOR DISPLAYING 3D IMAGES - Disclosed are a method for displaying 3D images and a broadcast receiver. The method for displaying 3D images according to one embodiment of the present invention comprises the steps of: receiving broadcasting signals including video data and 3D object data; decoding the 3D object data, the 3D object data including texts or image information for a 3D object, output position information of the 3D object, and disparity information of the 3D object; obtaining parallax values from the disparity information and producing distortion compensation coefficients using the parallax values; adjusting a display size of the 3D object using the distortion compensation coefficients; and outputting and displaying the 3D object. | 12-20-2012 |
20130014202 | METHOD OF PROCESSING NON-REAL TIME SERVICE AND BROADCAST RECEIVER - A method of processing a non-real time (NRT) service in a broadcast receiver is disclosed where the method includes receiving signaling information including the NRT service information and access information which indicates files of a content item can be accessed by Internet, receiving File Delivery over Unidirectional Transport (FLUTE) files through a FLUTE session, wherein File Delivery Table (FDT) instance of the FLUTE session for each file belonging to the content item includes information for content location of the file, the information for content location including an Uniform Resource Locator (URL), and providing the NRT service using the files belonging to the content item, wherein the files are accessed through the Internet using the URL indicated in the information for content location of the file or accessed through a storage in the broadcast receiver. | 01-10-2013 |
20130024900 | METHOD AND APPARATUS FOR PROCESSING NON-REAL-TIME BROADCAST SERVICE AND CONTENT TRANSMITTED BY BROADCAST SIGNAL - The present invention relates to a method and an apparatus for delivering an NRT service or NRT content through a broadcast signal. According to one embodiment of the present invention, the method for processing the NRT broadcast service comprises the steps of: receiving a broadcast signal including an IP multicast stream transmitted through a particular Internet protocol (IP) address; parsing a service map table (SMT) for signaling a non-real-time (NRT) service from the IP multicast stream included in the received broadcast signal; parsing a language information descriptor indicative of language information of an element associated with the NRT service at the parsed service map table; parsing, in the parsed language information descriptor, a language type field indicative of the type of language used in the NRT service and an element type field indicative of the type of element associated with the NRT service; and identifying that the language indicated by the language type field is used in the element associated with the NRT service indicated by the parsed element type field, wherein said element type field identifies one of elements which are associated with the NRT service and include a caption element of the NRT service and a text element of the NRT service. | 01-24-2013 |
20130088571 | DIGITAL RECEIVER AND METHOD FOR PROCESSING CAPTION DATA IN THE DIGITAL RECEIVER - The present description provides a digital receiver which provides 3D caption data and a method for processing 3D caption data in the digital receiver of the present invention. A method for transmitting a broadcast signal for 3D service according to one aspect of the present invention comprises the following steps: encoding 3D video ES including a 3D caption service; generating signaling information for signaling a 3D video service including the encoded 3D video ES; and transmitting a digital broadcast signal including the 3D video service and the signaling information, wherein said 3D caption service includes a first command code for generating left caption data and a second command code for indicating a disparity value for a caption window, and generates right caption data on the basis of the first command code and second command code. | 04-11-2013 |
Patent application number | Description | Published |
20120147514 | CERAMIC PASTE COMPOSITION FOR MULTILAYER CERAMIC CAPACITOR, MULTILAYER CERAMIC CAPACITOR COMPRISING THE SAME, AND METHODS OF MANUFACTURING THE SAME - There are provided a ceramic paste composition for a multilayer ceramic capacitor (MLCC), a multilayer ceramic capacitor comprising the same, and methods of manufacturing the same. The ceramic paste composition for the MLCC includes: a ceramic powder, a first phosphate ester-based dispersant and a second dispersant salt-bonded by a fatty acid and an alkyl amine; a binder including polyvinyl butyral and ethyl cellulose; and a solvent. The ceramic paste composition ceramic powder has a small average particle-diameter and the ceramic powder in the paste has excellent dispersibility. | 06-14-2012 |
20120162855 | CONDUCTIVE PASTE COMPOSITION FOR INTERNAL ELECTRODE, MULTILAYER CERAMIC CAPACITOR COMPRISING THE SAME AND METHOD OF MANUFACTURING THEREOF - There are provided a conductive paste composition for an internal electrode, and a multilayer ceramic capacitor comprising the same and a manufacturing method thereof. The conductive paste composition includes a metal powder, a dispersant made of an acrylic polymer having a weight average molecular weight of 500 to 5,000, and at least one organic binder selected from a group consisting of a polyvinylbutyral resin and a cellulose resin. The conductive paste composition for an internal electrode has superior dispersibility of the metal powder in the paste. | 06-28-2012 |
20120307414 | MULTILAYER CERAMIC CAPACITOR - There is provided a multilayer ceramic capacitor, including: a multilayer body having a plurality of dielectric layers and a plurality of internal electrode layers alternately laminated; wherein each internal electrode layer has a width gradually decreases from a center thereof towards both ends thereof in a length direction; and when a width of each internal electrode layer at the ends thereof in the length direction is defined as a minimum width L | 12-06-2012 |
20120307417 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component including: a lamination main body including a dielectric layer; and a plurality of inner electrode layers formed within the lamination main body and having ends exposed from one or more faces of the laminated main body, wherein when a distance between central portions of adjacent inner electrodes among the plurality of inner electrodes is T | 12-06-2012 |
20130027842 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer having an average thickness of 0.6 μm or less; and first and second inner electrode layers within the ceramic body, disposed to face each other with the dielectric layer interposed therebetween, wherein the dielectric layer includes contact dielectric grains in contact with the first or second inner electrode layer and non-contact dielectric grains not in contact with the first or second inner electrode layer, and, when an average thickness of the dielectric layer is defined as td and an average diameter of the contact dielectric grains is defined as De, De/td≦0.35 is satisfied. The multilayer ceramic electronic component has improved continuity of the inner electrode layer, large capacitance, extended accelerated lifespan and excellent reliability. | 01-31-2013 |
20130070386 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component including a lamination main body including a plurality of inner electrodes. When T | 03-21-2013 |
20130100578 | MULTILAYER CERAMIC ELECTRONIC PART - There is provided a multilayer ceramic electronic part, including: a ceramic body having a plurality of dielectric layers laminated therein; a plurality of inner electrode layers formed on at least one surface of each dielectric layer; and margin dielectric layers formed on a margin part of each dielectric layer, on which the inner electrode layers are not formed, and having a dielectric grain size smaller than that of the dielectric layers. | 04-25-2013 |
20130114182 | MULTILAYER CERAMIC CAPACITOR - There is provided a multilayer ceramic capacitor, including: a ceramic element having a plurality of dielectric layers stacked therein; a plurality of inner electrode layers formed on each dielectric layer; margin dielectric layers each formed on a margin part of each dielectric layer, on which the inner electrode layers are not formed, the margin dielectric layers having a porosity of 10% or less; and outer electrodes formed on outer surfaces of the ceramic element. | 05-09-2013 |
20130242459 | MULTILAYER CERAMIC ELECTRONIC COMPONENT - There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer having an average thickness of 0.6 μm or less; and first and second inner electrode layers within the ceramic body, disposed to face each other with the dielectric layer interposed therebetween, wherein the dielectric layer includes contact dielectric grains in contact with the first or second inner electrode layer and non-contact dielectric grains not in contact with the first or second inner electrode layer, and, when an average thickness of the dielectric layer is defined as td and an average diameter of the contact dielectric grains is defined as De, De/td≦0.35 is satisfied. The multilayer ceramic electronic component has improved continuity of the inner electrode layer, large capacitance, extended accelerated lifespan and excellent reliability. | 09-19-2013 |
Patent application number | Description | Published |
20130148644 | System and Method for Preambles in a Wireless Communications Network - A method for transmitting a frame includes generating an omni portion of the frame, the omni portion including a non-beamformed long training field and a signal field, the non-beamformed long training field including channel estimation information used to decode the signal field, the non-beamformed long training field configured to be transmitted through one of multiple antennas and multiple streams. The method also includes generating a multi-stream portion of the frame, the multi-stream portion including a data field and a multi-stream long training field, the multi-stream long training field including station-specific decoding information for station-specific data in the data field. The method further includes applying a beamforming indicator to the signal field of the omni portion, and transmitting the frame. | 06-13-2013 |
20130177002 | Systems and Methods for AP Discovery with FILS Beacon - A method and apparatus are disclosed for supporting access point (AP) discovery by a handset/station (STA) using a fast initial link setup (FILS) discovery frame. An embodiment method includes transmitting a plurality of FILS discovery frames at faster time intervals than designated for transmitting standard AP beacons, wherein the FILS discovery frames have a smaller size than standard AP beacons. An embodiment apparatus includes a processor and a computer readable storage medium storing programming for execution by the processor, the programming including instructions to broadcast a standard AP beacon for advertising a basic service set (BSS) repeatedly at subsequent time intervals, and broadcast a FILS discovery frame for advertising the BSS repeatedly at faster subsequent time intervals than for the standard AP beacon, wherein the FILS discovery frame has a smaller size than the standard AP beacon. | 07-11-2013 |
20130195167 | System and Method for Non-Interleaved Signal Field - Efficient decoding in IEEE 802.11ah networks can be achieved by transmitting the signal (SIG) preamble field without interleaving bits within the SIG field. This may allow channel equalization and decoding steps to be performed contemporaneously upon reception of the frame, which allows for the implementation of non-linear channel equalization techniques (e.g., maximum likelihood (ML) equalization, etc. | 08-01-2013 |
20130216002 | Dual-Stream Signal (SIG) Field Encoding with Higher Order Modulation - Signal (SIF) field capacity can be significantly increased by encoding SIG field data using two streams in accordance with a space-time block code (STBC) encoding scheme. Dual-stream SIG field encoding allows for the utilization of higher order modulation schemes, such as quadrature phase-shift keying (QPSK), which increases SIG field capacity. Dual-stream encoded SIG fields are transmitted using an omnidirectional beam to allow mobile stations to accurately decode the SIG field irrespective of their spatial location. | 08-22-2013 |
20130235859 | 802.11 PHY HASHED SSID - An access point (AP) hashes its SSID/BSSID according to a hashing function H and transmits wirelessly the hashed SSID/BSSID within a physical layer frame/packet to a user station (STA). The hashed SSID/BSSID uniquely identifies the AP. In one embodiment, the hashed SSID/BSSID is transmitted within a SIGNAL field of a preamble with the frame/packet. Upon receipt, the user station recovers the hashed SSID/BSSID and compares it to an expected hashed SSID/BSSID (calculated using the same hashing function H and a desired SSID/BSSID). In response to the comparison, the user station performs one or more actions. | 09-12-2013 |
20130308447 | Systems and Methods to Provision Quality of Service Sensitive Devices in Wireless Local Area Networks - System and method embodiments are provided for provisioning a quality of cellular user experience (QoE) or quality of service (QoS) specified device in a wireless local area network (LAN). The embodiments enable a QoE or QoS specified by a service agreement for a device to be maintained during periods when the device is transmitting data to and receiving data from the wireless LAN (e.g., a WiFi hotspot). In an embodiment, a method includes determining that at least one QoS-sensitive device is communicating with a wireless LAN access point (AP), reserving a contention free period (CFP) in a superframe for the at least one QoS-sensitive device to communicate with the AP, and allocating a contention period (CP) in the superframe for non-QoS-sensitive devices to communicate with the AP, wherein the non-QoS-sensitive devices are prohibited from transmitting during the CFP. | 11-21-2013 |
20140056204 | Systems and Methods for Interference Alignment in Wi-Fi - System and method embodiments are provided for interference alignment in a wireless local area network (LAN) with an overlapping basic service set (OBSS). In an embodiment, a method includes instructing a first access point (AP) in the wireless LAN to broadcast a null data packet (NDP) sounding packet to a plurality of stations when no other AP is broadcasting, wherein the NDP sounding packet comprises a plurality of long training field (LTFs), and wherein a total number of LTFs is equal to a total number of transmission streams, receiving channel beamforming (BF) information and a signal plus interference to noise ratio (SINR) from each of the stations, wherein each of the stations computes the channel BF information and the SINR from sounding packets received from each of the APs in the wireless LAN, and determining a transmission schedule according to the SINRs and the channel BF information. | 02-27-2014 |
20140056205 | System and Method for a Collaborative Service Set - In one embodiment, a collaborative service set (CSS) includes a controller access point (AP) configured to be associated with a first plurality of stations and a first member AP, where the first member AP is associated with a second plurality of stations, where the controller AP is configured to coordinate transmissions between the first member AP and the second plurality of stations with transmissions between the controller AP and the first plurality of stations, where the controller AP and the first member AP are configured to transmit messages simultaneously. | 02-27-2014 |
20140112273 | System and Method for Carrier Aggregation for Wireless Local Area Networks - Embodiments are provided herein for improving carrier aggregation for wireless networks. A plurality of bandwidth channels are assigned to a basic service set (BSS) for transmissions. Specifically, the bandwidth channels are divided into multiple channel segments corresponding to multiple primary or alternate primary channels. A channel segment possibly further includes one or more additional secondary channels. The locations of the primary or alternate primary channels that correspond to the channel segments of the BSS are then broadcasted in the network. When a station or AP receives this BSS information, it searches for an available primary or alternate primary channel of the BSS to begin transmission. Upon detecting an available primary channel or alternate primary channel that is not used for another transmission, the station or AP transmits data on the channel segment corresponding to the detected primary or alternate primary channel. | 04-24-2014 |
20140119300 | System and Method for User Cooperation Protocol for Interference Alignment in Wireless Networks - Embodiments are provided herein for implementing a user cooperation protocol for interference alignment (IA) in wireless local area network (WLAN) or a Wi-Fi hotspot. The embodiments allow collecting knowledge of the channels from user stations (STAs) and sending this information to the corresponding access points (APs) in the network. This information is then used by the APs to pre-code their signals such as to remove interfering signals to non-intended STAs. An AP transmits to the STAs a group identifier (GrpID) indicating an order of STAs for transmitting channel state information (CSI) and an AP index indicating an order of STA groups of the APs for transmitting the CSI. When a STA detects a CSI transmission from another STA preceding the STA in the order of transmission as indicated by the AP index and GrpID, the STA transmits its CSI. | 05-01-2014 |
20140169339 | Systems and Methods to Achieve Fairness in Wireless LANs for Cellular Offloading - System and method embodiments are included to provide various degrees of time allocation fairness to users using varying target transmission opportunity (TXOP) values. In one embodiment, a method for promoting various degrees of fairness for users in a wireless network includes assigning a target TXOP value for one or more users in the wireless network, wherein the target TXOP value indicates a number of time units for transmissions to be met on average over time by the one or more users, and transmitting the target TXOP value to the one or more users. In another embodiment, a method includes receiving a TXOP value from the wireless network, wherein the target TXOP value indicates a number of time units allocated for transmissions, and transmitting traffic over a plurality of time periods that have an average duration about equal to the number of time units. | 06-19-2014 |
20140204746 | OpenFlow Enabled WiFi Management Entity Architecture - System and method embodiments are provided to improve offloading traffic from mobile operators networks via a WiFi network. The embodiments also include schemes to offload traffic between WiFi networks. The embodiments include a network component comprising a WiFi management entity (WiME) configured to serve as an anchor point for a user device at a WiFi network and communicate with a management entity at a wireless network using OpenFlow protocol to handle a plurality of control and mobility functionalities for traffic in the WiFi network, wherein the control and mobility functionalities include offloading traffic for the user device from the wireless network to the WiFi network. | 07-24-2014 |
20140328242 | System and Method for Wi-Fi Downlink-Uplink Protocol Design for Uplink Interference Alignment - Embodiments are provided to enable concurrent uplink transmissions from multiple Wi-Fi stations (STAs) to one or more access points (APs) using Interference Alignment (IA). In an embodiment, the STAs broadcast, to one or more APs, beamforming reports including channel estimation information for downlink. The one or more AP then performs channel estimation using the beamforming reports, and selects at least some of the STAs. The AP also computes beamforming information for IA of uplink transmissions between the selected STAs and sends, to the selected STAs, the beamforming information. The beamforming information is piggy-backed over downlink data packets to the selected STAs. Each selected STA then sends an uplink data frame concurrently with one or more other uplink data frames from one or more other selected STAs to the AP. The uplink data frames are configured for concurrent uplink transmissions according to the beamforming information for IA. | 11-06-2014 |
20140341129 | Systems and Methods for Operation of Wireless User Devices with Cellular and Wi-Fi Interfaces - An embodiment method for wireless communication includes grouping a plurality of user equipments (UEs) wirelessly coupled to a cellular base station (BS) into a UE cluster to function as a Wi-Fi virtual station (V-STA), and communicating with an access point (AP) to contend for a Wi-Fi transmission opportunity (TXOP) for the V-STA. In a further embodiment, the cellular BS contends for the TXOP on behalf of the UE cluster using a carrier sense multiple access with collision avoidance (CSMA-CA) procedure. In an alternative embodiment, one UE in the UE cluster is selected as a leader UE to contend for the TXOP on behalf of the UE cluster using a CSMA-CA procedure. | 11-20-2014 |
20140376532 | System and Method for a CSMA-CA Half Window Scheme - Embodiments are provided for implementing a CSMA-CA half window scheme in 802.11 networks or other suitable wireless networks that could benefit from such scheme. The half window scheme improves a back-off time calculation by adding a probability prediction factor. The back-off time is part of a delay time in accessing a wireless transmission medium by a station (STA). The probability prediction factor is used to adjust a contention widow (CW) used to calculate the back-off time, based on the STA's medium access probability. The STA splits the CW into two at least half windows and then chooses one of the windows according to the window's information gain for the probability prediction. The selected window is used to select a random number for the back-off time. The improved back-off time calculation reduces contention between STAs in accessing the medium. | 12-25-2014 |
20150023440 | Systems and Methods for Trellis Coded Quantization Based Channel Feedback - System and method embodiments are provided for Trellis Coded Quantization (TCQ) based channel feedback. The embodiments provide full channel state information with a short feedback size to a scheduler in order for the scheduler to apply advanced beamforming schemes, such as those designed in non-linear precoder methods. In an embodiment, a method in a station for providing channel feedback to a transmission point (TP) in a wireless system includes receiving a signal from the TP; estimating channel parameters for the signal; applying a TCQ scheme to the estimated channel parameters to map the channel estimate parameters to trellis codes; and transmitting full channel state information to the TP, wherein the full channel state information comprises output of a Viterbi algorithm (VA) corresponding to the trellis codes. | 01-22-2015 |
Patent application number | Description | Published |
20120101356 | Optical Stimulus Probe with Reflecting Surface - An optical stimulation probe has a probe body inserted into a subject, an electrode formed on the probe body and collecting a response signal from the subject, a light irradiator attached to the probe body and irradiating an optical signal and a reflecting surface formed on the probe body on the path of the optical signal. The reflecting surface changes the course of the optical signal irradiated from the light irradiator to the direction where the electrode faces by reflecting the optical signal. The electrode may be formed on a side portion of the probe body such that it faces a direction perpendicular to a length direction of the probe body, and the optical signal reflected by the reflecting surface may travel along a direction perpendicular to the length direction of the probe body, such that the direction where the electrode faces and the direction along which the reflected optical signal travels are parallel to each other. | 04-26-2012 |
20120253423 | Artificial Nerve Networking System and Method for Functional Recovery of Damaged Nerve - Disclosed are a system and a method for artificial nerve networking capable of restoring a damaged nerve and allowing selective detection, analysis, transmission and stimulation of a signal from the damaged nerve. The artificial nerve networking system according to an embodiment of the present disclosure includes: a first nerve conduit connected at one end of a damaged nerve; a second nerve conduit connected at the other end of the damaged nerve; and an artificial nerve networking unit electrically connected to the first nerve conduit and the second nerve conduit and recovering the function of the damaged nerve by transmitting and receiving a signal to and from the damaged nerve. | 10-04-2012 |
20130140611 | PRESSURE SENSOR HAVING NANOSTRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a pressure sensor having a nanostructure and a method for manufacturing the same. More particularly, it relates to a pressure sensor having a nanostructure attached on the surface of the pressure sensor and thus having improved sensor response time and sensitivity and a method for manufacturing the same. The pressure sensor according to the present disclosure having a nanostructure includes: a substrate; a source electrode and a drain electrode arranged on the substrate with a predetermined spacing; a flexible sensor layer disposed on the source electrode and the drain electrode; and a nanostructure attached on the surface of the flexible sensor layer and having nanosized wrinkles. | 06-06-2013 |
20130144143 | PROBE STRUCTURE CAPABLE OF MEASURING pH LEVEL - The probe structure capable of measuring a pH level according to an embodiment of the present disclosure includes: a probe unit inserted into an experiment target; a fixing body connected to a terminal of the probe unit and fixing the probe unit; an electrode array disposed at a front end of the probe unit and sensing a neural signal from the experiment target and a pH level; a reference electrode disposed at the front end of the probe unit to be spaced apart from the electrode array by a predetermined interval and sensing a reference signal for pH level measurement; an electric wire electrically connected to the electrode array and the reference electrode; and a measured signal collecting electrode integrated at the fixing body and collecting measured signals transmitted through the electric wire. | 06-06-2013 |
20130253606 | PERIPHERAL NERVE INTERFACE SYSTEM AND METHOD FOR PROSTHETIC HAND CONTROL - The present disclosure relates to peripheral nerve interface system and method for prosthetic hand control, which may measure, analyze and control efferent motor nerve signals and afferent sensory nerve signals by regenerating a peripheral nerve and control an artificial prosthetic hand by means of the measurement, analysis and control of the signals. For this, the peripheral nerve interface system according to an embodiment of the present disclosure includes: a nerve conduit connected to a terminal of a damaged peripheral nerve at a cut body portion; a prosthesis for substituting for the cut body portion; and a peripheral nerve interface unit electrically connected to the nerve conduit and the prosthesis to restore a function of the damaged peripheral nerve and control operations of the prosthesis by transmitting and receiving signals of the damaged peripheral nerve. | 09-26-2013 |
20140140372 | PROBE SENSOR CAPABLE OF MEASUREMENT FOR TEMPERATURE WITH STIMULUS - A probe sensor has a probe structure having a probe body inserted into an experiment subject, a block body disposed on the probe body to transmit or reflect an incident light, and a light irradiation body for inputting a first incident light to the block body; a first light source for generating the first incident light and transmitting to the light irradiation body; and a light analyzer for analyzing a first reflection light which is a reflection light of the first incident light reflected by the block body, wherein the length of the block body changes according to a temperature change, and wherein the light analyzer measures a temperature change of the experiment subject by detecting a wavelength change of the first reflection light according to the length change of the block body. | 05-22-2014 |
20140163348 | NEURAL TUBE FOR RECOVERING FUNCTION OF INJURED NERVE - A neural tube capable of complexly playing roles of a support for regenerating a nerve and a nerve electrode has a support connected to a terminal of an injured nerve, and a sieve electrode having an electrode hole formed in a body thereof and a circular electrode formed around the electrode hole, wherein the body of the sieve electrode is buried in the support, wherein a cavity-type channel is formed at the support to extend to the inside of the support, wherein the electrode hole is aligned with the channel, and wherein a nerve cell growing along the channel at the terminal of the injured nerve is capable of contacting the circular electrode. | 06-12-2014 |
Patent application number | Description | Published |
20120026400 | METHOD FOR PROVIDING A SHORTCUT AND IMAGE DISPLAY DEVICE THEREOF - A multifunctional display device displays a menu including shortcut objects. A processor assigns each object to one of a broadcast channel, network address, or an application. The objects may be an alphabetical character, number, symbol, or icon. | 02-02-2012 |
20130124652 | ELECTRONIC DEVICE AND METHOD FOR PROVIDING CONTENTS RECOMMENDATION SERVICE - An electronic device and a method for providing a content recommendation service are disclosed. A controller detects a user action for requesting content recommendation, extracts content information about content displayed on a screen in response to the detected user action, and generates a content post request message including the extracted content information and ID information. A network interface transmits the generated content post request message to an electronic device or a server. | 05-16-2013 |
20130125172 | ELECTRONIC DEVICE AND METHOD FOR PROVIDING INFORMATION RELATED TO BROADCAST VIEWING - An electronic device and a method for providing view information are disclosed. A controller controls a request for broadcast rank to a relay server. A network interface receives a display page transmitted as a response to the request for broadcast rank. A display displays the received display page. The display page includes at least one feed associated with a real-time broadcast program and one of the at least one feed includes the number of users who view an associated real-time broadcast program. | 05-16-2013 |
20130150158 | METHOD OF PROVIDING GAME APPLICATION AND IMAGE DISPLAY DEVICE USING THE SAME - Disclosed herein are a method of providing a game application through an image display device and a user terminal connected over a network and a game application provision system employing the method. The method of providing the game application includes assigning a play identifier to the user terminal, executing the game application, generating game execution information, and transmitting the game execution information to the user terminal. | 06-13-2013 |
20130268967 | METHOD FOR PROVIDING A SHORTCUT AND IMAGE DISPLAY DEVICE THEREOF - A multifunctional display device displays a menu including shortcut objects. A processor assigns each object to one of a broadcast channel, network address, or an application. The objects may be an alphabetical character, number, symbol, or icon. | 10-10-2013 |
20130326557 | METHOD FOR PROVIDING APPLICATION MENU IN IMAGE DISPLAY DEVICE, AND IMAGE DISPLAY DEVICE USING SAME - The present invention relates to a method for maintaining various application installed in an image display device, and more particularly, to a method for operating an image display device, the method allowing a user to more conveniently select and execute applications in configuring selection menus of the applications, and to an image display device using the method. The method comprises: searching for applications which can be used on an image display device; displaying a first application list including selected menu items of the selected applications; and displaying one or more application key screens from among the applications which are included in the first application list. Accordingly, the user of the image display device can be provided, from the image display device, with application menus, which include menu items for running the applications that can be used on the image display device. | 12-05-2013 |