Patent application number | Description | Published |
20090082833 | TELEMETRY NOISE REDUCTION - A device includes a housing and electronics disposed in the housing. A telemetry antenna is disposed in the housing and is operably coupled to the electronics. A shielding coil is disposed between the housing and the telemetry antenna. The shielding coil has a first end and a second end. The second end is electrically terminated in circuitry of the electronics. | 03-26-2009 |
20100187206 | Terminal Platforms for Batteries in Implantable Medical Devices - A terminal platform comprising a first terminal block securable to a housing of the battery, a second terminal block configured to electrically connect to a terminal wire of the battery, and an insulating support electrically isolating the second terminal block from the first terminal block. | 07-29-2010 |
20110137379 | TELEMETRY NOISE REDUCTION - A device includes a housing and electronics disposed in the housing. A telemetry antenna is disposed in the housing and is operably coupled to the electronics. A shielding coil is disposed between the housing and the telemetry antenna. The shielding coil has a first end and a second end. The second end is electrically terminated in circuitry of the electronics. | 06-09-2011 |
20110257711 | Medical Devices Including Flexible Circuit Bodies with Exposed Portions of Circuit Traces Attached to Electrical Contacts of Components - Medical devices include stimulation and/or sensing circuitry that is interconnected to electrical components by a flexible circuit body having exposed portions of circuit traces that are attached to electrical contacts of the electrical components. Each circuit trace may span a separate window formed in an insulative body of the flexible circuit body, or a plurality of circuit traces may span a single window or may be freely extending from the insulative body. The exposed portion of the circuit trace may be plated with a conductive metal and then attached to the electrical contact of the electrical component. The flexible circuit body may be an extension from a flexible electrical circuit board containing the circuit. The circuit may be present on a circuit board that includes electrical contacts and where the flexible circuit body has exposed portions of circuit traces attached to the electrical contacts of the circuit board. | 10-20-2011 |
20130070423 | COMPACT CONNECTOR ASSEMBLY FOR IMPLANTABLE MEDICAL DEVICE - A connector assembly for an implantable medical device includes a plurality of feedthroughs mounted in a conductive array plate, each feedthrough in the plurality of feedthroughs including a feedthrough pin electrically isolated from the conductive array plate by an insulator and an electronic module assembly including a plurality of conductive strips set in a non-conductive block. The plurality of conductive strips is in physical and electrical contact with the feedthrough pins at an angle of less than 135 degrees. The connector assembly further includes at least one circuit, the circuit including a plurality of conductors corresponding to the plurality of feedthroughs. The plurality of conductors of the circuit is in physical and electrical contact with a corresponding one of the conductive strips of the plurality of conductive strips of the electronic module assembly at an angle of less than 135 degrees. | 03-21-2013 |
Patent application number | Description | Published |
20090064076 | SYSTEMS, METHODS AND COMPUTER PRODUCTS FOR TRAVERSING SCHEMATIC HIERARCHY USING A SCROLLING MECHANISM - A method and a system for displaying hierarchical navigating, debugging and editing of selected hierarchical levels of design of a plurality of hierarchical levels of design in graphical hierarchical design applications, by assigning, from a schematic of the integrated circuit, a viewable scope of a block element desired for traversing. Opening the viewable scope of the block element, by using a mouse scrolling device to cause a cursor to highlight and roll in a downward direction over the highlighted block element, while holding down a predefined keyboard key. Then closing the viewable scope of the block element, by causing the cursor to be positioned in an empty area of the schematic, while holding down an other predefined keyboard key and rolling the mouse scrolling device in an upward direction. | 03-05-2009 |
20090189653 | Phase Lock Loop Clock Distribution Method and System - A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes. | 07-30-2009 |
20090278515 | MULTIPLE OUTPUT VOLTAGE REGULATOR - A multiple output voltage regulator includes a voltage regulator amplifier, a first device, and a second device. The voltage regulator amplifier includes a first input configured to receive a reference voltage and an output. The first device includes a first terminal, a second terminal, and a control terminal. The control terminal of the first device is coupled to the output of the voltage regulator amplifier, the first terminal of the first device is coupled to a power supply terminal, and the second terminal of the first device is coupled to a second input of the voltage regulator amplifier (to provide negative feedback) and is configured to be coupled to one side of a first load. The second device includes a first terminal, a second terminal, and a control terminal. The control terminal of the second device is coupled to the output of the voltage regulator amplifier, the first terminal of the second device is coupled to a power supply terminal, and the second terminal of the second device is configured to be coupled to one side of a second load. | 11-12-2009 |
20100001804 | SYSTEM TO IMPROVE A VOLTAGE-CONTROLLED OSCILLATOR AND ASSOCIATED METHODS - A system to improve a voltage-controlled oscillator may include a voltage-controlled oscillator. The system may also include a switch to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain. | 01-07-2010 |
20110298474 | IMPLEMENTING INTEGRAL DYNAMIC VOLTAGE SENSING AND TRIGGER - A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output. | 12-08-2011 |
20120047481 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO. | 02-23-2012 |
20120194236 | IMPLEMENTING PHASE LOCKED LOOP (PLL) WITH ENHANCED LOCKING CAPABILITY WITH A WIDE RANGE DYNAMIC REFERENCE CLOCK - A method and a phase locked loop (PLL) circuit for implementing enhanced locking capability with a wide range dynamic reference clock, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a Voltage Controlled Oscillator (VCO) and a plurality of filter comparators receiving a differential filter VCO control voltage. The plurality of filter comparators comparing the differential filter VCO control voltage values, provides a respective gate enable signal responsive to the compared differential filter VCO control voltage values. A clock signal is applied to an up/down counter responsive to the respective gate enable signal and the wide range dynamic reference clock. The count values of the up/down counter are provided to the VCO to select a respective frequency range for the VCO. | 08-02-2012 |
20120212280 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 08-23-2012 |
20120331432 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 12-27-2012 |
20130088269 | IMPLEMENTING CONTROL VOLTAGE MIRROR - A circuit for implementing a control voltage mirror for phase error and jitter performance optimization and a design structure on which the subject circuit resides are provided. The control voltage mirror is used with a phase locked loop filter utilizing a thin oxide filter capacitor connected to a control voltage and a distal side of the capacitor connected to a voltage reference. The control voltage mirror includes an operational amplifier holding voltage across the capacitor to be near or at zero volts, substantially eliminating capacitor leakage current to provide phase error and jitter performance optimization. | 04-11-2013 |
20130106461 | IMPLEMENTING SCREENING FOR SINGLE FET COMPARE OF PHYSICALLY UNCLONABLE FUNCTION (PUF) | 05-02-2013 |
20140132321 | IMPLEMENTING COMPACT CURRENT MODE LOGIC (CML) INDUCTOR CAPACITOR (LC) VOLTAGE CONTROLLED OSCILLATOR (VCO) FOR HIGH-SPEED DATA COMMUNICATIONS - A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit. | 05-15-2014 |
20140167213 | Moat Construction to Reduce Noise Coupling to a Quiet Supply - A semiconductor chip having a P− substrate and an N+ epitaxial layer grown on the P− substrate is shown. A P− circuit layer is grown on top of the N+ epitaxial layer. A first moat having an electrically quiet ground connected to a first N+ epitaxial region is created by isolating the first N+ epitaxial region with a first deep trench. The first moat is surrounded, except for a DC path, by a second moat with a second N+ epitaxial region, created by isolating the second N+ epitaxial region with a second deep trench. The second moat may be arranged as a rectangular spiral around the first moat. | 06-19-2014 |
Patent application number | Description | Published |
20080204154 | Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing - A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution. | 08-28-2008 |
20080208541 | Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing - A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL, and a design structure on which the subject circuit resides is provided. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution. | 08-28-2008 |
20080301503 | HIGH FREQUENCY DIVIDER STATE CORRECTION CIRCUIT - The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input. | 12-04-2008 |
20120133413 | DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT - The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal. | 05-31-2012 |