Patent application number | Description | Published |
20080237214 | METHODS AND HEAT TREATMENT APPARATUS FOR UNIFORMLY HEATING A SUBSTRATE DURING A BAKE PROCESS - Methods and heat treatment apparatus for heating a substrate and any layer carried on the substrate during a bake process. A heat exchange gap between the substrate and a heated support is at least partially filled by a gas having a high thermal conductivity. The high thermal conductivity gas is introduced into the heat exchange gap by displacing a lower thermal conductivity originally present in the heat exchange gap when the substrate is loaded. Heat transfer across the heat exchange gap is mediated by the high thermal conductivity gas. | 10-02-2008 |
20080241400 | VACUUM ASSIST METHOD AND SYSTEM FOR REDUCING INTERMIXING OF LITHOGRAPHY LAYERS - Embodiments of an apparatus and methods for curing a plurality of lithography layers while reducing the level of intermixing are generally described herein. Other embodiments may be described and claimed. | 10-02-2008 |
20090144691 | Enhanced Process Yield Using a Hot-Spot Library - The invention provides apparatus and methods for processing substrates using a hot-spot library. | 06-04-2009 |
20090220893 | Method for Patterning a Semiconductor Wafer - A method for etching a pattern on a surface is disclosed. A mask layer is disposed over a surface and a resist is disposed over the mask layer. The resist is exposed to light through the mask exposing primary pattern and sidelobe regions. The resist is developed and the mask layer is etched according to the resist pattern. A first material is deposited over the mask layer, wherein a gap is formed beneath the material and over the primary pattern region. The material is etched back so that the gap is exposed, and the primary pattern region is etched using the first material as a mask. | 09-03-2009 |
20100055624 | METHOD OF PATTERNING A SUBSTRATE USING DUAL TONE DEVELOPMENT - A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process. | 03-04-2010 |
20100055625 | METHOD OF PROCESS OPTIMIZATION FOR DUAL TONE DEVELOPMENT - A method for patterning a substrate is described. In particular, the invention relates to a method for double patterning a substrate using dual tone development. Further, the invention relates to optimizing a dual tone development process. | 03-04-2010 |
20100068654 | METHOD FOR CREATING GRAY-SCALE FEATURES FOR DUAL TONE DEVELOPMENT PROCESSES - A method of patterning a substrate using a dual-tone development process is described. The patterning method comprises forming a layer of radiation-sensitive material on a substrate, wherein the layer of radiation-sensitive material comprises a dual tone resist. Thereafter, the patterning method comprises performing one or more exposures of the layer of radiation-sensitive material to one or more patterns of radiation, wherein at least one of the one or more exposures comprises using a mask having a dual-tone mask pattern region configured for printing dual tone features and a half-tone mask pattern region configured for printing half-tone features. Furthermore, the half-tone mask pattern region is optimized for use with the dual tone resist. | 03-18-2010 |
20100075238 | Variable Resist Protecting Groups - A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process. | 03-25-2010 |
20100119960 | Dual Tone Development Processes - A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process. | 05-13-2010 |
20100248152 | Using Electric-Field Directed Post-Exposure Bake for Double-Patterning (D-P) - The invention provides a method of processing a substrate using Double-Patterning (D-P) processing sequences and Electric-Field Enhanced Layers (E-FELs). The D-P processing sequences and E-FELs can be used to create lines, trenches, vias, spacers, contacts, and gate structures using a minimum number of etch processes. | 09-30-2010 |
20100273099 | Flood exposure process for dual tone development in lithographic applications - A method and system for patterning a substrate using a dual tone development process is described. The method and system comprise a flood exposure of the substrate to improve process latitude for the dual tone development process. | 10-28-2010 |
20100273107 | Dual tone development with a photo-activated acid enhancement component in lithographic applications - A method and system for patterning a substrate using a lithographic process, such as a dual tone development process, is described. The method comprises use of at least one photo-activated acid enhancement component to improve process latitude for the dual tone development process. | 10-28-2010 |
20100273111 | Dual tone development with plural photo-acid generators in lithographic applications - A method and system for patterning a substrate using a dual tone development process is described. The method comprises use of plural photo-acid generators with or without a flood exposure of the substrate to improve process latitude for the dual tone development process. | 10-28-2010 |
20110205505 | LINE PATTERN COLLAPSE MITIGATION THROUGH GAP-FILL MATERIAL APPLICATION - Disclosed is a method and apparatus for mitigation of photoresist line pattern collapse in a photolithography process by applying a gap-fill material treatment after the post-development line pattern rinse step. The gap-fill material dries into a solid layer filling the inter-line spaces of the line pattern, thereby preventing line pattern collapse due to capillary forces during the post-rinse line pattern drying step. Once dried, the gap-fill material is depolymerized, volatilized, and removed from the line pattern by heating, illumination with ultraviolet light, by application of a catalyst chemistry, or by plasma etching. | 08-25-2011 |
20110269078 | SUBSTRATE TREATMENT TO REDUCE PATTERN ROUGHNESS - A method for patterning a substrate with extreme ultraviolet (EUV) radiation is provided. The method includes contacting a surface of the substrate with at least one surface modification agent that reacts with and bonds to the surface | 11-03-2011 |
20120045721 | METHOD FOR FORMING A SELF-ALIGNED DOUBLE PATTERN - The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures. | 02-23-2012 |
20120045722 | TECHNIQUE TO FORM A SELF-ALIGNED DOUBLE PATTERN - The invention can provide a method of processing a substrate using Double-Patterned-Shadow (D-P-S) processing sequences that can include (D-P-S) creation procedures, (D-P-S) evaluation procedures, and (D-P-S) transfer sequences. The (D-P-S) creation procedures can include deposition procedures, activation procedures, de-protecting procedures, sidewall angle (SWA) correction procedure, and Double Patterned (DP) developing procedures. | 02-23-2012 |
20120244645 | ELECTROSTATIC POST EXPOSURE BAKE APPARATUS AND METHOD - An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP. | 09-27-2012 |