Patent application number | Description | Published |
20100221867 | LOW COST SOI SUBSTRATES FOR MONOLITHIC SOLAR CELLS - A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate. | 09-02-2010 |
20100307572 | Heterojunction III-V Photovoltaic Cell Fabrication - A method for forming a heterojunction III-V photovoltaic (PV) cell includes performing layer transfer of a base layer from a wafer of a III-V substrate, the base layer being less than about 20 microns thick; forming an intrinsic layer on the base layer; forming an amorphous silicon layer on the intrinsic layer; and forming a transparent conducting oxide layer on the amorphous silicon layer. A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer. | 12-09-2010 |
20100307591 | Single-Junction Photovoltaic Cell - A method for forming a single-junction photovoltaic cell includes forming a dopant layer on a surface of a semiconductor substrate; diffusing the dopant layer into the semiconductor substrate to form a doped layer of the semiconductor substrate; forming a metal layer over the doped layer, wherein a tensile stress in the metal layer is configured to cause a fracture in the semiconductor substrate; removing a semiconductor layer from the semiconductor substrate at the fracture; and forming the single junction photovoltaic cell using the semiconductor layer. A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer. | 12-09-2010 |
20100310775 | Spalling for a Semiconductor Substrate - A method for spalling a layer from an ingot of a semiconductor substrate includes forming a metal layer on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot; and removing the layer from the ingot at the fracture. A system for spalling a layer from an ingot of a semiconductor substrate includes a metal layer formed on the ingot of the semiconductor substrate, wherein a tensile stress in the metal layer is configured to cause a fracture in the ingot, and wherein the layer is configured to be removed from the ingot at the fracture. | 12-09-2010 |
20110001167 | REDUCED DEFECT SEMICONDUCTOR-ON-INSULATOR HETERO-STRUCTURES - A semiconductor-on-insulator hetero-structure and a method for fabricating the semiconductor-on-insulator hetero-structure include a crystalline substrate and a dielectric layer located thereupon having an aperture that exposes the crystalline substrate. The semiconductor-on-insulator hetero-structure and the method for fabricating the semiconductor-on-insulator hetero-structure also include a semiconductor layer of composition different than the crystalline substrate located within the aperture and upon the dielectric layer. A portion of the semiconductor layer located aligned over the aperture includes a defect. A portion of the semiconductor layer located aligned over the dielectric layer does not include a defect. Upon removing the portion of the semiconductor layer located aligned over the aperture a reduced defect semiconductor-on-insulator hetero-structure is formed. | 01-06-2011 |
20110048516 | Multijunction Photovoltaic Cell Fabrication - A method for fabrication of a multijunction photovoltaic (PV) cell includes providing a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack; forming a top metal layer, the top metal layer having a tensile stress, on top of the junction having the largest bandgap; adhering a top flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the top metal layer. | 03-03-2011 |
20110048517 | Multijunction Photovoltaic Cell Fabrication - A method for fabrication of a multijunction photovoltaic (PV) cell includes forming a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the largest bandgap being located on the substrate to the junction having the smallest bandgap being located on top of the stack; forming a metal layer, the metal layer having a tensile stress, on top of the junction having the smallest bandgap; adhering a flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the metal layer. | 03-03-2011 |
20110084315 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 04-14-2011 |
20110175164 | DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS - A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices. | 07-21-2011 |
20110175166 | STRAINED CMOS DEVICE, CIRCUIT AND METHOD OF FABRICATION - A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance. | 07-21-2011 |
20120261762 | DEVICE STRUCTURE, LAYOUT AND FABRICATION METHOD FOR UNIAXIALLY STRAINED TRANSISTORS - A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices. | 10-18-2012 |
20130000707 | Multijunction Photovoltaic Cell Fabrication - A method for fabrication of a multijunction photovoltaic (PV) cell includes forming a stack comprising a plurality of junctions on a substrate, each of the plurality of junctions having a respective bandgap, wherein the plurality of junctions are ordered from the junction having the largest bandgap being located on the substrate to the junction having the smallest bandgap being located on top of the stack; forming a metal layer, the metal layer having a tensile stress, on top of the junction having the smallest bandgap; adhering a flexible substrate to the metal layer; and spalling a semiconductor layer from the substrate at a fracture in the substrate, wherein the fracture is formed in response to the tensile stress in the metal layer. | 01-03-2013 |
20130000708 | Multijunction Photovoltaic Cell Fabrication - A multijunction photovoltaic (PV) cell includes a bottom flexible substrate and a bottom metal layer located on the bottom flexible substrate. The multijunction photovoltaic cell also includes a semiconductor layer located on the bottom metal layer and a stack having a plurality of junctions located on the semiconductor layer, each of the plurality of junctions having a respective bandgap. The pluralities of junctions are ordered from the junction having the smallest bandgap being located on the substrate to the junction having the largest bandgap being located on top of the stack. | 01-03-2013 |
20130174909 | SINGLE-JUNCTION PHOTOVOLTAIC CELL - A single-junction photovoltaic cell includes a doped layer comprising a dopant diffused into a semiconductor substrate; a patterned conducting layer formed on the doped layer; a semiconductor layer comprising the semiconductor substrate located on the doped layer on a surface of the doped layer opposite the patterned conducting layer; and an ohmic contact layer formed on the semiconductor layer. | 07-11-2013 |
20130220408 | High Efficiency Flexible Solar Cells For Consumer Electronics - A flexible solar cell comprises an epitaxially grown III-V layer having a first layer grown on a base substrate, at least one intermediate layer grown on the first layer, and a cap layer grown on the at least one intermediate layer, the III-V layer being separated from the base substrate by controllably spalling the first layer from the base substrate; and a flexible substrate coupled to the epitaxially grown III-V layer. The flexible solar cell may be used to provide power to an electronic device. | 08-29-2013 |
20140113402 | High Efficiency Flexible Solar Cells For Consumer Electronics - A method comprises providing a base substrate having a surface; disposing layers of III-V semiconductor material on the surface of the base substrate using a chemical vapor deposition technique or a molecular beam epitaxy technique; disposing a stressor layer on the layer of III-V semiconductor material; operatively associating a flexible handle substrate with the stressor layer; and using controlled spalling to separate the layer of III-V semiconductor material from the base substrate to expose a surface of the layer of III-V semiconductor material. | 04-24-2014 |
20140299181 | Heterojunction III-V Photovoltaic Cell Fabrication - A heterojunction III-V photovoltaic (PV) cell includes a base layer comprising a III-V substrate, the base layer being less than about 20 microns thick; an intrinsic layer located on the base layer; an amorphous silicon layer located on the intrinsic layer; and a transparent conducting oxide layer located on the amorphous silicon layer. | 10-09-2014 |