Patent application number | Description | Published |
20090125866 | METHOD FOR PERFORMING PATTERN DECOMPOSITION FOR A FULL CHIP DESIGN - A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph. | 05-14-2009 |
20090172630 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-02-2009 |
20090177876 | AUTOMATED PROCESSOR GENERATION SYSTEM AND METHOD FOR DESIGNING A CONFIGURABLE PROCESSOR - A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification. | 07-09-2009 |
Patent application number | Description | Published |
20080244287 | Platform communication protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 10-02-2008 |
20090089606 | Opportunistic initiation of data traffic - A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device. | 04-02-2009 |
20090164818 | ACTIVITY WINDOW NOTIFICATION PROTOCOL - Power management protocols for maximizing energy efficiency in power usage by mobile devices are described in this application. The power management protocols may allow for at least two power states by a CPU—active state, and inactive state. The active state corresponds to an active window when the mobile device is functional at full capacity and using the full clock speed frequency. The inactive state and opportunistic flush and fill states may be maximized by coordinating the activity of the CPU and other devices associated with a mobile device such as a bus, memory, graphics controller, hard drive, etc. By coordinating the critical functions of devices and CPU to occur during the active window, and delaying non-critical functions until an active window, the inactive and off states may be maximized, resulting in power savings and efficiency. Other embodiments are also described in this application. | 06-25-2009 |
20090172434 | Latency based platform coordination - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 07-02-2009 |
20090249103 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 10-01-2009 |
20100080272 | Platform communication protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 04-01-2010 |
20110047395 | Platform Communication Protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 02-24-2011 |
20110078473 | LATENCY BASED PLATFORM COORDINATION - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 03-31-2011 |
20110302626 | LATENCY BASED PLATFORM COORDINATION - In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value. | 12-08-2011 |
20120198248 | PLATFORM POWER MANAGEMENT BASED ON LATENCY GUIDANCE - Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described. | 08-02-2012 |
20130117492 | PLATFORM COMMUNICATION PROTOCOL - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 05-09-2013 |
20140181334 | SYSTEM AND METHOD FOR DETERMINATION OF LATENCY TOLERANCE - Particular embodiments described herein can offer a method that includes receiving first link state information associated with a first device, determining, by a processor, an upward latency tolerance based, at least in part, on the first link state information, and providing the upward latency tolerance to a power management controller. | 06-26-2014 |
20140181563 | SYSTEM AND METHOD FOR DETERMINATION OF LATENCY TOLERANCE - Particular embodiments described herein can offer a method that includes determining that a first reported latency tolerance associated with at least one first device has not been received, and causing determination of a platform latency tolerance based, at least in part, on a first predefined latency tolerance, which is to serve as a substitute for the first reported latency tolerance. | 06-26-2014 |
Patent application number | Description | Published |
20100169684 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 07-01-2010 |
20100169685 | IDLE DURATION REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed. | 07-01-2010 |
20120254644 | ACTIVITY ALIGNMENT ALGORITHM BY MASKING TRAFFIC FLOWS - Embodiments of methods and apparatus for entering an activity alignment on state from an activity alignment off state; masking one or more traffic flows that are received during at least a part of the activity alignment on state; and entering the activity alignment off state from the activity alignment on state, after being in the activity alignment on state for at least a first time period, based at least in part on said masking the one or more traffic flows. Additional variants and embodiments are also disclosed. | 10-04-2012 |
20140095908 | DOWNSTREAM DEVICE SERVICE LATENCY REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, a transition from a first state to a second, different state for at least a portion of a downstream device may be identified. The first and second states may correspond to different levels relating to activity for at least a portion of the downstream device. Data corresponding to a service latency may be transmitted to an upstream device in response to the identified transition for one or more upstream devices to manage power based at least in part on the service latency. Other embodiments are also disclosed. | 04-03-2014 |
20140101470 | IDLE DURATION REPORTING FOR POWER MANAGEMENT - For one disclosed embodiment, data corresponding to an idle duration for one or more downstream devices may be received. Power may be managed based at least in part on the received data. Other embodiments are also disclosed. | 04-10-2014 |