Patent application number | Description | Published |
20100327422 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME, AND STACK MODULE AND MEMORY CARD INCLUDING THE SAME - A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided. | 12-30-2010 |
20110097846 | SEMICONDUCTOR CHIP, WAFER STACK PACKAGE USING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug. | 04-28-2011 |
20110284936 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer. | 11-24-2011 |
20130221519 | SEMICONDUCTOR DEVICES INCLUDING DUMMY SOLDER BUMPS - A semiconductor device includes a substrate on which integrated circuit units are formed, main solder bumps that are electrically connected to the integrated circuit units on the substrate and dummy solder bumps that are not electrically connected to the integrated circuit units on the substrate. The dummy solder bumps are narrower than wiring patterns immediately below the dummy solder bumps. | 08-29-2013 |
20130264720 | Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages - A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. | 10-10-2013 |
20130313722 | THROUGH-SILICON VIA (TSV) SEMICONDUCTOR DEVICES HAVING VIA PAD INLAYS - A semiconductor device includes an insulating layer on a surface of a substrate, a through-via structure vertically passing through the substrate and the insulating layer and being exposed on the insulating layer, and a via pad on a surface of the exposed through-via structure. The via pad includes a via pad body, and a via pad inlay below the via pad body and protruding into the insulating layer and surrounding the through-via structure. The via pad body and the via pad inlay include a via pad barrier layer directly on the insulating layer and a via pad metal layer on the via pad barrier layer. | 11-28-2013 |
20140124901 | INTEGRATED CIRCUIT CHIPS HAVING VERTICALLY EXTENDED THROUGH-SUBSTRATE VIAS THEREIN - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 05-08-2014 |
20140329382 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING BUMP - Provided is a method of fabricating a semiconductor device. The method includes forming a photoresist pattern having a side recess on a seed metal layer and forming a plating layer having a hem using a plating process to fill the side recess. | 11-06-2014 |