Slotboom, NL
Daan Maurits Slotboom, Rhenen NL
Patent application number | Description | Published |
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20110013188 | Object Alignment Measurement Method and Apparatus - A lithographic apparatus includes apparatus for measuring the alignment of an object. The measuring apparatus includes a plurality of alignment sensors, each including an alignment detector for measuring the position of an alignment mark over an alignment detection area. The measuring apparatus further includes a leveling sensor for measuring the height and/or tilt of an object in a leveling sensor detection area, and a feed-forward connection between said leveling sensor and said alignment sensors. | 01-20-2011 |
20120218533 | METHOD OF CALCULATING MODEL PARAMETERS OF A SUBSTRATE, A LITHOGRAPHIC APPARATUS AND AN APPARATUS FOR CONTROLLING LITHOGRAPHIC PROCESSING BY A LITHOGRAPHIC APPARATUS - Estimating model parameters of a lithographic apparatus and controlling lithographic processing by a lithographic apparatus includes performing an exposure using a lithographic apparatus projecting a pattern onto a wafer. A set of predetermined wafer measurement locations is measured. Predetermined and measured locations of the marks are used to generate radial basis functions. Model parameters of said substrate are calculated using the generated radial basis functions as a basis function across said substrate. Finally, the estimated model parameters are used to control the lithographic apparatus in order to expose the substrate. | 08-30-2012 |
20140168627 | Method of Operating a Lithographic Apparatus, Device Manufacturing Method and Associated Data Processing Apparatus and Computer Program Product - A reticle is loaded into a lithographic apparatus. The apparatus performs measurements on the reticle, so as to calculate alignment parameters for transferring the pattern accurately to substrates. Tests are performed to detect possible contamination of the reticle or its support. Either operation proceeds with a warning, or the patterning of substrates is stopped. The test uses may use parameters of the alignment model itself, or different parameters. The integrity parameters may be compared against reference values reflecting historic measurements, so that sudden changes in a parameter are indicative of contamination. Integrity parameters may be calculated from residuals of the alignment model. In an example, height residuals are used to calculate parameters of residual wedge (Rx′) and residual roll (Ryy′). From these, integrity parameters expressed as height deviations are calculated and compared against thresholds. | 06-19-2014 |
Daan Maurtis Slotboom, Rhenen NL
Patent application number | Description | Published |
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20090296058 | LITHOGRAPHIC APPARATUS AND DEVICE MANUFACTURING METHOD - A detection method for detecting a property of an extended pattern formed by at least one line generally extending in a first direction. The extended pattern is formed on a substrate or on a substrate table and may extend, for example, over a length of at least 50× the width of the line. The extended pattern is focus sensitive. The detection method includes moving the substrate table in a first direction and measuring along that first direction a property of the extended pattern. The property can be a result of a physical property of the extended pattern in a second direction perpendicular to the first direction. In a next step a calibration of the substrate table position can be derived from the measured position of the extended pattern. | 12-03-2009 |
20090305151 | LITHOGRAPHIC APPARATUS AND DEVICE MANUFACTURING METHOD - A detection method for detecting a property of an extended pattern formed by at least one line generally extending in a first direction. The extended pattern is formed on a substrate or on a substrate table and preferably extends over a length of at least 50× the width of the line. The extended pattern is focus sensitive. The detection method includes moving the substrate table in a first direction and measuring along that first direction a property of the extended pattern. The property can be a result of a physical property of the extended pattern in a second direction perpendicular to the first direction. In a next step a calibration of the substrate table position can be derived from the measured position of the extended pattern. | 12-10-2009 |
Jan Slotboom, Eersel NL
Patent application number | Description | Published |
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20140175528 | SEMICONDUCTOR MAGNETIC FIELD SENSORS - A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field. | 06-26-2014 |
20140347135 | BIPOLAR TRANSISTORS WITH CONTROL OF ELECTRIC FIELD - The invention provides a bipolar transistor circuit and a method of controlling a bipolar transistor, in which the bipolar transistor has a gate terminal for controlling the electric field in a collector region of the transistor. The bias voltage applied to the gate terminal is controlled to achieve different transistor characteristics. | 11-27-2014 |
Jan W. Slotboom, Eersel NL
Patent application number | Description | Published |
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20080258182 | Bicmos Compatible Jfet Device and Method of Manufacturing Same - A BiCMOS-compatible JFET device comprising source and drain regions ( | 10-23-2008 |
20100038676 | Semiconductor Devices with a Field Shaping Region - A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region. | 02-18-2010 |
20100097135 | TUNNEL FIELD EFFECT TRANSISTOR - A tunnel transistor includes source diffusion ( | 04-22-2010 |
20100246249 | CHARGE CARRIER STREAM GENERATING ELECTRONIC DEVICE AND METHOD - The present invention discloses an electronic device comprising a generator for generating a stream ( | 09-30-2010 |
Jan Willem Slotboom, Eersel NL
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20090114950 | Semiconductor Device and Method of Manufacturing such a Device - The invention relates to a semiconductor device ( | 05-07-2009 |
20120038002 | IC AND IC MANUFACTURING METHOD - Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate ( | 02-16-2012 |
20140312356 | Semiconductor Device - A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base. | 10-23-2014 |
20140347131 | SEMICONDUCTOR DEVICE AND CIRCUIT WITH DYNAMIC CONTROL OF ELECTRIC FIELD - A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit. | 11-27-2014 |
Michiel Slotboom, Oss NL
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20090179254 | Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device - Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the material of at least one of the current-carrying channel region and/or the source and drain regions is in an elastically strained state. | 07-16-2009 |