Patent application number | Description | Published |
20080261367 | METHOD FOR PROCESS INTEGRATION OF NON-VOLATILE MEMORY CELL TRANSISTORS WITH TRANSISTORS OF ANOTHER TYPE - A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region. | 10-23-2008 |
20080261407 | SEMICONDUCTOR DEVICE WITH HYDROGEN BARRIER AND METHOD THEREFOR - A method of forming a semiconductor device comprises providing a portion of a semiconductor device structure, wherein the portion includes a region susceptible to hydrogen incorporation due to subsequent device processing. For example, the subsequent device processing can include one or more of (i) forming a layer over the region, wherein the layer includes hydrogen and (ii) using gases containing hydrogen in a plasma for the subsequent device processing, wherein the semiconductor device is subject to an undesirable device characteristic alteration by hydrogen incorporation into the region. The method further comprises forming a hydrogen barrier layer overlying the region, wherein the hydrogen barrier layer prevents substantial migration of hydrogen made available due to the subsequent device processing into the underlying region. The method further includes performing the subsequent device processing. | 10-23-2008 |
20090291547 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 11-26-2009 |
20100112779 | METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING - An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit. | 05-06-2010 |
20110003444 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS - An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region. | 01-06-2011 |
20110179394 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 07-21-2011 |
20120068305 | LATERAL CAPACITOR AND METHOD OF MAKING - An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant. | 03-22-2012 |
20120104483 | NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer. The first metal layer, the high K dielectric, and the remaining portion of the protective layer are removed over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high K dielectric layer over the logic region. A conductive layer is deposited over the remaining portion of the dielectric layer and over the first metal layer. The NVM cell and the logic transistor are formed and this includes patterning the conductive layer. | 05-03-2012 |
20120126309 | INTEGRATED NON-VOLATILE MEMORY (NVM) AND METHOD THEREFOR - A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack. | 05-24-2012 |
20120175697 | MULTI-STATE NON-VOLATILE MEMORY CELL INTEGRATION AND METHOD OF OPERATION - A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device. | 07-12-2012 |
20120248523 | NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - An integrated circuit is disclosed that includes a split gate memory device comprising a select gate is located over a substrate. A charge storage layer includes a layer of discrete storage elements and a layer of high-k dielectric material covering at least one side of the layer of discrete storage elements. At least a portion of a control gate is located over the charge storage layer. The control gate includes a layer of barrier work function material and a layer of gate material located over the layer of barrier work function material. | 10-04-2012 |
20120252171 | NON-VOLATILE MEMORY AND LOGIC CIRCUIT PROCESS INTEGRATION - A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material. | 10-04-2012 |
20120252178 | PATTERNING A GATE STACK OF A NON-VOLATILE MEMORY (NVM) WITH FORMATION OF A CAPACITOR - A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region. | 10-04-2012 |
20120267758 | Isolated Capacitors Within Shallow Trench Isolation - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer ( | 10-25-2012 |
20120267759 | DECOUPLING CAPACITORS RECESSED IN SHALLOW TRENCH ISOLATION - A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer below a trench opening, a capacitor dielectric layer and a recessed top capacitor plate that is covered by an STI region and isolated from cross talk by a sidewall dielectric layer. | 10-25-2012 |
20120273857 | SEMICONDUCTOR DEVICE STRUCTURE AS A CAPACITOR - A capacitor structure includes a conductive region; a first dielectric layer over the conductive region; a conductive material within the first dielectric layer, wherein the conductive material is on the conductive region and forms a first plate electrode of the capacitor structure; an insulating layer within the first dielectric layer and surrounding the conductive material; a first conductive layer within the first dielectric layer and surrounding the insulating layer, wherein the first conductive layer forms a second plate electrode of the capacitor structure; a second conductive layer laterally extending from the first conductive layer at a top surface of the first dielectric layer; a second dielectric layer over the first dielectric layer; and a third conductive layer within the second dielectric layer and on the conductive material. | 11-01-2012 |
20120276705 | METHOD OF MAKING A SEMICONDUCTOR DEVICE AS A CAPACITOR - Forming a capacitor structure includes forming a first dielectric layer over a conductive region, wherein the first dielectric layer has a first conductive layer at a top surface of the first dielectric layer; forming a first opening in the first dielectric layer over the conductive region, wherein the first opening exposes a first sidewall of the first conductive layer; forming a second conductive layer within the first opening, wherein the second conductive layer contacts the first sidewall of the first conductive layer; removing a portion of the second conductive layer from the bottom of the first opening; forming an insulating layer within the first opening; removing a portion of the insulating layer from the bottom of the first opening; extending the first opening through the first dielectric layer to expose the conductive region; and filling the first opening with a conductive material, wherein the conductive material contacts the conductive region. | 11-01-2012 |
20120292683 | MEMORY WITH DISCRETE STORAGE ELEMENTS - A method of making a non-volatile memory cell includes forming a plurality of discrete storage elements. A tensile dielectric layer is formed among the discrete storage elements and provides lateral tensile stress to the discrete storage elements. A gate is formed over the discrete storage elements. | 11-22-2012 |
20130043540 | IMPLANT FOR PERFORMANCE ENHANCEMENT OF SELECTED TRANSISTORS IN AN INTEGRATED CIRCUIT - A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant. | 02-21-2013 |
20130055184 | METHOD AND SYSTEM FOR PHYSICAL VERIFICATION USING NETWORK SEGMENT CURRENT - A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer. | 02-28-2013 |
20130062529 | INCIDENT CAPACITIVE SENSOR - A capacitive sensor device for measuring radiation. The device includes two sensor regions and top plate structure. The sensor regions are of a material that generates electron-hole pairs when radiation strikes the material. A separation region is located between the two sensor regions. The capacitance between a sensor region and top plate is dependent upon radiation striking the sensor region. A blocking structure selectively and differentially blocks radiation having a parameter value in a range from the sensor region so as to differentially impact electron-hole pair generation of one sensor region with respect to electron-hole pair generation of the other sensor region at selected angles of incidence of the radiation. | 03-14-2013 |
20130063164 | CAPACITIVE SENSOR RADIATION MEASUREMENT - A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose. | 03-14-2013 |
20130105986 | SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES | 05-02-2013 |
20130137227 | LOGIC AND NON-VOLATILE MEMORY (NVM) INTEGRATION - A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate. | 05-30-2013 |
20130147051 | METHOD OF PROTECTING AGAINST VIA FAILURE AND STRUCTURE THEREFOR - A method is for forming a decoy via and a functional via. The method includes forming the functional via between a metal portion of a first interconnect layer and a portion of a second interconnect layer. The method further includes forming the decoy via in a protection region between the metal portion of the first interconnect layer and a metal portion of the third interconnect level. | 06-13-2013 |
20130171785 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate. | 07-04-2013 |
20130171786 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate. | 07-04-2013 |
20130178027 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer. | 07-11-2013 |
20130178054 | METHODS OF MAKING LOGIC TRANSISTORS AND NON-VOLATILE MEMORY CELLS - Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned. | 07-11-2013 |
20130214346 | NON-VOLATILE MEMORY CELL AND LOGIC TRANSISTOR INTEGRATION - A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening. | 08-22-2013 |
20130217197 | INTEGRATION TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC FOR SELECT GATE AND REPLACEMENT GATE FOR LOGIC - A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening. | 08-22-2013 |
20130264633 | LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION - A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer. | 10-10-2013 |
20130264634 | LOGIC TRANSISTOR AND NON-VOLATILE MEMORY CELL INTEGRATION - A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer. | 10-10-2013 |
20130264698 | SEMICONDUCTOR DEVICE WITH HEAT DISSIPATION - A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors. | 10-10-2013 |
20130264700 | SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING - A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver. | 10-10-2013 |
20130267072 | NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION - A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region. | 10-10-2013 |
20130267074 | INTEGRATION TECHNIQUE USING THERMAL OXIDE SELECT GATE DIELECTRIC FOR SELECT GATE AND APARTIAL REPLACEMENT GATE FOR LOGIC - A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer. | 10-10-2013 |
20130326446 | TECHNIQUES FOR CHECKING COMPUTER-AIDED DESIGN LAYERS OF A DEVICE TO REDUCE THE OCCURRENCE OF MISSING DECK RULES - A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed. | 12-05-2013 |
20130326448 | Techniques for Electromigration Stress Determination in Interconnects of an Integrated Circuit - In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment. | 12-05-2013 |
20130330893 | INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC - A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate. | 12-12-2013 |
20140001432 | APPLICATIONS FOR NANOPILLAR STRUCTURES | 01-02-2014 |
20140038317 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number. | 02-06-2014 |
20140038319 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero. | 02-06-2014 |
20140040839 | METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN - A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices. | 02-06-2014 |
20140094029 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero. | 04-03-2014 |
20140120713 | METHOD OF MAKING A LOGIC TRANSISTOR AND A NON-VOLATILE MEMORY (NVM) CELL - An oxide-containing layer is formed directly on a semiconductor layer in an NVM region, and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-k dielectric layer is formed directly on the semiconductor layer in a logic region. A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell. | 05-01-2014 |
20140123085 | SYSTEMS AND METHODS FOR DETERMINING AGING DAMAGE FOR SEMICONDUCTOR DEVICES - A method includes generating a circuit design and executing a simulation of the circuit design at a plurality of time slices. Type 1 damage and type 2 damage are determined for each time slice. A total type 1 damage is provided as a sum of the type 1 damage for all of the slices in which type 1 damage is greater than type 2 damage. A total type 2 damage is similarly added for the slices where the type 2 damage is dominant. A type 1 aging effect is determined based on the total type 1 damage. A type 2 aging effect is determined based on the total type 2 damage. The type 1 aging effect is added to the type 2 aging effect to obtain a total aging effect. The circuit design is tested using the total aging effect to determine if the circuit design provides adequate lifetime performance. | 05-01-2014 |
20140131788 | SEMICONDUCTOR DEVICES WITH NON-VOLATILE MEMORY CELLS - A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device. | 05-15-2014 |
20140210016 | IMPLANT FOR PERFORMANCE ENHANCEMENT OF SELECTED TRANSISTORS IN AN INTEGRATED CIRCUIT - A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant. | 07-31-2014 |
20140239440 | Thin Beam Deposited Fuse - A back-end-of-line thin ion beam deposited fuse ( | 08-28-2014 |
20140258582 | SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES - A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses. | 09-11-2014 |
20140329383 | SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING - A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver. | 11-06-2014 |
20140353797 | FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING - A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge. | 12-04-2014 |
20140353841 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location. | 12-04-2014 |
20150035151 | Capping Layer Interface Interruption for Stress Migration Mitigation - A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface. | 02-05-2015 |
20150037958 | METHODS OF MAKING MULTI-STATE NON-VOLATILE MEMORY CELLS - A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device. | 02-05-2015 |
20150040092 | Stress Migration Mitigation - A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer. | 02-05-2015 |
20150091178 | 3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS - A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads. | 04-02-2015 |
20150091187 | 3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS - A method for 3D device packaging utilizes through-hole metal post techniques to mechanically and electrically bond two or more dice. The first die includes a set of through-holes extending from a first surface of the first die to a second surface of the first die. The second die includes a third surface and a set of metal posts. The first die and the second die are stacked such that the third surface of the second die faces the second surface of the first die, and each metal post extends through a corresponding through-hole to a point beyond the first surface of the first die, electrically coupling the first die and the second die. | 04-02-2015 |
20150137311 | Thin Beam Deposited Fuse - A back-end-of-line thin ion beam deposited fuse ( | 05-21-2015 |
20150234961 | METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING - A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results. | 08-20-2015 |
20150249048 | STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN METAL TRACE OF INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) device includes a plurality of metal layers having metal traces, and a plurality of vias interconnecting the metal traces. The presence of vacancies within the metal layers may disrupt the functionality of the IC device if the vacancies migrate to the vias interconnecting the metal layers. To mitigate vacancy migration, stressor elements are formed at the metal traces to form stress effects in the metal traces that, depending on type, either serve to repel migrating vacancies from the via contact area or to trap migrating vacancies at a portion of the metal trace displaced from the contact area. The stressor elements may be formed as stress-inducing dielectric or conductive material overlying the metal traces, or formed by inducing a stress memory effect in a portion of the metal trace itself. | 09-03-2015 |
20150249140 | METHOD OF MAKING A LOGIC TRANSISTOR AND NON-VOLATILE MEMORY (NVM) CELL - A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal. | 09-03-2015 |
20150279853 | METHOD FOR FORMING A SPLIT-GATE DEVICE - A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer. | 10-01-2015 |
20150279854 | METHOD FOR FORMING A SPLIT-GATE DEVICE - Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate. | 10-01-2015 |
20150348898 | APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIRCUIT DEVICE TO MANAGE ELECTROMIGRATION FAILURES - A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect. | 12-03-2015 |
20150363533 | VOLTAGE AND CURRENT LIMITS FOR ELECTRONIC DEVICE BASED ON TEMPERATURE RANGE - A design verification system simulates operation of an electronic device to identify one or more power characteristic vs. temperature (PC-T) curves for the electronic device. Each of the one or more PC-T curves indicates, for a particular reliability characteristic limit, a range of power characteristic values over a corresponding range of temperatures that are not expected to result in the reliability characteristic limit being exceeded. Based on the one or more PC-T curves, the design verification system sets a range of power characteristic limits, over a corresponding range of temperatures, for the electronic device. During operation, the electronic device employs a temperature sensor to measure an ambient or device temperature, and sets its power characteristic (voltage or current) according to the measured temperature and the power characteristic limits. | 12-17-2015 |
20160093549 | INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT - A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information. | 03-31-2016 |
20160109506 | SEMICONDUCTOR DEVICE WITH UPSET EVENT DETECTION AND METHOD OF MAKING - A semiconductor device includes a substrate, first electronic circuitry formed on the substrate, a first diode buried in the substrate under the first electronic circuitry, and a first fault detection circuit coupled to the first diode to detect energetic particle strikes on the first electronic circuitry. | 04-21-2016 |
20160133574 | THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR - A semiconductor device includes a semiconductor substrate having a first major surface and a second major surface opposite the first major surface. A via extends through the substrate. The via is filled with conductive material and extends to at least the first major surface of the substrate. A thermal expansion inhibitor is over and in direct contact with the via proximate the first major surface. The thermal expansion inhibitor exerts a compressive stress on the conductive material closest to the thermal expansion inhibitor compared to the conductive material at a further distance from the thermal expansion inhibitor. | 05-12-2016 |
Patent application number | Description | Published |
20100076903 | Systems and Methods for Providing Personalized Delivery Services - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. Typically, the consignee indicates a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 03-25-2010 |
20120089530 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 04-12-2012 |
20120089531 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 04-12-2012 |
20120089533 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 04-12-2012 |
20120095934 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 04-19-2012 |
20130151436 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 06-13-2013 |
20130173490 | SYSTEMS, METHODS, APPARATUSES AND COMPUTER PROGRAM PRODUCTS FOR FACILITATING PRODUCT EXCHANGE SERVICES - An apparatus for facilitating product exchanges includes a processor and memory storing executable computer code causing the apparatus to at least perform operations including triggering an exchange procedure to return a product(s) to an entity responsive to receipt of an indicated selection of a return service option. The computer program code may further cause the apparatus to generate a return label(s) and identify a box(es) for inclusion of the product responsive to the receipt of the indicated selection and may generate a notification(s) notifying a user of a pickup time for the product and receive an indication that the product is packaged in the box(es), that information of the return label is captured and that the product is collected for delivery. The computer program code may further cause the apparatus to receive an indication that the product is delivered to entity. Corresponding methods and computer program products are also provided. | 07-04-2013 |
20130268455 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 10-10-2013 |
20130275326 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 10-17-2013 |
20130275327 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 10-17-2013 |
20130275328 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package prior to a first delivery attempt, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 10-17-2013 |
20130297526 | SYSTEMS AND METHODS FOR PROVIDING PERSONALIZED DELIVERY SERVICES - Systems and methods are disclosed for providing personalized delivery services by a carrier providing a package delivery service. For example, a consignee may indicate a delivery preference to be applied to delivery of a package, such as indicating a specific location where the package is to be left upon delivery, if the consignee is not present to accept the package. In one embodiment, the consignee may be notified by the carrier of the scheduled delivery of the package, and may be linked to the carrier's web site to indicate a delivery preference. Alternatively, the delivery preference may be indicated by the consignee proactively accessing the web site. After conveying a delivery preference, the carrier's systems communicate the delivery preference at the appropriate time to a portable computing device which informs the delivery personnel of the consignee's delivery preference. Other embodiments allow the consignor to indicate delivery preferences. | 11-07-2013 |