Patent application number | Description | Published |
20120119303 | Oxygen-Rich Layers Underlying BPSG - An integrated circuit structure and a method of forming the same are provided. The method includes providing a surface; performing an ionized oxygen treatment to the surface; forming an initial layer comprising silicon oxide using first process gases comprising a first oxygen-containing gas and tetraethoxysilane (TEOS); and forming a silicate glass over the initial layer. The method may further include forming a buffer layer using second process gases comprising a second oxygen-containing gas and TEOS, wherein the first and the second process gases have different oxygen-to-TEOS ratio. | 05-17-2012 |
20130075831 | METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER - A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer. | 03-28-2013 |
20130149807 | Backside Illuminated CMOS Image Sensor - A backside illuminated CMOS image sensor comprises a photo active region formed over a substrate using a front side ion implantation process and an extended photo active region formed adjacent to the photo active region, wherein the extended photo active region is formed by using a backside ion implantation process. The backside illuminated CMOS image sensor may further comprise a laser annealed layer on the backside of the substrate. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency. | 06-13-2013 |
20130153901 | BSI Image Sensor Chips and Methods for Forming the Same - A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer. | 06-20-2013 |
20130171766 | Annealing Methods for Backside Illumination Image Sensor Chips - A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer. | 07-04-2013 |
20130181258 | IMAGE SENSOR AND METHOD OF MANUFACTURING - An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate. | 07-18-2013 |
20130193538 | Methods and Apparatus for an Improved Reflectivity Optical Grid for Image Sensors - An improved reflectivity optical grid for image sensors. In an embodiment, a backside illuminated CIS device includes a semiconductor substrate having a pixel array area comprising a plurality of photosensors formed on a front side surface of the semiconductor substrate, each of the photosensors forming a pixel in the pixel array area; an optical grid material disposed over a backside surface of the semiconductor substrate, the optical grid material patterned to form an optical grid that bounds each of the pixels in the pixel array area and extending above the semiconductor substrate, the optical grid having sidewalls and a top portion; and a highly reflective coating formed over the optical grid, comprising a pure metal coating of a metal that is at least 99% pure, and a high-k dielectric coating over the pure metal coating that has a refractive index of greater than about 2.0. Methods are also disclosed. | 08-01-2013 |
20130193540 | Apparatus and Method for Reducing Dark Current in Image Sensors - A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer. | 08-01-2013 |
20130193541 | UV Radiation Recovery of Image Sensor - A method of an embodiment comprises forming a dielectric layer on a first side of an image sensor substrate, and exposing the dielectric layer to ultraviolet (UV) radiation. The image sensor substrate comprises a photo diode. A structure of an embodiment comprises a substrate and a charge-less dielectric. The substrate comprises a photo diode. The charge-less dielectric layer is on a first side of the substrate, and a total charge of the charge-less dielectric results in an average voltage drop of less than 0.2 V across the charge-less dielectric layer. | 08-01-2013 |
20130207213 | Grids in Backside Illumination Image Sensor Chips and Methods for Forming the Same - A device includes a semiconductor substrate, which has a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A first and a second grid line are parallel to each other, and are disposed on the backside of, and overlying, the semiconductor substrate. A stacked layer includes an adhesion layer, a metal layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines. | 08-15-2013 |
20130228886 | Method and Apparatus for Backside Illumination Sensor - Methods and apparatus for a backside illuminated (BSI) image sensor device are disclosed. A BSI sensor device is formed on a substrate comprising a photosensitive diode. The substrate may be thinned at the backside, then a B doped Epi-Si(Ge) layer may be formed on the backside surface of the substrate. Additional layers may be formed on the B doped Epi-Si(Ge) layer, such as a metal shield layer, a dielectric layer, a micro-lens, and a color filter. | 09-05-2013 |
20130234202 | Image Sensor Isolation Region and Method of Forming the Same - Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material. | 09-12-2013 |
20130241018 | Grids in Backside Illumination Image Sensor Chips and Methods for Forming the Same - A device includes a semiconductor substrate having a front side and a backside, a photo-sensitive device disposed on the front side of the semiconductor substrate, and a first and a second grid line parallel to each other. The first and the second grid lines are on the backside of, and overlying, the semiconductor substrate. The device further includes an adhesion layer, a metal oxide layer over the adhesion layer, and a high-refractive index layer over the metal layer. The adhesion layer, the metal oxide layer, and the high-refractive index layer are substantially conformal, and extend on top surfaces and sidewalls of the first and the second grid lines. | 09-19-2013 |
20130267045 | SHOWER HEAD APPARATUS AND METHOD FOR CONTROLLIGN PLASMA OR GAS DISTRIBUTION - An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head. | 10-10-2013 |
20130280849 | Image Sensor Isolation Region and Method of Forming the Same - Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material. | 10-24-2013 |
20130320419 | CIS Image Sensors with Epitaxy Layers and Methods for Forming the Same - A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric. | 12-05-2013 |
20130320478 | System and Method for Processing a Backside Illuminated Photodiode - System and method for processing a semiconductor device surface to reduce dark current and white pixel anomalies. An embodiment comprises a method applied to a semiconductor or photodiode device surface adjacent to a photosensitive region, and opposite a side having circuit structures for the device. A doped layer may optionally be created at a depth of less than about 10 nanometers below the surface of the substrate and may be doped with a boron concentration between about 1 | 12-05-2013 |
20140015031 | Apparatus and Method for Memory Device - An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer. | 01-16-2014 |
20140054653 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel. | 02-27-2014 |
20140117483 | BLACK LEVEL CORRECTION (BLC) STRUCTURE - One or more techniques or systems for forming a black level correction (BLC) structure are provided herein. In some embodiments, the BLC structure comprises a first region, a second region above at least some of the first region, and a third region above at least some of the second region. For example, the first region comprises silicon and the third region comprises a passivation dielectric. In some embodiments, the second region comprises a first sub-region, a second sub-region above the first sub-region, and a third sub-region above the second sub-region. For example, the first sub-region comprises a metal-silicide, the second sub-region comprises a metal, and the third sub-region comprises a metal-oxide. In this manner, a BLC structure is provided, such that a surface of the BLC structure is flush, at least because the third region is flush, for example. | 05-01-2014 |
20140167197 | Metal Shield Structure and Methods for BSI Image Sensors - A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate. | 06-19-2014 |
20140179071 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-26-2014 |
20140183681 | Surface Treatment for BSI Image Sensors - A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film. | 07-03-2014 |
20140211057 | Black Level Control for Image Sensors - An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images. | 07-31-2014 |
20140235008 | BACK SIDE ILLUMINATION (BSI) SENSORS, MANUFACTURING METHODS THEREOF, AND SEMICONDUCTOR DEVICE MANUFACTURING METHODS - Back side illumination (BSI) sensors, manufacturing methods thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes providing a workpiece having a front side and a back side opposite the front side. An integrated circuit is formed on the workpiece, and a first insulating material is formed on the back side of the workpiece. A second insulating material is formed over the first insulating material. The second insulating material is patterned to form a grid on the back side of the workpiece. | 08-21-2014 |
20140263944 | Light Sensing Device with Outgassing Hole - A light sensing device includes a substrate, a light sensing area on the substrate, and a light shielding layer over the substrate. The light shielding layer does not cover the light sensing area. At least one outgassing hole is formed through the light shielding layer. | 09-18-2014 |
20140264696 | DIELECTRIC FILM FOR IMAGE SENSOR - Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises a calibration region configured to detect a color level for image reproduction, such as a black calibration region configured to detect a black level for an image detected by the photodiode array. The image sensor comprises a dielectric film that is formed over the photodiode array and the calibration region. The dielectric film is configured to balance stress between the photodiode and the calibration region in order to improve accuracy of the calibration region. | 09-18-2014 |
20140264710 | SEAL RING STRUCTURE WITH ROUNDED CORNERS FOR SEMICONDUCTOR DEVICES - Seal ring structures are provided with rounded corner junctions or corner junctions that include polygons. The seal rings surround generally rectangular semiconductor devices such as integrated circuits, image sensors and other devices. The seal ring includes a configuration of two sets of generally parallel opposed sides and the corner junctions are the junctions at which adjacent orthogonal seal ring sides are joined. The seal rings are trench structures or filled trench structures in various embodiments. The rounded corner junctions are formed by a curved arc or multiple line segments joined together at various angles. The corner junctions that include one or more enclosed polygons include polygons with at least one polygon side being formed by one of the seal ring sides. | 09-18-2014 |
20140319626 | Metal Gate Stack Having TiAlCN as Work Function Layer and/or Blocking/Wetting Layer - A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer. | 10-30-2014 |
20150041851 | CIS Image Sensors with Epitaxy Layers and Methods for Forming the Same - A method includes performing a first epitaxy to grow a first epitaxy layer of a first conductivity type, and performing a second epitaxy to grow a second epitaxy layer of a second conductivity type opposite the first conductivity type over the first epitaxy layer. The first and the second epitaxy layers form a diode. The method further includes forming a gate dielectric over the first epitaxy layer, forming a gate electrode over the gate dielectric, and implanting a top portion of the first epitaxy layer and the second epitaxy layer to form a source/drain region adjacent to the gate dielectric. | 02-12-2015 |
20150054029 | Metal Gate Stack Having TaAlCN Layer - An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer. | 02-26-2015 |
20150087102 | Surface Treatment for BSI Image Sensors - A method comprises implanting ions in a substrate to form a plurality of photo diodes, forming an interconnect layer over a first side of the substrate and applying a first halogen treatment process to a second side of the substrate and forming a first silicon-halogen compound layer over the second side of the substrate as a result of applying the first halogen treatment process. | 03-26-2015 |