Patent application number | Description | Published |
20140268074 | Lithography System with an Embedded Cleaning Module - The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism. | 09-18-2014 |
20150235857 | METHOD OF FORMING SUBSTRATE PATTERN - According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region. | 08-20-2015 |
20150278429 | System and Method for Integrated Circuit Manufacturing - Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, the design layout having a main feature; performing a process correction to the main feature thereby generating a modified main feature; using a computer, generating a simulated contour of the modified main feature, the simulated contour having a plurality of points; generating a plurality of assistant data in computer readable format, wherein each assistant data includes at least one process performance factor associated with one of the points; and keeping the simulated contour and the assistant data for use by a further process stage, such as mask making, mask inspection, mask repairing, wafer direct writing, wafer inspection, and wafer repairing. | 10-01-2015 |
20150286146 | Systems and Methods for Improving Pattern Transfer - Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided. | 10-08-2015 |
20150311063 | Methods for Integrated Circuit Design and Fabrication - The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of: forming a plurality of first features over the target material layer using a first sub-layout, with each first feature having sidewalls; forming a plurality of spacer features, with each spacer feature conforming to the sidewalls of one of the first features and having a spacer width; and forming a plurality of second features over the target material layer using a second sub-layout. The method further includes steps of removing the plurality of spacer features from around each first feature and patterning the target material layer using the plurality of first features and the plurality of second features. Other methods and associated patterned semiconductor wafers are also provided herein. | 10-29-2015 |
20150311086 | Systems and Methods for a Sequential Spacer Scheme - The present disclosure describes methods for transferring a desired layout into a target layer. The method includes a step of forming a spacer, having a second width, around a first and a second desired layout feature pattern of the desired layout over a semiconductor substrate. The first desired layout feature pattern is formed using a first sub-layout and the second desired layout feature pattern is formed using a second sub-layout. The first and second desired layout feature patterns are separated by a first width. The method further includes forming a third desired layout feature pattern according to a third sub-layout. The third desired layout feature pattern is shaped in part by the spacer. The method further includes removing the spacer from around the first and second desired layout feature pattern and etching the target layer using the first, second, and third layout feature patterns as masking features. | 10-29-2015 |
20150318209 | Self-Aligned Semiconductor Fabrication With Fosse Features - The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer. | 11-05-2015 |
20150380256 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench. | 12-31-2015 |
20150380259 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first feature in a first hard mask layer formed over the patterning-target layer; forming a second feature in a second hard mask layer formed over the patterning-target layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the first feature in the first hard mask layer within a first trench to formed a reshaped first feature; selectively removing a portion of the second feature in the second hard mask layer within a second trench to form a reshaped second feature; and transferring the reshaped first feature and the reshaped second feature to the patterning-target layer. | 12-31-2015 |
20150380261 | Mechanisms for Forming Patterns Using Multiple Lithography Processes - The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern. | 12-31-2015 |