Patent application number | Description | Published |
20080245671 | Electrochemical Process to Recycle Aqueous Alkali Chemicals Using Ceramic Ion Conducting Solid Membranes - A method is provided to recycle and synthesize aqueous alkali chemicals from industrial and radioactively contaminated alkali salt based waste streams using a two-compartment electrolytic cell having an alkali cation-conductive ceramic membrane. The processes and apparatus provide the capability of recycling and synthesizing value added chemicals, including but not limited to, alkali hydroxides. | 10-09-2008 |
20080264778 | Cleansing Agent Generator and Dispenser - Electrochemical apparatus and processes for the point-of-use production of cleansing, sanitizing, and antimicrobial agents, such as sodium hypochlorite (NaOCl) or hypochlorous acid (HOCl). The processes may be used to produce NaOCl from seawater, low purity un-softened or NaCl-based salt solutions. HOCl may be produced from HCl solutions and water. NaOCl is produced using a sodium ion conductive ceramic membrane, such as membranes based on NASICON-type materials, in an electrolytic cell. HOCl is produced using an anion conductive membrane in an electrolytic cell. The cleansing, sanitizing, and antimicrobial agent may be generated on demand and used in household, industrial, and water treatment applications. | 10-30-2008 |
20080268327 | Advanced Metal-Air Battery Having a Ceramic Membrane Electrolyte Background of the Invention - A metal-air battery is disclosed in one embodiment of the invention as including a cathode to reduce oxygen molecules and an alkali-metal-containing anode to oxidize the alkali metal (e.g., Li, Na, and K) contained therein to produce alkali-metal ions. An aqueous catholyte is placed in ionic communication with the cathode to store reaction products generated by reacting the alkali-metal ions with the oxygen containing anions. These reaction products are stored as solutes dissolved in the aqueous catholyte. An ion-selective membrane is interposed between the alkali-metal containing anode and the aqueous catholyte. The ion-selective membrane is designed to be conductive to the alkali-metal ions while being impermeable to the aqueous catholyte. | 10-30-2008 |
20090057162 | Electrolytic Process to Separate Alkali Metal Ions from Alkali Salts of Glycerine - Methods and apparatus for separating alkali metal ions from alkali salts of glycerine to thereby form clean glycerine. These methods are enabled by the use of alkali ion conductive membranes in electrolytic cells that are chemically stable in low pH conditions. The alkali ion conductive membrane preferably includes a chemically stable ionic-selective polymer membrane. A layered composite of a chemically stable ionic-selective polymer and a cation-conductive ceramic membrane is disclosed. | 03-05-2009 |
20100044241 | Methods for Producing Sodium Hypochlorite with a Three-Compartment Apparatus Containing a Basic Anolyte - An electrochemical method for the production of a chlorine-based oxidant product, such as sodium hypochlorite, is disclosed. The method may potentially be used to produce sodium hypochlorite from sea water or low purity un-softened or NaCl-based salt solutions. The method utilizes alkali cation-conductive ceramic membranes, such as membranes based on NaSICON-type materials, and organic polymer membranes in electrochemical cells to produce sodium hypochlorite. Generally, the electrochemical cell includes three compartments and the first compartment contains an anolyte having a basic pH. | 02-25-2010 |
20100331170 | ALKALI METAL SUPER IONIC CONDUCTING CERAMIC - Metal ion conducting ceramic materials are disclosed having characteristics of high ion conductivity for certain alkali and monovalent metal ions at low temperatures, high selectivity for the metal ions, good current efficiency and stability in water and corrosive media under static and electrochemical conditions. The metal ion conducting ceramic materials are fabricated to be deficient in the metal ion. One general formulation of the metal ion conducting ceramic materials is Me | 12-30-2010 |
20110042238 | SENSOR TO MEASURE A CONCENTRATION OF ALKALI ALCOHOLATE - A sodium sensor to measure a concentration of sodium methylate in methanol. The sensor assembly includes a solid alkali ion conducting membrane, a reference electrode, and a measurement electrode. The solid alkali ion conducting membrane transports ions between two alkali-containing solutions, including an aqueous solution and a non-aqueous solution. The reference electrode is at least partially within an alkali halide solution of a known alkali concentration on a first side of the solid alkali ion conducting membrane. The measurement electrode is on a second side of the solid alkali ion conducting membrane. The measurement electrode exhibits a measurable electrical characteristic corresponding to a measured alkali concentration within the non-aqueous solution, to which the measurement electrode is exposed. | 02-24-2011 |
20110259736 | ELECTROLYTIC CELL FOR MAKING ALKALI ALCOHOLATES USING CERAMIC ION CONDUCTING SOLID MEMBRANES - Disclosed are electrolytic cells for making solutions of metal alcoholates in their corresponding alcohols using an electrolytic process. In one embodiment, sodium methylate in methanol is made from methanol and sodium hydroxide solution. The sodium hydroxide solution is placed in the anolyte compartment and the methanol is placed in the catholyte compartment, and the two compartments are separated by a ceramic membrane that selectively transports sodium under the influence of current. In preferred embodiments, the process is cost-effective and not environmentally harmful. | 10-27-2011 |
20120043219 | ELECTROCHEMICAL PROCESS FOR THE PRODUCTION OF SYNTHESIS GAS USING ATMOSPHERIC AIR AND WATER - A process is provided for synthesizing synthesis gas from carbon dioxide obtained from atmospheric air or other available carbon dioxide source and water using a sodium-conducting electrochemical cell. Synthesis gas is also produced by the coelectrolysis of carbon dioxide and steam in a solid oxide fuel cell or solid oxide electrolytic cell. The synthesis gas produced may then be further processed and eventually converted into a liquid fuel suitable for transportation or other applications. | 02-23-2012 |
20120292200 | ELECTROLYTIC PROCESS TO PRODUCE ALUMINUM HYDROXIDE - Methods and apparatus for separating aqueous solution of alkali aluminate into alkali hydroxide and aluminate hydroxide are disclosed. These methods are enabled by the use of alkali ion conductive membranes in electrolytic cells that are chemically stable and alkali ion selective. The alkali ion conductive membrane includes a chemically stable ionic-selective cation membrane. | 11-22-2012 |
20130048509 | ELECTROCHEMICAL PROCESS TO RECYCLE AQUEOUS ALKALI CHEMICALS USING CERAMIC ION CONDUCTING SOLID MEMBRANES - A method for producing an alkali metal hydroxide, comprises providing an electrolytic cell that includes at least one membrane having ceramic material configured to selectively transport alkali metal ions. The method includes introducing a first solution comprising an alkali metal hydroxide solution into a catholyte compartment such that said first solution is in communication with the membrane and a cathode. A second solution comprising at least one alkali metal salt and one or more monovalent, divalent, or multivalent metal salts is introduced into an anolyte compartment such that said second solution is in communication with the membrane and an anode. The method includes applying an electric potential to the electrolytic cell such that alkali metal ions pass through the membrane and are available to undertake a chemical reaction with hydroxyl ions in the catholyte compartment to form alkali metal hydroxide. | 02-28-2013 |
20140197351 | LITHIUM-ION-CONDUCTING MATERIALS - Lithium-ion-conducting ceramic materials are disclosed having characteristics of high lithium-ion conductivity at low temperatures, good current efficiency, and stability in water and corrosive media under static and electrochemical conditions. Some general formulas for the lithium-ion-conducting materials include M | 07-17-2014 |
Patent application number | Description | Published |
20090115018 | Transient voltage suppressor manufactured in silicon on oxide (SOI) layer - A transient voltage-suppressing (TVS) device supported on a semiconductor substrate is applied to protect an electronic device from a transient voltage. The TVS device includes a clamp diode functions with a high-side and a low side diodes for clamping a transient voltage disposed on a top layer of the semiconductor substrate insulated by a insulation layer constituting a TVS on silicon-on-insulator (SOI) device. In an exemplary embodiment, the insulator layer further includes a thick body oxide (BOX) layer having a thickness in the range of 250 Angstroms to 1 micrometer to sustain an application with a breakdown voltage higher than 25 volts. In another exemplary embodiment, the clamp diode further surrounded by a P-well and the P-well is formed on top of a P−/P+ substrate layer disposed above the insulator layer. | 05-07-2009 |
20090268361 | Transient voltage suppressor (TVS) with improved clamping voltage - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage. | 10-29-2009 |
20090273028 | Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes:
| 11-05-2009 |
20090283831 | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies - An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration. | 11-19-2009 |
20110049623 | Short Channel Lateral MOSFET and Method - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region. | 03-03-2011 |
20110127602 | Dual Channel Trench LDMOS Transistors and BCD Process with Deep Trench Isolation - A dual channel trench LDMOS transistor includes a substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on the substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the first conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the second conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain region of the second conductivity type spaced apart from the body region by a drain drift region. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor. | 06-02-2011 |
20110180845 | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies - An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration. | 07-28-2011 |
20110267724 | Circuit configurations to reduce snapback of a transient voltage suppressor - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit. The TVS circuit includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes' a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. In a preferred embodiment, the triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in a N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device. | 11-03-2011 |
20120086499 | LOW LEAKAGE DYNAMIC BI-DIRECTIONAL BODY-SNATCHING (LLDBBS) SCHEME FOR HIGH SPEED ANALOG SWITCHES - A bidirectional switch device includes a main pass field effect transistor (FET) connected to an input node and an output node. A body region of the first main pass transistor is tied to a voltage substantially halfway between the voltage at the input node side of the first main pass transistor and the voltage at the output node side of the transistor when the first main pass transistor is in an ON state. | 04-12-2012 |
20120187481 | Vertical Trench LDMOS Transistor - A vertical trench LDMOS transistor includes a semiconductor layer of a first conductivity type; a first trench formed in the semiconductor layer and filled with a trench dielectric and a trench gate is formed in the first trench; a body region of a second conductivity type formed in the semiconductor layer adjacent the first trench; a source region formed in the body region and adjacent the first trench; a planar gate insulated from the semiconductor layer by a second gate dielectric layer and overlying the body region; and a drain drift region formed in the semiconductor layer. The planar gate forms a lateral channel in the body region between the source region and the drain drift region, and the trench gate in the first trench forms a vertical channel in the body region along the sidewall of the first trench between the source region and the semiconductor layer. | 07-26-2012 |
20120235232 | Short Channel Lateral MOSFET - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region. | 09-20-2012 |
20120273878 | THROUGH SILICON VIA PROCESSING TECHNIQUES FOR LATERAL DOUBLE-DIFFUSED MOSFETS - The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel. | 11-01-2012 |
20120273879 | TOP DRAIN LDMOS - In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate. | 11-01-2012 |
20120281329 | TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH IMPROVED CLAMPING VOLTAGE - This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit. And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage. | 11-08-2012 |
20130016446 | CIRCUIT CONFIGURATIONS TO REDUCE SNAPBACK OF A TRANSIENT VOLTAGE SUPPRESSOR - This invention discloses a transient voltage suppressing (TVS) circuit that includes a triggering Zener diode connected between an emitter and a collector of a bipolar-junction transistor (BJT) wherein the Zener diode having a reverse breakdown voltage BV less than or equal to a BVceo of the BJT where BVceo stands for a collector to emitter breakdown voltage with base left open. The TVS circuit further includes a rectifier connected in parallel to the BJT for triggering a rectified current through the rectifier for further limiting an increase of a reverse blocking voltage. The triggering Zener diode, the BJT and the rectifier are formed in a semiconductor substrate by implanting and configuring dopant regions of a first and a second conductivity types in an N-well and a P-well whereby the TVS can be formed in parallel as part of the manufacturing processes of the electronic device. | 01-17-2013 |
20130075741 | Lateral PNP Bipolar Transistor Formed with Multiple Epitaxial Layers - A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance. | 03-28-2013 |
20130075746 | Lateral PNP Bipolar Transistor with Narrow Trench Emitter - A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches. | 03-28-2013 |
20130119465 | DUAL CHANNEL TRENCH LDMOS TRANSISTORS AND TRANSISTORS INTEGRATED THEREWITH - A dual channel trench LDMOS transistor includes a semiconductor layer of a first conductivity type formed on a substrate; a first trench formed in the semiconductor layer where a trench gate is formed in an upper portion of the first trench; a body region of the second conductivity type formed in the semiconductor layer adjacent the first trench; a source region of the first conductivity type formed in the body region and adjacent the first trench; a planar gate overlying the body region; a drain drift region of the first conductivity type formed in the semiconductor layer and in electrical contact with a drain electrode. The planar gate forms a lateral channel in the body region, and the trench gate in the first trench forms a vertical channel in the body region of the LDMOS transistor. | 05-16-2013 |
20140049293 | Three-Dimensional High Voltage Gate Driver Integrated Circuit - A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit | 02-20-2014 |
20140167218 | CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER - A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter. | 06-19-2014 |
20140268441 | ACTIVE ESD PROTECTION CIRCUIT - A high-voltage gate driver circuit configured to drive a high-side power switch and a low-side power switch includes an active dv/dt triggered ESD protection circuit coupled between a protected node and a power rail node. The active dv/dt triggered ESD protection circuit includes a dv/dt circuit controlling an ESD protection transistor connected between the protected node and the power rail node. The ESD protection transistor is turned on when an ESD event occurs at the protected node to conduct ESD current from the protected node to the power rail node. The dv/dt circuit is charged up after a time constant to disable the ESD protection transistor. | 09-18-2014 |
20140308784 | THREE-DIMENSIONAL HIGH VOLTAGE GATE DRIVER INTEGRATED CIRCUIT - A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit. | 10-16-2014 |
20150069464 | LATERAL PNP BIPOLAR TRANSISTOR FORMED WITH MULTIPLE EPITAXIAL LAYERS - A lateral bipolar transistor with deep emitter and deep collector regions is formed using multiple epitaxial layers of the same conductivity type. Deep emitter and deep collector regions are formed without the use of trenches. Vertically aligned diffusion regions are formed in each epitaxial layer so that the diffusion regions merged into a contiguous diffusion region after annealing to function as emitter or collector or isolation structures. In another embodiment, a lateral trench PNP bipolar transistor is formed using trench emitter and trench collector regions. In yet another embodiment, a lateral PNP bipolar transistor with a merged LDMOS transistor is formed to achieve high performance. | 03-12-2015 |