Patent application number | Description | Published |
20080247316 | Method Circuit and System for Data Flow Control - Disclosed is a method and circuit for a receiver to receive data from an associated data transmitter. The receiver may include a signaling module adapted to transmit a Ready-To-Receive (“RTR”) signal to the associated transmitter when a number of vacant bits in a data buffer exceeds a delay associated value. | 10-09-2008 |
20090138641 | Device, System, and Method of Handling Delayed Transactions - Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit. | 05-28-2009 |
20090177822 | Device, System, and Method of Handling Transactions - Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme. | 07-09-2009 |
20090185487 | AUTOMATED ADVANCE LINK ACTIVATION - Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays. | 07-23-2009 |
20090187683 | ADAPTIVE LINK WIDTH CONTROL - A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link. Conversely, if the real-time data transfer bandwidth is above the predetermined data transfer bandwidth standard, the link management unit is adapted to perform down-configuring the logical communications link by deactivating lanes within the logical communications link. The lanes consume less power when the lanes are deactivated relative to when the lanes are activated, thus the down-configuring reduces power consumption. | 07-23-2009 |
20090187870 | PLACEMENT DRIVEN ROUTING - A method placing items routing wiring pursuant to integrated circuit specifications to create an integrated circuit design. Once the initially placed design is legalized, rather that just starting wiring routing, the method identifies books in the integrated circuit design which contain blocked items. The method allows the routing process to be paused temporarily, and for the items to be moved to a certain extent. This movement process is controlled (limited according to signal power output by the associated books) so that the timing of the integrated circuit design is not affected by any such “mid-routing” movement. If the books do not have any blocked items, the process continues to route wires between the items and the books. If at any point before or during the routing of the wires it is found that the books do have blocked items, the process pauses the routing of the wires and performs any number of different processes to solve the blocked item situation (unblock the blocked items). | 07-23-2009 |
20120124291 | Secondary Cache Memory With A Counter For Determining Whether to Replace Cached Data - A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter. | 05-17-2012 |
20130036271 | DYNAMIC INDEX SELECTION IN A HARDWARE CACHE - Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data. | 02-07-2013 |