Patent application number | Description | Published |
20090276689 | Using short burst error detector in a queue-based system - A system, method, and device for detecting short burst errors in a queue-based system is disclosed. A first detector performs a data detection on a first input data set at a first time and on a second input data set at a second time. A second detector performs a data re-detection on input data sets. A decoder decodes derivations of the outputs of the first and second detector. A short burst error detector may perform a short burst error detection on decoded data and erase any detected errors. An output data buffer stores and orders the decoded data for output. | 11-05-2009 |
20100042891 | ERROR-CORRECTION DECODER EMPLOYING CHECK-NODE MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and one or more check-node units (CNUs). Each CNU is selectively configurable to operate in (i) a first mode that updates check-node (i.e., R) messages without averaging and (ii) a second mode that that updates R messages using averaging. Initially, each CNU is configured in the first mode to generate non-averaged R messages, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged R messages. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) each CNU is configured to operate in the second mode to generate averaged R messages, and (iii) the decoder attempts to recover the correct codeword using the averaged R messages. Averaging the R messages may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 02-18-2010 |
20100042897 | SELECTIVELY STRENGTHENING AND WEAKENING CHECK-NODE MESSAGES IN ERROR-CORRECTION DECODERS - In one embodiment, an LDPC decoder has a plurality of check-node units (CNUs) and a controller. Initially, the CNUs generate check-node messages based on an initial offset value selected by the controller. If the decoder converges on a trapping set, then the controller selects new offset values for missatisfied check nodes (MSCs), the locations of which are approximated, and/or unsatisfied check nodes (USCs). In particular, offset values are selected such that (i) the messages corresponding to the MSCs are decreased relative to the messages that would be generated using the initial offset value and/or (ii) the messages corresponding to the USCs are increased relative to the messages that would be generated using the initial offset value. Decoding is then continued for a specified number of iterations to break the trapping set. In other embodiments, the controller selects scaling factors rather than, or in addition to, offset values. | 02-18-2010 |
20100042905 | ADJUSTING INPUT SAMPLES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder. | 02-18-2010 |
20100042906 | ADJUSTING SOFT-OUTPUT VALUES IN TURBO EQUALIZATION SCHEMES TO BREAK TRAPPING SETS - In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword. | 02-18-2010 |
20100091629 | Method for detecting short burst errors in LDPC system - The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors. | 04-15-2010 |
20100100788 | Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel - The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*G | 04-22-2010 |
20100115209 | METHODS AND APPARATUS FOR DETECTING A SYNCMARK IN A HARD DISK DRIVE - Methods and apparatus are provided for detecting a syncMark in a read channel, such as a hard disk drive. A syncMark is detected in a sector in an iterative read channel by obtaining a sector signal from a storage media, the sector signal comprising a first syncMark, data and a second syncMark substantially at an end of the sector; determining whether the first syncMark is detected in the sector signal; searching for the second syncMark if the first syncMark is not detected in the sector signal; and detecting and decoding the sector signal based on a detection of the second syncMark. The second syncMark may be positioned, for example, following data in the sector signal. The second syncMark can be searched for in a window within the signal sector that is based on an estimated location of the first syncMark. | 05-06-2010 |
20100146229 | Interleaver and de-interleaver for iterative code systems - In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector. | 06-10-2010 |
20100235718 | Decoding Techniques for Correcting Errors Using Soft Information - Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected. | 09-16-2010 |
20100269026 | ERROR PATTERN GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING - The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths. | 10-21-2010 |
20110119553 | SUBWORDS CODING USING DIFFERENT ENCODING/DECODING MATRICES - In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices. | 05-19-2011 |
20110199699 | FREQUENCY-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out media defect (MD). | 08-18-2011 |
20110235204 | DETECTION OF HARD-DISC DEFECT REGIONS USING SOFT DECISIONS - In a hard-disc drive, a defect region on the hard disc is detected by generating two statistical measures (e.g., β | 09-29-2011 |
20110235490 | AMPLITUDE-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS - In a hard-disc drive, a defect region on the hard disc is classified as corresponding to either thermal asperity (TA) or media defect (MD) by generating two statistical measures. A first measure (e.g., ∝ | 09-29-2011 |
20110246856 | Systems and Methods for Efficient Data Storage - Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data. | 10-06-2011 |
20110264979 | ERROR-CORRECTION DECODER EMPLOYING EXTRINSIC MESSAGE AVERAGING - In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets. | 10-27-2011 |
20110292535 | METHODS AND APPARATUS FOR SYNCHRONIZATION MARK DETECTION BASED ON A POSITION OF AN EXTREME DISTANCE METRIC - Methods and apparatus are provided for detection of a synchronization mark based on a position of an extreme distance metric. A synchronization mark is detected in a received signal by computing a distance metric between the received signal and an ideal version of the received signal expected when reading the synchronization mark, wherein the distance metric is computed for a plurality of positions within a search window; determining a substantially extreme distance metric within the search window; and detecting the synchronization mark based on a position of the substantially extreme distance metric. The distance metric can comprise a sum of square differences or a Euclidean distance between the received signal and the ideal version of the received signal. | 12-01-2011 |
20110311002 | Turbo-Equalization Methods For Iterative Decoders - Certain embodiments of the present invention are improved turbo-equalization methods for decoding encoded codewords. In one embodiment, in global decoding iteration i, the magnitude values of all decoder-input LLR values (L | 12-22-2011 |
20120063022 | Systems and Methods for Inter-track Interference Compensation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. | 03-15-2012 |
20120063023 | Systems and Methods for Block-wise Inter-track Interference Compensation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a block-wise data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, and an inter-track interference signal estimator circuit. The data buffer is operable to store a previous track data set corresponding to a block. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set across the block based at least in part on the previous track data set and a current track data set. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set across the block based at least in part on the previous track data set and the inter-track interference response from the previous track data set. | 03-15-2012 |
20120063024 | Systems and Methods for Handling Sector Gaps in Inter-track Interference Compensation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes an inter-track interference determination circuit operable to calculate an inter-track interference from a previous track data set based at least in part on the previous track data set and a current track data set. The previous track data set includes a gap. A portion of the data in the previous track data set corresponds to a previous track on a storage medium, and the data in the previous track data set corresponding to the gap corresponds to a track preceding a previous track. | 03-15-2012 |
20120063284 | Systems and Methods for Track to Track Phase Alignment - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a data buffer, an inter-track interference response circuit, an inter-track interference signal estimator circuit, and a sync mark detector circuit. The data buffer is operable to store a previous track data set that includes a first sync pattern. The inter-track interference response circuit is operable to estimate an inter-track interference response from the previous track data set based at least in part on the previous track data set and a current track data set. The current track data set includes a second sync pattern. The inter-track interference signal estimator circuit is operable to calculate an inter-track interference from the previous track data set based at least in part on the previous track data set and the inter-track interference response from the previous track data set. The sync mark detector circuit operable to identify the first sync pattern in the inter-track interference from the previous track data set in the current track data set. | 03-15-2012 |
20120087033 | Systems and Methods for Identifying Potential Media Failure - Various embodiments of the present invention provide systems and methods for medium utilization control. As an example, a method for identifying potentially damaged media regions is discussed that includes receiving a data set; performing a data detection process on the data set to yield a detected output and a status value corresponding to the data set; performing a data decoding process on the detected output to yield a decoded output; and identifying a region of a storage medium from which the data set was derived as failing based at least in part on the status value. | 04-12-2012 |
20120089657 | Systems and Methods for Partially Conditioned Noise Predictive Equalization - Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits. | 04-12-2012 |
20120089883 | Systems and Methods for Error Correction Using Irregular Low Density Parity Check Codes - Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated. | 04-12-2012 |
20120089888 | Systems and Methods for Multi-Level Quasi-Cyclic Low Density Parity Check Codes - Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains. | 04-12-2012 |
20120120784 | Systems and Methods for Sync Mark Detection Metric Computation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a pattern detection circuit is discussed that includes a distance calculation circuit and a comparator circuit. The distance calculation circuit is operable to calculate a noise whitened distance between a reference signal and a received input to yield a comparison value. The comparator circuit is operable to compare the comparison value with a threshold value. | 05-17-2012 |
20120124118 | Systems and Methods for Variance Dependent Normalization for Branch Metric Calculation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a noise predictive filter circuit, a scaling factor adaptation circuit, and a scaling factor application circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based on a filter tap to yield a noise filtered output. The scaling factor adaptation circuit is operable to calculate a scaling factor based at least in part on a derivative of the noise filtered output. The scaling factor application circuit is operable to apply the scaling factor to scale the noise filtered output. | 05-17-2012 |
20120124119 | Systems and Methods for Self Tuning Target Adaptation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial. The adaptation circuit is operable to adaptively calculate the equalizer coefficient, the noise predictive filter coefficient and the target polynomial. | 05-17-2012 |
20120124241 | Systems and Methods for Sync Mark Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a circuit for data processing is described that includes a sync mark pattern match calculation circuit and an indication circuit. The sync mark pattern match calculation circuit is operable to provide at least a first comparison value corresponding to a comparison between a received input data set and a sync mark pattern, and a second comparison value corresponding to a comparison between the received input data set and a subset of the sync mark pattern and a subset of a preamble pattern. The indication circuit is operable to compare the first comparison value with the second comparison value, and to assert a sync found signal based at least in part on the comparison of the first comparison value and the second comparison value. | 05-17-2012 |
20120170678 | METHODS AND APPARATUS FOR TRELLIS-BASED MODULATION ENCODING - Methods and apparatus are provided for trellis-based modulation encoding. A signal is modulation encoded by encoding one or more blocks of the signal using one or more corresponding edges in a trellis, wherein each edge in the trellis has a corresponding bit pattern; selecting a winning path through the trellis based on at least one transition-based run-length constraint; and generating an encoded sequence using edges associated with the winning path. Exemplary trellis pruning techniques are also provided. The winning path through the trellis is selected by minimizing one or more modulation metrics. | 07-05-2012 |
20120173950 | Systems and Methods for Efficient Data Storage - Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data. | 07-05-2012 |
20120200954 | Systems and Methods for Off Track Error Recovery - Various embodiments of the present invention provide systems and methods for recovering data from a storage medium. As an example, a data recovery circuit is disclosed that includes: a controller circuit, a data processing circuit, a selector circuit, and a combining circuit. The controller circuit is operable to position a sensor over a track of the storage medium at a first distance from the center of the track to yield a first data set, and to position the sensor over the track of the storage medium at a second distance from the center of the track to yield a second data set. The data processing circuit is operable to process a processing data set, and the selector circuit is operable to select between the first data set and a combined data set as the processing data set. The combining circuit is operable to combine the first data set with at least the second data set to yield the combined data set. | 08-09-2012 |
20120207201 | Systems and Methods for Data Detection Using Distance Based Tuning - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path. | 08-16-2012 |
20120212849 | Systems and Methods for Data Pre-Coding Calibration - Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value. The pre-code selection circuit is operable to determine a selectable configuration of the first data detector circuit based at least in part on the first comparison value and the second comparison value. | 08-23-2012 |
20120236428 | Systems and Methods for Sync Mark Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit and a data detection circuit. The equalizer circuit is operable to filter a series of samples based at least in part on a filter coefficient and to provide a corresponding series of filtered samples. The data detection circuit includes: a core data detector circuit and a coefficient determination circuit. The core data detector circuit is operable to perform a data detection process on the series of filtered samples and to provide a most likely path and a next most likely path. The coefficient determination circuit operable to update the filter coefficient based at least in part on the most likely path and the next most likely path. | 09-20-2012 |
20120236429 | Systems and Methods for Sample Averaging in Data Processing - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set. | 09-20-2012 |
20120262814 | Systems and Methods for Data Processing - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a data decoder circuit, and a multi-path circuit. The data detector circuit is operable to apply a data detection algorithm to a data input and a decoder output to yield a detected output. The data decoder circuit is operable to apply a decoding algorithm to a decoder input to yield the decoder output and a status input. The multi-path circuit is operable to provide the decoder input based at least in part on the detected output and the status input. | 10-18-2012 |
20120266055 | Systems and Methods for Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. As an example, a data processing circuit is disclosed that includes a defect detector circuit and a comparator circuit. The defect detector circuit is operable to calculate a correlation value combining at least three of a data input derived from a medium, a detector extrinsic output, a detector intrinsic output and a decoder output. The comparator circuit is operable to compare the correlation value to a threshold value and to assert a media defect indicator when the correlation value is less than the threshold value. | 10-18-2012 |
20120281305 | Systems and Methods for Servo Data Detection - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a codeword detector circuit operable to apply a codeword based data detection algorithm to a data input corresponding to an encoded servo data region to yield a detected output, and a servo address mark processing circuit operable to identify a pre-defined pattern in the detected output. | 11-08-2012 |
20120300332 | Systems and Methods for Data Addressing in a Storage Device - Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output. | 11-29-2012 |
20120331363 | Systems and Methods for Reduced Format Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector. | 12-27-2012 |
20120331370 | Systems and Methods for Non-Binary Decoding - Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output. | 12-27-2012 |
20130019141 | Min-Sum Based Non-Binary LDPC DecoderAANM Wang; Chung-LiAACI San JoseAAST CAAACO USAAGP Wang; Chung-Li San Jose CA USAANM LI; ZongwangAACI San JoseAAST CAAACO USAAGP LI; Zongwang San Jose CA USAANM Yang; ShaohuaAACI San JoseAAST CAAACO USAAGP Yang; Shaohua San Jose CA US - Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors. | 01-17-2013 |
20130021187 | Systems and Methods for ADC Based Timing and Gain Control - Various embodiments of the present invention provide circuits, systems and methods for data processing. For example, a data processing circuit is discussed that includes: an analog to digital converter circuit, a target response circuit, and a timing circuit. The analog to digital converter circuit is operable to receive a data input and to provide corresponding digital samples synchronous to a sampling phase. The sampling phase corresponds to a phase feedback. The target response circuit is operable to provide an expected output corresponding to a known input. The timing circuit is operable to generate the phase feedback based at least in part on values derived from the expected output. | 01-24-2013 |
20130021690 | Systems and Methods for User Data Based Fly Height Calculation - Various embodiments of the present invention provide systems and methods for calculating and/or modifying fly height. For example, a circuit for calculating fly height is disclosed that includes: a first pattern detector circuit, a second pattern detector circuit, a first pattern fly height calculation circuit, a second pattern fly height calculation circuit, a first averaging circuit, a second averaging circuit, and a combining circuit. | 01-24-2013 |
20130024163 | Systems and Methods for Early Stage Noise Compensation in a Detection Channel - Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output. | 01-24-2013 |
20130024740 | Systems and Methods for Mitigating Stubborn Errors in a Data Processing System - Various embodiments of the present invention provide data processing circuits that include: a data detector circuit, a data decoder circuit, and a modification circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output. The data decoder circuit is operable to apply a data decode algorithm to a decode input to yield a decoded output. The decode input is selected between at least the detected output, and a modified version of the detected output. The modification circuit is operable to receive the detected output and to provide the modified version of the detected output. | 01-24-2013 |
20130054664 | Systems and Methods for Anti-Causal Noise Predictive Filtering in a Data Channel - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit. | 02-28-2013 |
20130077186 | Systems and Methods for Pattern Dependent Target Adaptation - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a noise predictive filter circuit, a data detector circuit, and a first and a second pattern dependent adaptive target circuits. The noise predictive filter circuit includes at least a first pattern dependent filter circuit operable to perform noise predictive filtering on a data input for a first pattern using a first adaptive target to yield a first noise predictive output, and a second pattern dependent filter circuit operable to perform noise predictive filtering on the data input for a second pattern using a second adaptive target to yield a second noise predictive output. The data detector circuit is operable to apply a data detection algorithm to the first noise predictive output and the second noise predictive output to yield a detected output. The first pattern dependent adaptive target circuit is operable to adaptively calculate the first adaptive target based at least in part on the first noise predictive output and a training sequence. The second pattern dependent adaptive target circuit operable to adaptively calculate the second adaptive target based at least in part on the second noise predictive output and the training sequence. | 03-28-2013 |
20130091403 | PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL - The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*G | 04-11-2013 |
20130097475 | LDPC Decoder With Targeted Symbol Flipping - Various embodiments of the present invention provide systems and methods for decoding data in a non-binary LDPC decoder with targeted symbol flipping. For example, a non-binary low density parity check data decoder is disclosed that comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor. | 04-18-2013 |
20130103731 | Systems and Methods for Efficient Data Channel Testing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a pseudo-random sequence generator circuit, a decoder circuit, and a pseudo-random sequence reconstitution circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a detected output. The pseudo-random sequence generator circuit is operable to generate an interim data sequence and to generate a second data set based upon a combination of the detected output and the interim data sequence. The decoder circuit is operable to apply a data decode algorithm to a derivative of the second data set to yield a third data set. | 04-25-2013 |
20130111289 | SYSTEMS AND METHODS FOR DUAL PROCESS DATA DECODING | 05-02-2013 |
20130111290 | Systems and Methods for Ambiguity Based Decode Algorithm Modification | 05-02-2013 |
20130111294 | Systems and Methods for Late Stage Precoding | 05-02-2013 |
20130111297 | Systems and Methods for Symbol Selective Scaling in a Data Processing Circuit | 05-02-2013 |
20130111306 | Detector with Soft Pruning | 05-02-2013 |
20130111309 | Systems and Methods for Selective Decode Algorithm Modification | 05-02-2013 |
20130120167 | Systems and Methods for Memory Efficient Data Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a data decoder circuit. The data decoder circuit is operable to: apply a decoding algorithm to a decoder input on a first decoder iteration to yield a first decoder output; compress an output derived from the first decoder output to yield a compressed decoder output; de-compress the compressed decoder output to yield a second decoder output; and apply the decoding algorithm to the second decoder output to yield a third decoder output. | 05-16-2013 |
20130124950 | Low Latency Enumeration Endec - Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data. | 05-16-2013 |
20130139022 | Variable Sector Size LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding variably sized blocks of data in an LDPC decoder. For example, in one embodiment an apparatus includes a low density parity check decoder operable to perform decoding of a plurality of circulant sub-matrices from an H matrix, and a controller connected to the low density parity check decoder, operable to omit any of the plurality of circulant sub-matrices from the decoding if they do not contain user data. | 05-30-2013 |
20130139023 | Variable Sector Size Interleaver - Various embodiments of the present invention are related to methods and apparatuses for interleaving data, and more particularly to methods and apparatuses for interleaving variably sized blocks of data. For example, in one embodiment an apparatus includes a data partitioner operable to partition the block of data into a real data portion and a missing bits portion. The real data portion is adapted to contain data bits from the variably sized block of data and the missing bits portion is adapted to be filled with a variable number of the data bits. The apparatus also includes at least one local interleaver operable to apply a permutation across each of a plurality of sub-portions of the real data portion and the missing bits portion, and a global interleaver operable to apply a global permutation across the real data portion. | 05-30-2013 |
20130148226 | Systems and Methods for Zone Servo Timing Gain Recovery - Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing system is disclosed that includes Various embodiments of the present invention provide data processing systems that include an analog to digital converter circuit and a phase and gain computation circuit. The analog to digital converter circuit is operable to convert an analog input into a series of digital samples. At least a portion of the series of digitals samples represent a periodic signal from a servo data region. The phase and gain computation circuit is operable to: determine an approximate amplitude of the periodic signal based at least in part upon the digital samples representing the periodic signal from the servo data region; determine a gain based at least in part on the approximate amplitude; and determine a phase based at least in part on the approximate amplitude. | 06-13-2013 |
20130148232 | Systems and Methods for Combined Binary and Non-Binary Data Processing - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit. | 06-13-2013 |
20130148233 | Systems and Methods for SNR Measurement Using Equalized Data - Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is discussed that includes: an equalizer circuit, a signal to noise ratio calculation circuit, and a parameter adjustment circuit. The equalizer circuit is operable to equalize a data input to yield an equalized output. The signal to noise ratio calculation circuit is operable to calculate a signal to noise ratio of the equalized output based at least in part on a noise power derived from the equalized output. The parameter adjustment circuit is operable to adjust a parameter based at least in part on the signal to noise ratio. | 06-13-2013 |
20130151923 | Systems and Methods for Scalable Data Processing Shut Down - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 06-13-2013 |
20130159634 | Systems and Methods for Handling Out of Order Reporting in a Storage Device - Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device. | 06-20-2013 |
20130173988 | Mixed Domain FFT-Based Non-Binary LDPC Decoder - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for decoding data in a mixed domain FFT-based non-binary LDPC decoder. For example, in one embodiment an apparatus includes a message processing circuit operable to process variable node messages and check node messages in a log domain, and a check node calculation circuit in the low density parity check decoder operable to perform a Fast Fourier Transform-based check node calculation in a real domain. The message processing circuit and the check node calculation circuit perform iterative layer decoding. | 07-04-2013 |
20130173994 | Variable Barrel Shifter - In one embodiment a variable barrel shifter includes a shifter operable to apply a cyclic shift to each of a number of portions of a data word, a pivot circuit operable to swap sections of the data word around at least one pivot point in the data word, a first multiplexer operable to select between an input of the variable barrel shifter or an output of the pivot circuit as an input to the shifter, a second multiplexer operable to select between the input of the variable barrel shifter or an output of the shifter as an input to the pivot circuit, and a third multiplexer operable to select between the output of the shifter or the output of the pivot circuit as an output to the variable barrel shifter. | 07-04-2013 |
20130191618 | Systems and Methods for Dynamic Scaling in a Data Decoding System - Various embodiments of the present invention provide systems and methods for data processing using variable scaling. | 07-25-2013 |
20130198584 | Systems and Methods for Multi-Pass Alternate Decoding - Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit. | 08-01-2013 |
20130205146 | Systems and Methods for Power Governance in a Data Processing Circuit - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. | 08-08-2013 |
20130208377 | Systems and Methods for Adaptive Decoder Message Scaling - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for adaptively modifying a scaling factor in a data processing system. | 08-15-2013 |
20130219233 | Systems and Methods for Quality Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 08-22-2013 |
20130232360 | Data Processing System with Thermal Control - Various embodiments of the present invention provide systems and methods for a data processing system with thermal control. For example, a data processing system with thermal control is disclosed that includes a number of data processors and a scheduler, which is operable to determine the power consumption of the data processors and to switch the data processing system from a first mode to a second mode and from the second mode to a third mode. The data processing system consumes less power in the third mode than in the first mode. The second mode prepares the data processing system to enter the third mode. | 09-05-2013 |
20130246877 | Systems and Methods for Compression Driven Variable Rate Decoding in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate encoding and/or decoding in a data processing system. | 09-19-2013 |
20130254619 | Systems and Methods for Mis-Correction Correction in a Data Processing System - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for mis-correction detection and correction in a data processing system. | 09-26-2013 |
20130262788 | Systems and Methods for External Priority Controlled Data Transfer - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. As an example a system is discussed that includes a data transfer controller circuit operable to provide a read request to a storage device. The read request indicates a data set to be provided from the storage device and a processing priority of at least a portion of the data set. | 10-03-2013 |
20130263147 | Systems and Methods for Speculative Read Based Data Processing Priority - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 10-03-2013 |
20130275717 | Multi-Tier Data Processing - Various embodiments of the present invention provide systems and methods for a multi-tier data processing system. For example, a data processing system is disclosed that includes an input operable to receive data to be processed, a first data processor operable to process at least some of the data, a second data processor operable to process a portion of the data not processed by the first data processor, wherein the first data processor has a higher throughput than the second data processor, and an output operable to yield processed data from the first data processor and the second data processor. | 10-17-2013 |
20130275827 | Multi-Section Non-Binary LDPC Decoder - Various embodiments of the present invention provide systems and methods for decoding codewords in a multi-section non-binary LDPC decoder. For example, an LDPC decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node messages and to generate variable node to check node messages, and a check node processor operable to process the variable node to check node messages in groups across each of a plurality of sections of an H matrix and to generate the check node to variable node messages. | 10-17-2013 |
20130275986 | Data Processing System with Out of Order Transfer - Various embodiments of the present inventions provide systems and methods for data processing with out of order transfer. For example, a data processing system is disclosed that includes a data processor operable to process input blocks of data and to yield corresponding processed output blocks of data, wherein the processed output blocks of data are output from the data processor in an order in which their processing is completed, and a scheduler operable to receive processing priority requests for the input blocks of data and to assign processing resources in the data processor according to the priority requests. | 10-17-2013 |
20130290798 | Systems and Methods for Short Media Defect Detection Using Non-Binary Coded Information - Various embodiments of the present invention provide systems and methods for media defect detection. | 10-31-2013 |
20130290806 | Systems and Methods for Data Decoder State Preservation During Extended Delay Processing - The present invention is related to systems and methods for maintaining additional processing information during extended delay processing. | 10-31-2013 |
20130297983 | Data Processing System with Failure Recovery - Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors. | 11-07-2013 |
20130308221 | Systems and Methods for Symbol Re-Grouping Decoding Processing - The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing. | 11-21-2013 |
20130322578 | Systems and Methods for Data Processing Including EET Feedback - The present invention is related to systems and methods for data processing system characterization. | 12-05-2013 |
20130326302 | Error Injection for LDPC Retry Validation - The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation circuit in the data processing circuit is operable to inject errors in the data set to trigger the at least one retry feature. | 12-05-2013 |
20130326316 | Systems and Methods for Improved Data Detection Processing - The present invention is related to systems and methods for enhancing data detection in a data processing system. | 12-05-2013 |
20130332790 | LDPC Decision Driven Equalizer Adaptation - The present inventions are related to LDPC decision-driven equalizer adaptation. For example, a data processing apparatus is disclosed that includes an equalizer operable to yield equalized data, a low density parity check decoder operable to decode the equalized data to yield decoded data, and an equalizer adaptation circuit operable to adapt settings in the equalizer based in part on the decoded data. | 12-12-2013 |
20130332794 | Data Processing System with Retained Sector Reprocessing - Various embodiments of the present inventions are related to apparatuses and methods for data processing systems with retained sector reprocessing. For example, a data processing system is disclosed that includes a data processor operable to process blocks of data and to yield corresponding processed output blocks of data, and to retain the blocks of data for reprocessing when requested, and a scheduler operable to receive reprocessing requests for the retained blocks of data and to initiate a reprocessing operation in the data processor for the retained blocks of data. | 12-12-2013 |
20130335850 | Initialization for Decoder-Based Filter Calibration - Various embodiments of the present inventions are related to initialization of decoder-based filter calibration, and in particular to initially using either a detector output or unconverged data from the decoder to train filter coefficients in a noise predictive calibration engine until data sectors converge in the decoder and can be used to train filter coefficients. | 12-19-2013 |
20130339827 | Adaptive Calibration of Noise Predictive Finite Impulse Response Filter - Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold. | 12-19-2013 |
20130343495 | APPARATUS AND METHOD FOR BREAKING TRAPPING SETS - An error correction data processing apparatus includes a noise predictive calibration circuit operable to calibrate a first set of filter coefficients based on a first data set and a second set of filter coefficients based on a second data set, and includes a first noise predictive detector operable to receive the first set of filter coefficients. The apparatus further includes a decoder operable to perform a first global iteration with the first noise predictive detector and determine a violation check count value, and a second noise predictive detector operable to receive the second set of filter coefficients if the violation check count value is less than a predetermined value or receive the first set of filter coefficients if the violation check count value is greater than the predetermined value. | 12-26-2013 |
20140016220 | Systems and Methods for Hardware Assisted Write Pre-Compensation Enhancement - Various embodiments of the present invention provide systems and methods for calibrating write pre-compensation values. | 01-16-2014 |
20140032989 | Symbol Selective Scaling With Parity Forcing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing. | 01-30-2014 |
20140032998 | Systems and Methods for Improved Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. | 01-30-2014 |
20140032999 | Systems and Methods for Information Divergence Based Data Processing - The present inventions are related to systems and methods for information divergence based data processing. | 01-30-2014 |
20140035692 | OPTIMIZED MULTI-LEVEL FINITE STATE MACHINE WITH REDUNDANT DC NODES - A method and system for eliminating/suppressing long transition runs over a communications channel is disclosed. The method may include providing modulation coding based on a multi-level finite state machine (ML-FSM) having a periodic structure, the periodic structure being defined by a predetermined number of time frames. The ML-FSM may include a plurality of penalty-free edges for connecting nodes in one time frame to nodes at the same level in a subsequent time frame and a plurality of penalty edges for connecting nodes in one time frame to nodes at an upper level in the subsequent time frame. The method may further include utilizing the ML-FSM based modulation coding to facilitate data transmission over the communications channel. | 02-06-2014 |
20140040682 | METHOD AND SYSTEM FOR SYMBOL ERROR RATE ESTIMATION AND SECTOR QUALITY MEASUREMENT - A probabilistic approach of symbol error estimation is disclosed. The probabilistic approach of symbol error estimation reflects the number of symbol errors more precisely than the number of unsatisfied checks. The more precise quality metric calculated in accordance with the present disclosure allows a codec system to achieve a better overall performance. In addition, many other features that previously depend on the number of unsatisfied checks as the sector quality metric may also benefit by adopting the more precise quality metric. | 02-06-2014 |
20140053037 | Multi-Level LDPC Layered Decoder With Out-Of-Order Processing - Various embodiments of the present invention are related to methods and apparatuses for decoding data, and more particularly to methods and apparatuses for multi-level layered LDPC decoding with out-of-order processing. | 02-20-2014 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 02-27-2014 |
20140063636 | Systems and Methods for Conditional Positive Feedback Data Decoding - The present inventions are related to systems and methods for information data processing included selective decoder message determination. | 03-06-2014 |
20140068372 | Systems and Methods for Local Iteration Randomization in a Data Decoder - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for local iteration randomization in a data decoder circuit. | 03-06-2014 |
20140068394 | SYSTEMS AND METHODS FOR SECTOR QUALITY DETERMINATION IN A DATA PROCESSING SYSTEM - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data set quality determination. | 03-06-2014 |
20140075261 | OPTIMIZED MECHANISM TO SIMPLIFY THE CIRCULANT SHIFTER AND THE P/Q KICK OUT FOR LAYERED LDPC DECODER - A layered LDPC decoder architecture includes a single MUX and a single shifter element for processing an optimized LDPC parity check matrix. The optimized LDPC parity check matrix may be a K×L sub-matrix having zero elements, non-zero elements defined by a circulant matrix or zero matrices, and identity matrixes. | 03-13-2014 |
20140075264 | CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING - A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword. | 03-13-2014 |
20140082448 | LDPC Decoder With Dynamic Graph Modification - The present inventions are related to systems and methods for an LDPC decoder with dynamic Tanner graph modification, and in particular, to a non-erasure channel LDPC decoder that implements a probabilistic approach to Tanner graph modification. | 03-20-2014 |
20140086298 | DATA-DEPENDENT EQUALIZER CIRCUIT - A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined NRZ condition for one or more of the noise prediction filters. | 03-27-2014 |
20140089757 | LDPC Decoder With Fractional Local Iterations - The present inventions are related to systems and methods for an LDPC decoder with fractional local iterations that may be used in a data processing system with an LDPC decoder and data detector to better balance processing times in the LDPC decoder and data detector. | 03-27-2014 |
20140095954 | MODIFIED TARGETED SYMBOL FLIPPING FOR NON-BINARY LDPC CODES - A LDPC decoder includes a processor for targeted symbol flipping of suspicious bits in a LDPC codeword with unsatisfied checks. All combinations of check indices and variable indices are compiled and correlated into a pool of targeted symbol flipping candidates and returned along with symbol indices to a process that uses such symbol indices to identify symbols to flip in order to break a trapping set. | 04-03-2014 |
20140101483 | Systems and Methods for Modified Quality Based Priority Scheduling During Iterative Data Processing - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 04-10-2014 |
20140101509 | Systems and Methods for Parallel Retry Processing During Iterative Data Processing - Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 04-10-2014 |
20140101510 | Low Density Parity Check Layer Decoder For Codes With Overlapped Circulants - The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants. | 04-10-2014 |
20140104720 | ENHANCED QUALITY-SORTING SCHEDULER - Aspects of the disclosure pertain to a read channel system and method for providing sector prioritization for promoting improved sector processing performance. The system and method, during processing of sectors of data, prioritize each of the sectors for further processing based upon: a global iteration index of each sector, trapping set characteristics of each sector and processing latency of each sector. | 04-17-2014 |
20140108880 | Systems and Methods for Enhanced Local Iteration Randomization in a Data Decoder - systems and methods for data processing particularly related local iteration randomization in a data decoding circuit. | 04-17-2014 |
20140111880 | MULTI-LEVEL RUN-LENGTH LIMITED FINITE STATE MACHINE FOR MAGNETIC RECORDING CHANNEL - A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure. | 04-24-2014 |
20140115407 | Systems and Methods for Short Media Defect Detection Using Multi-Iteration Soft Data Feedback - Various systems and methods for media defect detection. | 04-24-2014 |
20140115431 | Systems and Methods for Positive Feedback Short Media Defect Detection - Various systems and methods for media defect detection. | 04-24-2014 |
20140119113 | Threshold Acquisition and Adaption in NAND Flash Memory - A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration. | 05-01-2014 |
20140122923 | Sector Failure Prediction Method and Related System - A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the sector having the defined pattern and period. Once identified, the method uses a power management scheme to remove the sector prone to failure from further use by the memory system and displays to a user the details of the action taken. | 05-01-2014 |
20140122971 | LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System - A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue. | 05-01-2014 |
20140129603 | Systems and Methods for Partially Conditioned Noise Predictive Equalization - Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits. | 05-08-2014 |
20140129890 | Test Pattern Optimization for LDPC Based Flawscan - A method for producing a LDPC encoded test pattern for media in a LDPC based drive system includes adding error detection code data to a predominantly zero bit test pattern and adding additional zero bits to produce a test pattern of a desirable length. The test pattern may then be scrambled to produce a desirable flaw detection test pattern. The flaw detection test pattern may then be encoding with an LDPC code, or other error correction code with minimal disturbance to the run length constraints of the data pattern, and written to a storage medium. | 05-08-2014 |
20140129905 | Flexible Low Density Parity Check Code Seed - Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed. | 05-08-2014 |
20140139943 | READ CHANNEL ERROR CORRECTION USING MULTIPLE CALIBRATORS - Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel data signal, to determine second hard decision information regarding the error corrected read channel data signal using the calibrated second set of filters, and to decode the second hard decision information. The first set of filters and the second set of filters are calibrated in respective first and second calibrators. | 05-22-2014 |
20140143289 | Constrained System Endec - Various embodiments of the present invention provide apparatuses and methods for encoding and decoding data for constrained systems with reduced or eliminated need for hardware and time intensive arithmetic operations such as multiplication and division. | 05-22-2014 |
20140143628 | Low Density Parity Check Decoder With Flexible Saturation - Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values. | 05-22-2014 |
20140164866 | Low Density Parity Check Decoder With Miscorrection Handling - A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected. | 06-12-2014 |
20140168811 | Irregular Low Density Parity Check Decoder With Low Syndrome Error Handling - A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome. | 06-19-2014 |
20140172934 | Systems and Methods for Data Retry Using Averaging Process - Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. | 06-19-2014 |
20140173385 | Low Density Parity Check Decoder With Dynamic Scaling - A data processing system is disclosed including a low density parity check decoder with a variable node processor, a check node processor and a scaler circuit. The low density parity check decoder is operable to scale soft information with a scaling factor in the scaler circuit while iteratively generating and processing check node to variable node messages in the variable node processor and variable node to check node messages in the check node processor between a plurality of check nodes and variable nodes. The scaling factor is derived from a distribution of possible values in an input to the low density parity check decoder. | 06-19-2014 |
20140177082 | OVER-SAMPLED SIGNAL EQUALIZER - An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize an oversampled digital data signal to determine an equalized digital data signal, filter the equalized digital data signal, determine a hard decision and reliability of the filtered digital data signal, and decode the filtered digital data signal based at least in part on the hard decision and reliability. The oversampled digital data signal comprises a first set of sampled digital data and a corresponding second set of sampled digital data, each of the samples in the first set of sampled digital data being offset from a corresponding one of the sample in the second set of sampled digital data by a phase difference. | 06-26-2014 |
20140177087 | EQUALIZATION COMBINING OUTPUTS OF MULTIPLE COMPONENT FILTERS - An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output of the detector configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; and a multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer. The hard decision information is used to train the equalizer. | 06-26-2014 |
20140181570 | SIGNAL PROCESSING CIRCUITRY WITH FRONTEND AND BACKEND CIRCUITRY CONTROLLED BY SEPARATE CLOCKS - An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. | 06-26-2014 |
20140181624 | Majority-Tabular Post Processing of Quasi-Cyclic Low-Density Parity-Check Codes - A method for finding a valid codeword based on a near codeword trapping in a low-density parity-check decoding process includes identifying trapping set configurations and applying corrections to produce trapping sets with a limited number of invalid checks. Trapping set configurations are corrected in order to produce a trapping set in a table of trapping sets, the table associating each corrected trapping set with a valid codeword. | 06-26-2014 |
20140181625 | READ CHANNEL DATA SIGNAL DETECTION WITH REDUCED-STATE TRELLIS - An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to determine a first set of soft outputs, hard decisions and reliability indicators for a read channel data signal, to determine a second set of soft outputs, hard decisions and reliability indicators based at least in part on the first set of soft outputs, hard decisions and reliability indicators, and to perform an iterative decoding process to decode the read channel data signal based at least in part on the second set of soft outputs, hard decisions and reliability indicators. The first set of soft outputs, hard decisions and reliability indicators are used to determine a reduced-state trellis for determining the second set of soft outputs, hard decisions and reliability indicators. | 06-26-2014 |
20140185159 | SYNC MARK DETECTION USING BRANCH METRICS FROM DATA DETECTOR - Methods and apparatus are provided for detecting a sync mark in a storage system, such as a hard disk drive. A sync mark is detected in a storage system by obtaining one or more branch metrics from a data detector in the storage system; generating one or more sync mark metrics using the one or more branch metrics from the data detector; and identifying the sync mark based on the sync mark metrics. An input data set is optionally compared with a plurality of portions of a sync mark pattern to yield corresponding comparison values and the comparison values can be summed to obtain at least one result. A sync mark found signal is asserted based upon the at least one result. | 07-03-2014 |
20140201585 | State-Split Based Endec - Various embodiments of the present invention provide systems and methods for encoding and decoding data for constrained systems with state-split based encoders and decoders. | 07-17-2014 |
20140208180 | Systems and Methods for Reusing a Layered Decoder to Yield a Non-Layered Result - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 07-24-2014 |
20140211337 | Systems and Methods for Improved Short Media Defect Detection - Various embodiments of the present invention provide systems and methods for media defect detection. | 07-31-2014 |
20140237313 | Systems and Methods for Trapping Set Disruption - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding. | 08-21-2014 |
20140237314 | Systems and Methods for Skip Layer Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process. | 08-21-2014 |
20140237329 | Ratio-Adjustable Sync Mark Detection System - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system. | 08-21-2014 |
20140244926 | Dedicated Memory Structure for Sector Spreading Interleaving - The present disclosure is directed to a method for managing a memory. The method includes the step of receiving data, the data including a plurality of sectors. The method also includes the step of dividing each sector of the plurality of sectors into a plurality of data units. A further step of the method involves interleaving the plurality of data units to yield a plurality of interleaved data units. The method also includes the step of writing the plurality of interleaved data units to a disk. An additional step of the method is to de-spread the plurality of interleaved data units to yield at least one sector of the plurality of sectors. | 08-28-2014 |
20140268390 | SYSTEMS AND METHODS FOR TRANSITION BASED EQUALIZATION - Systems, methods, devices, circuits for transition based equalization. | 09-18-2014 |
20140268401 | Systems and Methods for P-Distance Based Priority Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing. | 09-18-2014 |
20140281787 | Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder - Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder. | 09-18-2014 |
20140281790 | Systems and Methods for Multi-Stage Encoding Of Concatenated Low Density Parity Check Codes - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes. | 09-18-2014 |
20140289582 | Systems and Methods for Reduced Constraint Code Data Processing - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 09-25-2014 |
20140362461 | Systems and Methods for Floating Variance Branch Metric Calculation - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data detection. | 12-11-2014 |
20140372828 | Systems and Methods for Hybrid Layer Data Decoding - The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding. | 12-18-2014 |
20150058693 | Systems and Methods for Enhanced Data Encoding and Decoding - Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. | 02-26-2015 |
20150062738 | Systems and Methods for Variable Sector Count Spreading and De-Spreading - Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information. | 03-05-2015 |
20150067685 | Systems and Methods for Multiple Sensor Noise Predictive Filtering - The present invention is related to systems and methods for branch metric calculation based on multiple data streams in a data processing circuit. | 03-05-2015 |
20150081626 | Systems and Methods for Recovered Data Stitching - Systems and method relating generally to data processing, and more particularly to systems and methods for combining recovered portions of a data set. | 03-19-2015 |