Patent application number | Description | Published |
20130191569 | MULTI-LANE HIGH-SPEED INTERFACES FOR HIGH SPEED SYNCHRONOUS SERIAL INTERFACE (HSI), AND RELATED SYSTEMS AND METHODS - Multi-lane high speed interfaces for a modified High Speed Synchronous Serial (HSI) system, and related systems methods are disclosed. In one embodiment, electronic device using a modified HSI protocol comprises a transmit communications interface. The transmit communications interface comprises a data path configured to carry data from the electronic device, a ready path configured to carry an HSI protocol compliant READY signal, and a flag path configured to carry an HSI protocol compliant FLAG signal indicative of repeated bit values of data carried on the data path. The transmit communications interface further comprises one or more additional data paths configured to carry additional data from the electronic device in parallel with the data carried by the data path such that the data path and the one or more additional data paths carry HSI protocol compliant data striped across the data path and the one or more additional data paths. | 07-25-2013 |
20140281283 | DUAL HOST EMBEDDED SHARED DEVICE CONTROLLER - Efficient techniques using a multi-port shared non-volatile memory are described that reduce latency in memory accesses from dedicated function specific processors, such as a modem control processor. The modem processor preempts a host processor that is accessing data from a multi-port shared non-volatile memory flash device allowing the modem processor to quickly access data in the flash device. The preemption process uses a doorbell interrupt initiated by a processor that seeks access and interrupts the processor being preempted. After preemption, the host processor may resume or restart the data access. Access control by the processors utilizes a hardware semaphore atomic control mechanism. Power control of the shared non-volatile memory modules includes at least one inactivity timer to indicate when a supply voltage to the shared non-volatile memory modules can be safely reduced or turned off. Power may be restarted by any of the processors sharing the memory, allowing fast access to the data. | 09-18-2014 |
20140310536 | STORAGE DEVICE ASSISTED INLINE ENCRYPTION AND DECRYPTION - Various features pertain to inline encryption and decryption. In one aspect, inline read/write operations are performed by configuring an off-chip storage device to provide parameters to facilitate inline encryption/decryption of data by a host storage controller of a system-on-a-chip (SoC.) The parameters provided by the storage device to the host storage controller include an identifier that is the same for read and write operations for a particular block of data but differs from one block of data to another. The host storage controller employs the parameters as initial vectors to generate encryption keys for use in encrypting/decrypting data. Exemplary read and write operations of the host storage controller and the off-chip storage device are described herein. Examples are also described wherein the parameters are obtained from host memory rather than from the storage device. | 10-16-2014 |
20150033071 | ROBUST HARDWARE/SOFTWARE ERROR RECOVERY SYSTEM - A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software. | 01-29-2015 |
20150033234 | PROVIDING QUEUE BARRIERS WHEN UNSUPPORTED BY AN I/O PROTOCOL OR TARGET DEVICE - A host controller is provided that unilaterally supports queue barrier functionality. The host controller may receive a first task marked with a queue barrier indicator. As a result, the host controller stalls transmission of the first task to a target device. Additionally, the host controller also stalls transmission of any task, occurring after the first task, to the target device. The host controller only sends the first task to the target device once an indication is received from the target device that all previously sent tasks have been processed. The host controller only sends any task, occurring after the first task, to the target device once an indication is received from the target device that the first task has been processed. | 01-29-2015 |
20150074294 | PROVIDING COMMAND QUEUING IN EMBEDDED MEMORIES - Providing command queuing in embedded memories is provided. In particular, aspects disclosed herein relate to a process through which a status of the queue is communicated to a host from a device. Aspects of the present disclosure use the command structure of the embedded Multi-Media Card (eMMC) standard, such that the host may determine a state of the queue in the device proximate a known end of an in-progress data transfer. In this manner, the host can select a task to commence after completion of a current data transfer while the current data transfer is still ongoing. | 03-12-2015 |
20150074338 | ASCERTAINING COMMAND COMPLETION IN FLASH MEMORIES - Ascertaining command completion in flash memories is disclosed. An exemplary aspect includes eliminating the software lock and the outstanding requests variable and replacing them with a transfer request completion register. The transfer request completion register may be mapped to the universal flash storage (UFS) Transfer Protocol (UTP) Transfer Request List (UTRL) slots. The controller of the host—a hardware component—may set the bit in the transfer request completion register on transfer request completion at the same time the doorbell register is cleared. After this bit has been read, the bit in the transfer request completion register is cleared. | 03-12-2015 |
20150143022 | REMOVABLE MEMORY CARD DISCRIMINATION SYSTEMS AND METHODS - Removable memory card discrimination systems and methods are disclosed. In particular, exemplary embodiments discriminate between secure digital (SD) cards and other removable memory cards that comply with the SD form factor, but support the Universal Flash Storage (UFS) protocol. That is, a host may have a receptacle that supports the SD card form factor and is configured to receive a device. In use, a removable memory card is inserted into the receptacle and, using an SD compliant interrogation signal, the host interrogates a common area on the card so inserted. The common area includes information related to capability descriptors of the card. An SD compliant card will respond with information such as capability descriptors about the SD protocol capabilities, while a UFS compliant card will respond with an indication that the card is UFS compliant. The host may then restart the communication with the card using the UFS protocol. | 05-21-2015 |
20150220475 | DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS - Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source. | 08-06-2015 |
Patent application number | Description | Published |
20100288404 | Highly-Filled, High-Viscosity Paste Charge, And Method And Device For Production Thereof - A highly-filled paste, and a method and device of de-aerating and injecting the paste, the paste including: (a) a solid filler; (b) an organic binder, and (c) a residual gas, wherein the paste contains at least 80 volume-% of the solid filler and has a viscosity exceeding 100 kilopascal·seconds, wherein the filler, binder, and residual gas are intimately mixed so as to form a substantially homogeneous paste, and wherein a composition of the solid filler, binder, and residual gas is selected such that the homogeneous paste has: an average density greater than 98.5% of a Theoretical Maximum Density (TMD). | 11-18-2010 |
20110209600 | Highly-Filled, High-Viscosity Paste Charge, And Method And Device For Production Thereof - A highly-filled paste, and a method and device of de-aerating and injecting the paste, the paste including: (a) a solid filler; (b) an organic binder, and (c) a residual gas, wherein the paste contains at least 80 volume-% of the solid filler and has a viscosity exceeding 100 kilopascal·seconds, wherein the filler, binder, and residual gas are intimately mixed so as to form a substantially homogeneous paste, and wherein a composition of the solid filler, binder, and residual gas is selected such that the homogeneous paste has: an average density greater than 98.5% of a Theoretical Maximum Density (TMD). | 09-01-2011 |
20110209805 | Highly-Filled, High-Viscosity Paste Charge, And Method And Device For Production Thereof - A highly-filled paste, and a method and device of de-aerating and injecting the paste, the paste including: (a) a solid filler; (b) an organic binder, and (c) a residual gas, wherein the paste contains at least 80 volume-% of the solid filler and has a viscosity exceeding 100 kilopascal·seconds, wherein the filler, binder, and residual gas are intimately mixed so as to form a substantially homogeneous paste, and wherein a composition of the solid filler, binder, and residual gas is selected such that the homogeneous paste has: an average density greater than 98.5% of a Theoretical Maximum Density (TMD). | 09-01-2011 |
Patent application number | Description | Published |
20100228650 | Apparatus and Method for Tracking Transaction Related Data - A method of tracking information in a multi-tier computerized environment, the method comprising: receiving an at least one packet; storing data associated with the at least one packet and with an at least one request or transaction associated with the at least one packet; parsing a byte stream generated from conversion of the at least one packet; detecting data associated with the at least one request or transaction related to the byte stream; matching a thread associated with the byte stream with the at least one request or transaction associated with the at least one packet according to predetermined fields within the byte stream, an apparatus for implementing the same and methods for determining resource consumption of requests or transactions. | 09-09-2010 |
20100287416 | METHOD AND APPARATUS FOR EVENT DIAGNOSIS IN A COMPUTERIZED SYSTEM - A method and apparatus for diagnosis of a computerized system, the method comprising the steps of collecting one or more events; transforming the events to events based time series, said events based time series having intervals; determining which resources of the computerized system are being consumed by which events, for a first predetermined time interval; and determining a function between the events based time series and one or more measurable attributes of one or more resources that were consumed by the events for a second predetermined time interval. | 11-11-2010 |
20110035493 | APPARATUS AND METHOD FOR TRACKING REQUESTS IN A MULTI THREADED MULTI TIER COMPUTERIZED ENVIORONMENT - The subject matter discloses a method and apparatus for associating requests and responses in a multi-tier computerized environment, comprising for each tier, detecting incoming and outgoing data flow; sending the detected data to a processing module; for each two neighboring tiers, comparing incoming data of one tier and outgoing data of the other tier; associating incoming requests of one tier to outgoing requests of the other tier. The association may use an ad-hoc ID. The subject matter also discloses a computerized apparatus detecting data and sending the data to a central storage outside the multi-tier environment when the data is used to match requests and responses. Another object of the subject matter is a method for associating an incoming request and outgoing response or outgoing requests in a multi-threaded computerized environment. | 02-10-2011 |
20140156842 | METHOD AND APPARATUS FOR ASSEMBLING ELEMENTS OF DATA TRANSACTIONS - A computerized method for organizing representations of transactions in a multi-node system, comprising randomly selecting by each computer of a plurality of computers a message in a repository of messages of transactions accessible to the plurality of computers, and selecting in the repository by each computer of the plurality of computers further messages belonging to the transaction the randomly selected message belongs to, and assembling the selected messages to a representation of the transaction the randomly selected message belongs to, and an apparatus for the same. | 06-05-2014 |
Patent application number | Description | Published |
20090024557 | Clause and Proof Tightening - A computer-implemented method for verification of a target system includes defining a formula describing the target system, the formula including clauses, which include variables and which express constraints on states of the target system. The formula is processed so as to derive, using the clauses, a proof relating to a property of the target system. After deriving the proof, a variable that has a constant value is identified in the proof. The number of the variables in the proof is reduced using the identified variable, thereby producing a tightened expression, which is applied in making a determination of whether the target system satisfies the formula. | 01-22-2009 |
20090064064 | Device, System and Method for Formal Verification - Device, system and method of efficient automata-based implementation of liveness properties for formal verification. A system according to embodiments of the invention includes a property transformation module to receive an assume verification directive on a liveness property in a property specification language, and to translate the property a fairness statement that uses a deterministic automaton. The deterministic automaton is exponential in the size of the input property. The assume verification directive may be transformed into a strong suffix implication in the property specification language. | 03-05-2009 |
20090248601 | EXPLOITING DOUBLE RESOLUTIONS FOR PROOF OPTIMIZATIONS - A method for simplifying resolution proofs in DAG format where each leaf node represents a clause and each internal node represents a resolution between its children includes representing a SAT proof as a stripped proof, analyzing pivots to identify redundant resolutions, and constructing a simplified proof without the redundant resolutions. | 10-01-2009 |
20090307204 | ADAPTIVE APPLICATION OF SAT SOLVING TECHNIQUES - A computer-implemented method for solving a satisfiability (SAT) problem includes defining a formula, including variables, which refers to properties of a target system. Using a chosen search strategy, a search process is performed over possible value assignments of the variables for a satisfying assignment that satisfies the formula. A performance metric estimating an effectiveness of the search process is periodically evaluated during the search process. The strategy of the search process is modified responsively to the evaluated performance metric. The method determines, using the search process, whether the formula is satisfiable on the target system. | 12-10-2009 |
20100218150 | Logic Design Verification Techniques for Liveness Checking - A technique for verification of a logic design (embodied in a netlist) using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of the netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop. | 08-26-2010 |
20110178970 | TEMPLATE CLAUSES BASED SAT TECHNIQUES - A CNF formula comprises at least one template clause representing a set of concrete clauses, each associated with a different temporal shift. The template clause is utilized by a SAT solver in determining satisfiability of the CNF formula. The template clause may be utilized to reduce amount of storage resources required for performing the satisfiability analysis. The template clause may in some cases increase feasibility of determining satisfiability. The template clause may in some cases reduce required time to determine satisfiability. The template clause may be utilized in incremental SAT solving to reuse deduced relations between literals that are applicable to additional cycles, such as invariants originating from a transition relation of a model. | 07-21-2011 |
20110213605 | Satisfiability (SAT) Based Bounded Model Checkers - Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains. | 09-01-2011 |
20110295789 | Context-Sensitive Dynamic Bloat Detection System - Methods and apparatus are provided for a context-sensitive dynamic bloat detection system. A profiling tool is disclosed that selects an appropriate collection implementation for a given application. The disclosed profiling tool uses semantic profiling together with a set of collection selection rules to make an informed choice. A collection implementation, such as an abstract data entity, is selected for a given program by obtaining collection usage statistics from the program. The collection implementation is selected based on the collection usage statistics using a set of collection selection rules. The collection implementation is one of a plurality of interchangeable collection implementations having a substantially similar logical behavior for substantially all collection types. The collection usage statistics indicate how the collection implementation is used in the given program. One or more suggestions can be generated for improving the collection allocated at a particular allocation context. | 12-01-2011 |
20120060064 | SOFT ERROR VERIFICATION IN HARDWARE DESIGNS - Soft error detection is performed by computation of states based on formal methods and by simulating a synthesized target identification logic together with the design. Soft errors may be simulated in response to detecting that a simulated state of the design is comprised by the states. A BDD representation of the design may be utilized to determine the states. A Boolean satisfiability problem may be defined and solved using an all-SAT solver in order to determine the states. | 03-08-2012 |
20130159241 | TEMPLATE CLAUSES BASED SAT TECHNIQUES - A CNF formula comprises at least one template clause representing a set of concrete clauses, each associated with a different temporal shift. The template clause is utilized by a SAT solver in determining satisfiability of the CNF formula. The template clause may be utilized to reduce amount of storage resources required for performing the satisfiability analysis. The template clause may in some cases increase feasibility of determining satisfiability. The template clause may in some cases reduce required time to determine satisfiability. The template clause may be utilized in incremental SAT solving to reuse deduced relations between literals that are applicable to additional cycles, such as invariants originating from a transition relation of a model. | 06-20-2013 |
Patent application number | Description | Published |
20100228921 | CACHE HIT MANAGEMENT - A system and method for cache hit management. | 09-09-2010 |
20110279831 | REDUCING THE VISIBILITY OF COLOR CHANGES CAUSED BY COLOR PLANE REGISTRATION VARIATIONS IN HALFTONE COLOR PRINTING - A set of screens is provided for use in printing respective color separations in a halftone color printing process. This set of screens comprises at least two clustered-dot screens and the frequency and angle parameter values of the screens is such that the lowest frequency moiré produced by any combination of at least two frequency components, taken from the group comprising the first and second screen harmonics, for which the sum of the harmonic orders of the frequency components in the combination is less than a predetermined value, is of a sufficiently high frequency as to be substantially unperceivable to the human visual system; other moirés are also substantially unperceivable to the human visual system. The lowest frequency moiré serves to reduce the visibility of color changes caused by color plane registration variations. A printing system and method employing the screen set are also provided. | 11-17-2011 |
20120182344 | CLUSTERED HALFTONE GENERATION - A method for generating a clustered halftone representation of a continuous-tone image for printing includes applying a search technique. In the search technique, evaluation of a similarity between an initial halftone and the continuous-tone image includes application of an initialization filter to an initial error image that represents a difference between the initial halftone and the continuous-tone image. Evaluation of a similarity between each updated halftone, formed by modifying a previously-evaluated halftone, and the continuous-tone image includes application of an update filter that is different from the initialization filter to an updated error image that represents a difference between the updated halftone and the continuous-tone image. Relating computer program product and data processing system are also disclosed. | 07-19-2012 |
20120182587 | METHOD AND SYSTEM FOR ENHANCING A DIGITAL HALFTONE REPRESENTATION FOR PRINTING - A method for predicting an appearance of a rendering by a printer of a digital halftone representation of a continuous-tone image includes calculating a predicted absorptance value of a dot of a rendered halftone of the digital halftone representation. The dot corresponds to a pixel of the digital halftone representation. The predicted absorptance value is based on a configuration of pixel values of pixels in an immediate neighborhood of the pixel, and on a weighted contribution of a pixel value of each pixel in an outer neighborhood of the pixel. The method may be incorporated into a halftoning technique. Relating computer program product and data processing system are also disclosed. | 07-19-2012 |
20120188611 | COLOR SCREEN SETS - A method for designing a screen set for color halftoning includes selecting a screen set that includes at least two screens. The screens are applied to a uniform color image so as to form a set of corresponding colorant halftones. The colorant halftones are superposed to form a color halftone. A spatial frequency spectrum of the color halftone is calculated. Maxima of the spatial frequency spectrum that occur at two effective frequencies are identified, the two effective frequencies being located in two adjacent quadrants of a complex spatial frequency space. A magnitude of each effective frequency is compared with a predetermined frequency magnitude. The screen set is accepted for future application for color halftoning only if both effective frequency magnitudes are greater than the predetermined frequency magnitude. Relating computer program product and data processing system are also disclosed. | 07-26-2012 |
20130135689 | AUTOMATIC DETECTION OF CORNERS OF A SCANNED DOCUMENT - A method includes obtaining an image of a document against a background. A bounding box that bounds a region of the image that is distinguishable from the background is found. Coordinates of a plurality of points of the distinguishable region are found, each point being a point of the distinguishable region that is closest to each corner of the bounding box. The document is identified within the image as a region of the image whose corners are defined by the found coordinates. | 05-30-2013 |
20140132694 | SECURITY IMAGE PRINTING - Printing with a single colorant a security feature imperceptible to the naked eye. For a digital security image having a first region formed by a first pattern of binary pixels and a second region formed by a different second pattern of binary pixels, the first and second patterns are printed with the single colorant. A darker one of the first and second printed patterns is determined. The security image is printed with the single colorant, the region corresponding to the darker printed pattern printed at a reduced gray level such that the printed first and second regions appear substantially indistinguishable to the naked eye. | 05-15-2014 |