Patent application number | Description | Published |
20100084726 | Wafer level packaging image sensor module having lens actuator and method of manfacturing the same - Disclosed herein is a wafer level packaging image sensor module, including a wafer including an image sensor, a circuit portion and a lower electrode on one side thereof, a lens actuator disposed on the lower electrode and made of electroactive polymer, an upper electrode disposed on the lens actuator, and a lens unit disposed on the upper electrode to allow light to be transmitted to the image sensor therethrough. The wafer level packaging image sensor module includes the lens actuator made of electroactive polymer, and thus it enables realization of the autofocusing of the wafer level packaging image sensor module. | 04-08-2010 |
20100187002 | METHOD OF ATTACHING DIE USING SELF-ASSEMBLING MONOLAYER AND PACKAGE SUBSTRATE INCLUDING DIE ATTACHED THERETO USING SELF-ASSEMBLING MONOLAYER - Disclosed herein are a method of attaching a die using a self-assembling monolayer and a package substrate including a die attached thereto using a self-assembling monolayer. A first self-assembling monolayer formed on a die and a second self-assembling monolayer formed on a substrate are provided with the same hydrophilic or hydrophobic functional group, so that the die is attached to the substrate using an attractive force acting between the first and second self-assembling monolayers. An accuracy of alignment between the die and the substrate can be improved by the simple solution. | 07-29-2010 |
20110037145 | WAFER LEVEL PACKAGE HAVING CYLINDRICAL CAPACITOR AND METHOD OF FABRICATING THE SAME - Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided. | 02-17-2011 |
20110109339 | APPARATUS AND METHOD FOR INSPECTING CIRCUIT OF SUBSTRATE - Disclosed herein is an apparatus and method for inspecting a circuit of a substrate. The apparatus includes a pin probe coming into contact with a first end of an electrode formed on a first side of a substrate, a voltage source for applying a voltage to the pin probe, a film disposed at a second end of the electrode formed on a second side of the substrate, a dielectric fluid sealed in the film, and an electronic ink dispersed in the dielectric fluid, and charged with electricity to flow when the electrode is electrified. The present invention is advantageous in that whether an electrode has been electrified is measured using charged electronic ink, so that the use of a pin probe is limited to one side of a substrate, thus reducing cost required for the entire inspection. | 05-12-2011 |
20110115516 | APPARATUS AND METHOD FOR INSPECTING DEFECTS IN CIRCUIT PATTERN OF SUBSTRATE - Disclosed herein is an apparatus and method for inspecting defects in the circuit pattern of a substrate. The apparatus for inspecting defects in a circuit pattern of a substrate includes a pin probe configured to input a voltage while coming into contact with an inspection target circuit pattern of a substrate. A capacitor sensor is provided with a membrane electrode which is opposite a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner, and is configured to detect both capacitance and capacitance variation, generated due to displacement of the membrane electrode attributable to electrostatic attractive force acting from the connection circuit pattern on the membrane electrode. A capacitance measurement unit is connected to the capacitor sensor and is configured to measure capacitance attributable to the displacement of the membrane electrode, which is input from the capacitor sensor. | 05-19-2011 |
20110116084 | METHOD OF INSPECTING DEFECTS IN CIRCUIT PATTERN OF SUBSTRATE - Disclosed herein is a method of inspecting defects in a circuit pattern of a substrate. At least one laser beam radiation unit for radiating a laser beam onto an inspection target circuit pattern of a substrate in a non-contact manner is prepared. A probe beam radiation unit for radiating a probe beam onto a connection circuit pattern to be electrically connected to the inspection target circuit pattern in a non-contact manner is prepared. The laser beam is radiated onto the inspection target circuit pattern using the laser beam radiation unit. The probe beam is radiated onto the connection circuit pattern using the probe beam radiation unit, thus measuring information about whether the probe beam is diffracted, and a diffraction angle. Accordingly, the method can solve problems such as erroneous measurements caused by contact pressure and can reduce the time required for measurements. | 05-19-2011 |
20110128011 | APPARATUS AND METHOD FOR INSPECTING DEFECTS IN CIRCUIT PATTERN - Disclosed herein is an apparatus and method for inspecting defects in a circuit pattern. In the inspection apparatus and method, a laser beam is radiated by a laser unit onto a first end of a circuit pattern, and variation in impedance of a capacitor sensor disposed at a second end of the circuit pattern is measured, thus measuring the open/short circuits of the circuit pattern. | 06-02-2011 |
20130147014 | Wafer Level Package Having Cylindrical Capacitor and Method Of Fabrication The Same - Disclosed is a wafer level package having a cylindrical capacitor, which is capable of increasing electrostatic capacity thanks to the use of a cylindrical capacitor structure and which includes a wafer chip having a bonding pad formed thereon and an insulating layer formed thereon and exposing the bonding pad, a redistribution layer connected to the bonding pad and extending to one side of the insulating layer, a cylindrical outer electrode connected to the redistribution layer and having a center opening therein, a cylindrical inner electrode formed in the center opening of the outer electrode so as to be separated from the outer electrode, a dielectric layer formed between the outer electrode and the inner electrode, and a resin sealing portion formed on the insulating layer to cover the redistribution layer, the inner electrode, the outer electrode and the dielectric layer and having a first recess for exposing an upper surface of the inner electrode. A method of fabricating the wafer level package having a cylindrical capacitor is also provided. | 06-13-2013 |