Patent application number | Description | Published |
20100258861 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-14-2010 |
20120025327 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode. | 02-02-2012 |
20120261748 | SEMICONDUCTOR DEVICE WITH RECESS GATE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer. | 10-18-2012 |
20130105901 | SEMICONDUCTOR DEVICE WITH METAL GATE ELECTRODE AND HIGH-K DIELECTRIC MATERIAL AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
20130105905 | SEMICONDUCTOR DEVICE WITH METAL GATE AND HIGH-K DIELECTRIC LAYER, CMOS INTEGRATED CIRCUIT, AND METHOD FOR FABRICATING THE SAME | 05-02-2013 |
20130161710 | SEMICONDUCTOR DEVICE HAVING BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer. | 06-27-2013 |
20130240957 | METHOD OF FORMING GATE DIELECTRIC LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process. | 09-19-2013 |
20130244394 | METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO - A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer. | 09-19-2013 |
20140004679 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140162448 | SEMICONDUCTOR DEVICE WITH METAL GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode. | 06-12-2014 |
20140183649 | SEMICONDUCTOR DEVICE HAVING METAL GATE AND HIGH-K DIELECTRIC LAYER AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an N-channel transistor configured to have a first gate dielectric layer, a first metal containing gate electrode and a dipole forming layer, wherein the first metal containing gate electrode is formed on the first gate dielectric layer, and the dipole forming layer is formed on an interface of the first gate dielectric layer and the first metal containing gate electrode, and a P-channel transistor configured to have a channel region, a second gate dielectric layer and a second metal containing gate electrode, wherein the channel region has threshold voltage adjusting species, the second gate dielectric layer is formed on the channel region, and the second metal containing gate electrode has effective work function adjusting species of the second gate dielectric layer. | 07-03-2014 |
20140183651 | SEMICONDUCTOR DEVICE WITH METAL GATE AND HIGH-K MATERIALS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including first and second regions. A first gate stack structure containing a first effective work function adjust species is formed over the first region and a second gate stack structure containing a second effective work function adjust species is formed over the second region A channel region is formed under the first gate stack structure and contains a threshold voltage adjust species. | 07-03-2014 |
20140187030 | SEMICONDUCTOR DEVICE WITH DUAL WORK FUNCTION GATE STACKS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer. | 07-03-2014 |
20140203337 | METHOD OF FORMING GATE DIELECTRIC LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes ion-implanting germanium into a monocrystalline silicon-containing substrate; forming a gate oxide layer over a surface of the monocrystalline silicon-containing substrate and forming, under the gate oxide layer, a germanium-rich region in which the germanium is concentrated, by performing a plasma oxidation process; and crystallizing the germanium-rich region by performing an annealing process. | 07-24-2014 |