Patent application number | Description | Published |
20080219043 | Word Line Transistor Strength Control for Read and Write in Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for controlling word line voltage at a word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the word line transistor for write operations. A second voltage, which is less than the first voltage, can be supplied to the word line transistor during read operations. | 09-11-2008 |
20080219044 | Read Disturb Reduction Circuit for Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for reducing read disturbances in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A resistive element can be used during the read operation to control the read current and control read disturbances. An isolation element can be used to isolate the resistive element from the circuit during write operations. | 09-11-2008 |
20080238475 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 10-02-2008 |
20080247222 | Spin Transfer Torque Magnetoresistive Random Access Memory and Design Methods - Systems, circuits and methods for determining read and write voltages for a given word line transistor in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A first voltage can be supplied to the write operations so that the write operations occur in the saturation region of the word line transistor. A second voltage, which is less than the first voltage, can be supplied for read operations so that the read operations occur in the linear region of the word line transistor. | 10-09-2008 |
20090103354 | Ground Level Precharge Bit Line Scheme for Read Operation in Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for read operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A plurality of bit cells, each coupled to one of a plurality of bit lines, word lines and source lines are provided. A plurality of precharge transistors corresponding to one of the plurality of bit lines are configured to discharge the bit lines to ground prior to a read operation. | 04-23-2009 |
20090130779 | Method of Forming a Magnetic Tunnel Junction Structure - In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) structure including a conductive layer on a substrate. The method also includes depositing a sacrificial layer on the conductive layer before depositing a patterning film layer. | 05-21-2009 |
20090161422 | Magnetic Tunnel Junction Device with Separate Read and Write Paths - In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path. | 06-25-2009 |
20090174015 | Memory Cell and Method of Forming a Magnetic Tunnel Junction (MTJ) of a Memory Cell - A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane. | 07-09-2009 |
20090243009 | Magnetic Tunnel Junction Cell Including Multiple Vertical Magnetic Domains - Magnetic tunnel junction cell including multiple vertical domains. In an embodiment, a magnetic tunnel junction (MTJ) structure is disclosed. The MTJ structure includes an MTJ cell. The MTJ cell includes multiple vertical side walls. Each of the multiple vertical side walls defines a unique vertical magnetic domain. Each of the unique vertical magnetic domains is adapted to store a digital value. | 10-01-2009 |
20090261433 | One-Mask MTJ Integration for STT MRAM - A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit. | 10-22-2009 |
20090261434 | STT MRAM Magnetic Tunnel Junction Architecture and Integration - A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) in a semiconductor back-end-of-line (BEOL) process flow includes a first metal interconnect for communicating with at least one control device and a first electrode for coupling to the first metal interconnect through a via formed in a dielectric passivation barrier using a first mask. The device also includes an MTJ stack for storing data coupled to the first electrode, a portion of the MTJ stack having lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a same lateral dimension as defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second metal interconnect is coupled to the second electrode and at least one other control device. | 10-22-2009 |
20090261437 | Two Mask MTJ Integration For STT MRAM - A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization. | 10-22-2009 |
20090265678 | System and Method of Resistance Based Memory Circuit Parameter Adjustment - Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter. | 10-22-2009 |
20090290406 | Low loading pad design for STT MRAM or other short pulse signal transmission - A low loading pad for a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The low loading pad includes a plurality of hollow-shaped lower metal layers and a top metal layer formed on an uppermost layer of the plurality of hollow-shaped lower metal layers. | 11-26-2009 |
20090290409 | Pad design with buffers for STT-MRAM or other short pulse signal transmission - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line. | 11-26-2009 |
20090321859 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, the method includes depositing a cap layer on a magnetic tunnel junction (MTJ) structure, depositing a first spin-on material layer over the cap layer, and etching the first spin-on material layer and at least a portion of the cap layer. | 12-31-2009 |
20090323404 | Write Operation for Spin Transfer Torque Magnetoresistive Random Access Memory with Reduced Bit Cell Size - Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation. | 12-31-2009 |
20090323405 | Controlled Value Reference Signal of Resistance Based Memory Circuit - Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell. | 12-31-2009 |
20090323410 | System and Method to Fabricate Magnetic Random Access Memory - A system and method to fabricate magnetic random access memory is disclosed. In a particular embodiment, a method of aligning a magnetic film during deposition is disclosed. The method includes applying a first magnetic field along a first direction in a region in which a substrate resides during a deposition of a first magnetic material onto the substrate. The method further includes applying a second magnetic field along a second direction in the region during the deposition of the first magnetic material onto the substrate. | 12-31-2009 |
20090327983 | Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology - A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component. | 12-31-2009 |
20100045326 | THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS - The invention, in one aspect, provides a semiconductor device ( | 02-25-2010 |
20100057411 | PREDICTIVE MODELING OF CONTACT AND VIA MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY - A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via. | 03-04-2010 |
20100072566 | Magnetic Element Utilizing Protective Sidewall Passivation - Exemplary embodiments of the invention are directed to magnetic elements including a passivation layer for isolation from other on-chip elements. One embodiment is directed to an apparatus comprising a magnetic tunnel junction (MTJ) element. The MTJ element comprises: a first ferromagnetic layer; a second ferromagnetic layer; an insulating layer disposed between the first and second ferromagnetic layers; and an MTJ passivation layer forming protective sidewalls disposed adjacent to the first ferromagnetic layer, the second ferromagnetic layer, and the insulating layer. | 03-25-2010 |
20100074092 | Reducing Spin Pumping Induced Damping of a Free Layer of a Memory Device - A system and method of reducing spin pumping induced damping of a free layer of a memory device is disclosed. The memory device includes an anti-ferromagnetic material (AFM) pinning layer in contact with a bit line access electrode. The memory device also includes a pinned layer in contact with the AFM pinning layer, a tunnel barrier layer in contact with the pinned layer, and a free layer in contact with the tunnel barrier layer. The memory device includes a spin torque enhancing layer in contact with the free layer and in contact with an access transistor electrode. The spin torque enhancing layer is configured to substantially reduce spin pumping induced damping of the free layer. | 03-25-2010 |
20100077244 | LOW POWER ELECTRONIC SYSTEM ARCHITECTURE USING NON-VOLATILE MAGNETIC MEMORY - A computing system includes at least one functional unit and a magnetic random access memory (MRAM) block coupled to the at least one functional unit. The MRAM block is configured to store a functional state of the at least one functional unit during a power down state of the at least one functional unit. | 03-25-2010 |
20100102404 | Magnetic Tunnel Junction and Method of Fabrication - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal. | 04-29-2010 |
20100110775 | Word Line Voltage Control in STT-MRAM - Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage. | 05-06-2010 |
20100110776 | Data Protection Scheme during Power-Up in Spin Transfer Torque Magnetoresistive Random Access Memory - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) array including a plurality of bit cells, a power-up controller, and a first plurality of precharge transistors is disclosed. The plurality of bit cells are each coupled to one of a plurality of bit lines and word lines. The power-up controller is configured to provide a power-up control signal to control the voltage level of at least one of the bit lines or the word lines during power-up. The first plurality of precharge transistors are respectively coupled to at least one of the plurality of bit lines or the plurality of word lines, each precharge transistor being configured to discharge a corresponding bit line or word line to a desired voltage level based on the power-up control signal. | 05-06-2010 |
20100142260 | Data Integrity Preservation In Spin Transfer Torque Magnetoresistive Random Access Memory - Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. A write-back circuit configured to detect a read value of the bit cell and is configured to write back the read value to the bit cell after a read operation. | 06-10-2010 |
20100157654 | Balancing A Signal Margin Of A Resistance Based Memory Circuit - A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value. | 06-24-2010 |
20100176471 | Magnetic Element With Storage Layer Materials - According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers. | 07-15-2010 |
20100193888 | Magnetic Tunnel Junction (MTJ) Storage Element and Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) Cells Having an MJT - A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, a pinned layer adjacent to the bottom electrode layer, a dielectric layer encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier adjacent to the pinned layer, a free layer adjacent to the tunneling barrier, and a top electrode adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell. | 08-05-2010 |
20100194431 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 08-05-2010 |
20100195376 | BIT LINE VOLTAGE CONTROL IN SPIN TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY - A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) and associated read operations are disclosed. A bit cell includes a magnetic tunnel junction (MTJ) and a word line transistor, the bit cell being coupled to a bit line and a source line. A clamping circuit is coupled to the bit line and is configured to clamp the bit line voltage to a desired voltage level during a read operation of the STT-MRAM to prevent the bit line voltage from exceeding the desired voltage level. The desired voltage level is less than a write voltage threshold associated with a write operation of the STT-MRAM. | 08-05-2010 |
20100207221 | Magnetic Random Access Memory - A device includes a magnetic tunnel junction (MTJ) structure and a cap layer in contact with the MTJ structure. The device also includes a spin-on material layer in contact with a sidewall portion of the cap layer and a conducting layer in contact with at least the spin-on material layer and a portion of the MTJ structure. The cap layer has been etched to expose a portion of an electrode contact layer of the MTJ structure. The conducting layer is in electrical contact with the exposed portion of the electrode contact layer of the MTJ structure. | 08-19-2010 |
20100219491 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 09-02-2010 |
20100220516 | Reducing Source Loading Effect in Spin Torque Transfer Magnetoresisitive Random Access Memory (STT-MRAM) - Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio. | 09-02-2010 |
20100225435 | Magnetic Film Enhanced Inductor - An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film. | 09-09-2010 |
20100258887 | Magnetic Tunnel Junction (MTJ) and Methods, and Magnetic Random Access Memory (MRAM) Employing Same - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 10-14-2010 |
20100289098 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis. | 11-18-2010 |
20100302843 | Spin Transfer Torque - Magnetic Tunnel Junction Device and Method of Operation - A method is disclosed that includes controlling current flow direction for current sent over a source line or a bit line of a magnetic memory device. A current generated magnetic field assists switching of a direction of a magnetic field of a free layer of a magnetic element within a spin transfer torque magnetic tunnel junction (STT-MTJ) device. | 12-02-2010 |
20100315863 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 12-16-2010 |
20100321976 | Split Path Sensing Circuit - A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including a second load transistor. The second path is coupled to a third split path including a third load transistor and to a fourth split path including a fourth load transistor. | 12-23-2010 |
20110049654 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer over the MTJ cap layer. The top electrode layer includes a first nitrified metal. | 03-03-2011 |
20110049656 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming a top electrode layer over an MTJ structure. The top electrode layer includes a first nitrified metal. | 03-03-2011 |
20110090732 | Magnetic Tunnel Junction Cell Adapted to Store Multiple Digital Values - A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value. | 04-21-2011 |
20110121417 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction structure above a bottom electrode. The method also includes forming a diffusion barrier layer above and adjacent to the magnetic tunnel junction structure. The method further includes etching back the diffusion barrier layer, removing the diffusion barrier layer above the magnetic tunnel junction structure. The method also includes connecting a top of the magnetic tunnel junction structure to a conductive layer. | 05-26-2011 |
20110127626 | Fabrication and Integration of Devices with Top and Bottom Electrodes Including Magnetic Tunnel Junctions - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 06-02-2011 |
20110133298 | Spin-Transfer Switching Magnetic Element Utilizing a Composite Free Layer Comprising a Superparamagnetic Layer - A system and method for forming a magnetic tunnel junction (MTJ) storage element utilizes a composite free layer structure. The MTJ element includes a stack comprising a pinned layer, a barrier layer, and a composite free layer. The composite free layer includes a first free layer, a superparamagnetic layer and a nonmagnetic spacer layer interspersed between the first free layer and the superparamagnetic layer. A thickness of the spacer layer controls a manner of magnetic coupling between the first free layer and the superparamagnetic layer. | 06-09-2011 |
20110133299 | Magnetic Tunnel Junction Device - A system and method of manufacturing and using a magnetic tunnel junction device is disclosed. In a particular embodiment, a magnetic tunnel junction device includes a first free layer and second free layer. The magnetic tunnel junction also includes a spin torque enhancement layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers that includes a material and has a thickness that substantially inhibits exchange coupling between the first and second free layers. The first and second free layers are magneto-statically coupled. | 06-09-2011 |
20110139497 | Via Structure Integrated in Electronic Substrate - A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided. | 06-16-2011 |
20110141796 | Magnetic Tunnel Junction Device and Fabrication - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer. | 06-16-2011 |
20110169112 | Composite Hardmask Architecture and Method of Creating Non-Uniform Current Path for Spin Torque Driven Magnetic Tunnel Junction - A magnetic tunnel junction (MTJ) storage element and method of forming the MTJ are disclosed. The magnetic tunnel junction (MTJ) storage element includes a pinned layer, a barrier layer, a free layer and a composite hardmask or top electrode. The composite hardmask/top electrode architecture is configured to provide a non-uniform current path through the MTJ storage element and is formed from electrodes having different resistance characteristics coupled in parallel. An optional tuning layer interposed between the free layer and the top electrode helps to reduce the damping constant of the free layer. | 07-14-2011 |
20110175181 | Magnetic Tunnel Junction (MTJ) on Planarized Electrode - A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ. | 07-21-2011 |
20110176350 | RESISTANCE-BASED MEMORY WITH REDUCED VOLTAGE INPUT/OUTPUT DEVICE - A resistance-based memory with a reduced voltage I/O device is disclosed. In a particular embodiment, a circuit includes a data path including a first resistive memory cell and a first load transistor. A reference path includes a second resistive memory cell and a second load transistor. The first load transistor and the second load transistor are input and output (I/O) transistors adapted to operate at a load supply voltage similar to a core supply voltage of a core transistor within the circuit. | 07-21-2011 |
20110178768 | System and Method of Adjusting a Resistance-Based Memory Circuit Parameter - Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin. | 07-21-2011 |
20110186946 | Magnetic Tunnel Junction with Domain Wall Pinning - Magnetic tunnel junctions (MTJs) are manufactured having pinning sites in a ferromagnetic layer of the MTJ. The pinning sites are created using patterns in the photomask used during patterning of the ferromagnetic layer without adding additional processes to manufacturing of the MTJs. The pinning sites create energy barriers substantially preventing a domain wall in the ferromagnetic layer from passing into fixed regions of the ferromagnetic layer. Additionally, the pinning sites substantially prevent a domain wall in the ferromagnetic layer from returning to the middle of the free region. Pinning the domain wall at the boundary of the fixed region and the free region the ferromagnetic layer improves reliability and sensitivity of the MTJ. The ferromagnetic layer may be magnetized in a direction perpendicular to the plane of the ferromagnetic layer. | 08-04-2011 |
20110233695 | Magnetoresistive Random Access Memory (MRAM) With Integrated Magnetic Film Enhanced Circuit Elements - A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions. | 09-29-2011 |
20110235217 | Fabricating A Magnetic Tunnel Junction Storage Element - Methods for forming a magnetic tunnel junction (MTJ) storage element and MTJ storage elements formed are disclosed. The MTJ storage element includes a MTJ stack having a pinned layer stack, a barrier layer and a free layer. An adjusting layer is formed on the free layer, such that the free layer is protected from process related damages. A top electrode is formed on the adjusting layer and the adjusting layer and the free layer are etched utilizing the top electrode as a mask. A spacer layer is then formed, encapsulating the top electrode, the adjusting layer and the free layer. The spacer layer and the remaining portions of the MTJ stack are etched. A protective covering layer is deposited over the spacer layer and the MTJ stack. | 09-29-2011 |
20110249490 | Asymmetric Write Scheme for Magnetic Bit Cell Elements - Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element. | 10-13-2011 |
20110254587 | Software Programmable Logic Using Spin Transfer Torque Magnetoresistive Devices - Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions. | 10-20-2011 |
20110267874 | Invalid Write Prevention for STT-MRAM Array - In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. | 11-03-2011 |
20110273926 | Method and Apparatus of Probabilistic Programming Multi-Level Memory in Cluster States Of Bi-Stable Elements - A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data. | 11-10-2011 |
20120012952 | Magnetic Storage Element Utilizing Improved Pinned Layer Stack - A magnetic tunnel junction (MTJ) storage element may comprise a pinned layer stack and a first functional layer. The pinned layer stack is formed of a plurality of layers comprising a bottom pinned layer, a coupling layer, and a top pinned layer. The first functional layer is disposed in the bottom pinned layer or the top pinned layer. | 01-19-2012 |
20120026783 | Latching Circuit - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path. | 02-02-2012 |
20120032287 | MRAM Device and Integration Techniques Compatible with Logic Integration - A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps. | 02-09-2012 |
20120033490 | Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction - A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. | 02-09-2012 |
20120040712 | System and Method to Initiate a Housekeeping Operation at a Mobile Device - A system and method to initiate a housekeeping operation at a mobile device is disclosed. In a particular embodiment, a method at a mobile device includes modifying a scheduled housekeeping operation in response to determining that the mobile device is in a charging mode. | 02-16-2012 |
20120075906 | Resistance Based Memory Having Two-Diode Access Device - A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line. | 03-29-2012 |
20120086089 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. A particular embodiment includes a magnetic tunnel junction structure above a bottom electrode. The particular embodiment further includes a portion of a diffusion barrier layer adjacent to the magnetic tunnel junction structure. A top of the magnetic tunnel junction structure is connected to a conductive layer. | 04-12-2012 |
20120087184 | Magnetic Random Access Memory (MRAM) Layout with Uniform Pattern - A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 04-12-2012 |
20120107966 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material. | 05-03-2012 |
20120188816 | Row-Decoder Circuit and Method with Dual Power Systems - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 07-26-2012 |
20120205764 | Methods of Integrated Shielding into MTJ Device for MRAM - Methods and apparatus for shielding a shielding a non-volatile memory, such as shielding a magnetic tunnel junction (MTJ) device from a magnetic flux are provided. In an example, a shielding layer is formed adjacent to an electrode of an MTJ device, such that the shielding layer substantially surrounds a surface of the electrode, and a metal line is coupled to the shielding layer. The metal line can be coupled to the shielding layer by a via. | 08-16-2012 |
20120218805 | Configurable Memory Array - Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode. | 08-30-2012 |
20120275212 | Self-Body Biasing Sensing Circuit for Resistance-Based Memories - A resistance based memory sensing circuit has reference current transistors feeding a reference node and a read current transistor feeding a sense node, each transistor has a substrate body at a regular substrate voltage during a stand-by mode and biased during a sensing mode at a body bias voltage lower than the regular substrate voltage. In one option the body bias voltage is determined by a reference voltage on the reference node. The substrate body at the regular substrate voltage causes the transistors to have a regular threshold voltage, and the substrate body at the body bias voltage causes the transistors to have a sense mode threshold voltage, lower than the regular threshold voltage. | 11-01-2012 |
20130002352 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier. | 01-03-2013 |
20130003447 | SENSING CIRCUIT - A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit. | 01-03-2013 |
20130062714 | STRAIN INDUCED REDUCTION OF SWITCHING CURRENT IN SPIN-TRANSFER TORQUE SWITCHING DEVICES - Partial perpendicular magnetic anisotropy (PPMA) type magnetic random access memory cells are constructed using processes and structural configurations that induce a directed static strain/stress on an MTJ to increase the perpendicular magnetic anisotropy. Consequently, reduced switching current of the MTJ results. The directed static strain/stress on the MTJ is induced in a controlled direction and/or with a controlled magnitude during fabrication. The MTJ is permanently subject to a predetermined directed stress and permanently includes the directed static strain/strain that provides reduced switching current. | 03-14-2013 |
20130062715 | SYMMETRICALLY SWITCHABLE SPIN-TRANSFER-TORQUE MAGNETORESISTIVE DEVICE - A spin transfer torque magnetic random access memory (STT-MRAM) device includes magnetic tunnel junctions (MTJs) with reduced switching current asymmetry. At least one switching asymmetry balance layer (SABL) near the free layer of the MTJ reduces a first switching current Ic(p-ap) causing the value of the first switching current to be nearly equal to the value of a second switching current Ic(ap-p) without increasing the average switching current of the device. The SABL may be a non-magnetic switching asymmetry balance layer (NM-SABL) and/or a magnetic switching asymmetry balance layer (M-SABL). | 03-14-2013 |
20130073598 | Entropy source with magneto-resistive element for random number generator - An entropy source and a random number (RN) generator are disclosed. In one aspect, a low-energy entropy source includes a magneto-resistive (MR) element and a sensing circuit. The MR element is applied a static current and has a variable resistance determined based on magnetization of the MR element. The sensing circuit senses the resistance of the MR element and provides random values based on the sensed resistance of the MR element. In another aspect, a RN generator includes an entropy source and a post-processing module. The entropy source includes at least one MR element and provides first random values based on the at least one MR element. The post-processing module receives and processes the first random values (e.g., based on a cryptographic hash function, an error detection code, a stream cipher algorithm, etc.) and provides second random values having improved randomness characteristics. | 03-21-2013 |
20130075845 | THERMALLY TOLERANT PERPENDICULAR MAGNETIC ANISOTROPY COUPLED ELEMENTS FOR SPIN-TRANSFER TORQUE SWITCHING DEVICE - Perpendicular magnetic anisotropy (PMA) type magnetic random access memory cells are constructed with a composite PMA layer to provide a magnetic tunnel junction (MTJ) with an acceptable thermal barrier, A PMA coupling layer is deposited between a first PMA layer and a second PMA layer to form the composite PMA layer. The composite PMA layer may be incorporated in PMA type MRAM cells or in-plane type MRAM cells. | 03-28-2013 |
20130076390 | Programmable Logic Sensing in Magnetic Random Access Memory - A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented. | 03-28-2013 |
20130114336 | THREE PORT MTJ STRUCTURE AND INTEGRATION - A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process. | 05-09-2013 |
20130119494 | MTJ STRUCTURE AND INTEGRATION SCHEME - A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack. | 05-16-2013 |
20130121066 | CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT - A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit. | 05-16-2013 |
20130130406 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a free layer and a spin torque enhancing layer. The spin torque enhancing layer includes a nano-oxide layer. | 05-23-2013 |
20130134533 | MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 05-30-2013 |
20130161771 | REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM) - An apparatus includes a memory cell including a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line. The MTJ structure includes a free layer coupled to the bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. A physical dimension of the pinned layer produces an unbalanced offset magnetic field which corresponds to a first switching current of the MTJ structure that enables switching from the first state to the second state when a first voltage is applied to the bit line and corresponds to a second switching current that enables switching from the second state to the first state when the first voltage is applied to the source line. | 06-27-2013 |
20130182500 | LATCHING CIRCUIT - A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit. | 07-18-2013 |
20130187247 | MULTI-BIT MAGNETIC TUNNEL JUNCTION MEMORY AND METHOD OF FORMING SAME - A spin-torque transfer (STT) magnetic tunnel junction (MTJ) memory includes a unitary fixed magnetic layer, a magnetic barrier layer on the unitary fixed magnetic layer, a free magnetic layer having a plurality of free magnetic islands on the magnetic barrier layer, and a cap layer overlying the free magnetic layer. Also a method of forming an STT-MTJ memory. | 07-25-2013 |
20130191048 | METHOD AND DEVICE FOR ESTIMATING DAMAGE TO A MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT - A method of estimating damage to a magnetic tunnel junction (MTJ) element that includes providing an MTJ element having a magnetic barrier layer, the magnetic barrier layer having a periphery, a cross-sectional area and a thickness and comprising an inner region of undamaged magnetic barrier material and an outer region of damaged magnetic barrier material between the inner region and the periphery, determining a first value indicative of an electrical characteristic of the MTJ element, determining a second value indicative of the electrical characteristic that the MTJ element would have had if the outer region of damaged magnetic barrier material were not present and if the inner region of undamaged magnetic barrier material extended to the periphery, and calculating a value indicative of the size of the outer region of damaged magnetic barrier material from the first value and the second value. Also a computer configured to perform the method. | 07-25-2013 |
20130194862 | NON-VOLATILE FLIP-FLOP - A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element. | 08-01-2013 |
20130201757 | MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING - A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer. | 08-08-2013 |
20130215675 | INVALID WRITE PREVENTION FOR STT-MRAM ARRAY - In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. | 08-22-2013 |
20130235639 | MAGNETIC RANDOM ACCESS MEMORY (MRAM)LAYOUT WITH UNIFORM PATTERN - A large scale memory array includes a. uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects. | 09-12-2013 |
20130235656 | MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION - An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad. | 09-12-2013 |
20130244345 | FABRICATION AND INTEGRATION OF DEVICES WITH TOP AND BOTTOM ELECTRODES INCLUDING MAGNETIC TUNNEL JUNCTIONS - An electronic device manufacturing process includes depositing a bottom electrode layer. Then an electronic device is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer. The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well-suited for is magnetic tunnel junctions (MTJs). | 09-19-2013 |
20130279244 | HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE - A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency. | 10-24-2013 |
20130286721 | LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP - A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage. | 10-31-2013 |
20130288395 | MAGNETIC TUNNEL JUNCTION DEVICE FABRICATION - In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal. | 10-31-2013 |
20130294150 | METHOD AND APPARATUS FOR TESTING A RESISTIVE MEMORY ELEMENT - Methods and apparatus for testing a resistive memory element are provided. In an example, an initial test resistor in a resistance network coupled to a first input of a sense amplifier is selected, where the resistive memory element is coupled. to a second input of the sense amplifier and an output of the sense amplifier is measured. Another test resistor is selected based on the output of the sense amplifier and both the measuring the output step and the selecting another test resistor step are repeated until the output of the sense amplifier changes. A resistance of the resistive memory element is estimated based on the last test resistor selected, where the selected test resistors and the resistive memory element pass respective currents having substantially similar amplitudes and are coupled to respective access transistors having substantially similar properties. | 11-07-2013 |
20130314980 | ROW-DECODER CIRCUIT AND METHOD WITH DUAL POWER SYSTEMS - A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation. | 11-28-2013 |
20140010006 | NON-REVERSIBLE STATE AT A BITCELL HAVING A FIRST MAGNETIC TUNNEL JUNCTION AND A SECOND MAGNETIC TUNNEL JUNCTION - A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ. | 01-09-2014 |
20140015077 | REDUCING SOURCE LOADING EFFECT IN SPIN TORQUE TRANSFER MAGNETORESISTIVE RANDOM ACCESS MEMORY (STT-MRAM) - A memory cell comprises a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line. | 01-16-2014 |
20140015080 | STT MRAM MAGNETIC TUNNEL JUNCTION ARCHITECTURE AND INTEGRATION - A magnetic tunnel junction (MTJ) device for a magnetic random access memory (MRAM) includes a first conductive interconnect communicating with at least one control device and a first electrode coupling to the first conductive interconnect through a via opening formed in a dielectric passivation barrier using a first mask. The device has an MTJ stack for storing data, coupled to the first electrode. A portion of the MTJ stack has lateral dimensions based upon a second mask. The portion defined by the second mask is over the contact via. A second electrode is coupled to the MTJ stack and also has a lateral dimension defined by the second mask. The first electrode and a portion of the MTJ stack are defined by a third mask. A second conductive interconnect is coupled to the second electrode and at least one other control device. | 01-16-2014 |
20140027869 | AMORPHOUS ALLOY SPACER FOR PERPENDICULAR MTJs - A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization. | 01-30-2014 |
20140043890 | MONOLITHIC MULTI-CHANNEL ADAPTABLE STT-MRAM - A monolithic multi-channel resistive memory includes at least one first bank associated with a first channel and tuned according to first device attributes and/or first circuit attributes. The memory also includes at least one second bank associated with a second channel and tuned according to second device attributes and/or second circuit attributes. | 02-13-2014 |
20140047184 | TUNABLE MULTI-TIERED STT-MRAM CACHE FOR MULTI-CORE PROCESSORS - A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes. | 02-13-2014 |
20140048894 | MTP MTJ DEVICE - Systems and methods for multiple-time programmable (MTP) devices. An MTP device includes a magnetic tunnel junction (MTJ) device programmable to a plurality of states based on voltage applied across the MTJ device. The plurality of states include a first resistance state corresponding to a first binary value stored in the MTJ device based on a first voltage, a second resistance state corresponding to a second binary value stored in the MTJ device based on a second voltage, a third resistance state corresponding to a breakdown of a barrier layer of the MTJ device based on a third voltage, and a fourth resistance state corresponding to an open fuse based on a fourth voltage. | 02-20-2014 |
20140050019 | MULTI-LEVEL MEMORY CELL USING MULTIPLE MAGNETIC TUNNEL JUNCTIONS WITH VARYING MGO THICKNESS - A Multi-Level Memory Cell (MLC) using multiple Magnetic Tunnel Junction (MTJ) structures having one or more layers with varying thickness is disclosed. The multiple MTJ structures, which are vertically stacked and arranged in series, may have substantially identical area dimensions to minimize fabrication costs because one mask can be used to pattern the multiple MTJ structures. Further, varying the thicknesses associated with the one or more layers may provide the multiple MTJ structures with different switching current densities and thereby increase memory density and improve read and write operations. In one embodiment, the layers with the varying thicknesses may include tunnel barriers or magnesium oxide layers associated with the multiple MTJ structures and/or free layers associated with the multiple MTJ structures. | 02-20-2014 |
20140063895 | LOW COST PROGRAMMABLE MULTI-STATE DEVICE - A one time programmable (OPT) and multiple time programmable (MTP) structure is constructed in a back end of line (BEOL) process using only one, two or three masks. The OTP/MTP structure can be programmed in one of three states, a pre-programmed high resistance state, and a programmable low resistance state and a programmable very high resistance state. In the programmable low resistance state, a barrier layer is broken down during an anti-fuse programming so that the OTP/MTP structure exhibits resistance in the hundred ohm order of magnitude. In the very high resistance state a conductive fuse is blown open during programming so that the OTP/MTP structure exhibits resistance in the mega-ohm order of magnitude. The OTP/MTP structure may include a magnetic tunnel junction (MTJ) structure or a metal-insulator-metal (MIM) capacitor structure. | 03-06-2014 |
20140063922 | MRAM WORD LINE POWER CONTROL SCHEME - Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated, with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro. | 03-06-2014 |
20140067890 | MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR - Embodiments of the disclosure are directed to generating a random number. An embodiment of the disclosure passes a current from a read operation through a magnetic tunnel junction (MTJ) to cause a first magnetization orientation of a free layer to switch to a second magnetization orientation, the switch in magnetization orientation causing a change in a resistance of the MTJ, and periodically samples the resistance of the MTJ to generate a bit value for the random number. | 03-06-2014 |
20140071741 | OTP CELL WITH REVERSED MTJ CONNECTION - A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current. | 03-13-2014 |
20140108478 | MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR - A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset. | 04-17-2014 |
20140139209 | MAGNETIC AUTOMATIC TESTING EQUIPMENT (ATE) MEMORY TESTER - Several novel features pertain to an automatic testing equipment (ATE) memory tester that includes a load board, a projected-field electromagnet, a positioning mechanism and a memory tester. The load board is for coupling to a die package that includes a magnetoresistive random access memory (MRAM) having several cells, where each cell includes a magnetic tunnel junction (MTJ). The projected-field electromagnet is for applying a portion of a magnetic field across the MRAM. The portion of the magnetic field may be substantially uniform. The positioning mechanism is coupled to the electromagnet and the load board, and is configured to position the electromagnet vertically about (above/below) the die package when the die package is coupled to the load board. The memory tester is coupled to the load board. The memory tester is for testing the MRAM when the substantially uniform portion of the magnetic field is applied across the MRAM. | 05-22-2014 |
20140203381 | PROCESS AND APPARATUS FOR TRANSFORMING NITRIDATION/OXIDATION AT EDGES, AND PROTECTING EDGES OF MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) LAYERS - Material surrounding a magnetic tunnel junction (MTJ) device region of a multi-layer starting structure is etched, forming an MTJ device pillar having an MTJ layer with a chemically damaged peripheral edge region. De-nitridation or de-oxidation, or both, restore the chemically damaged peripheral region to form an edge-restored MTJ layer. An MTJ edge restoration assist layer is formed on the edge-restored MTJ layer. An MTJ-edge-protect layer is formed on the insulating MTJ-edge-restoration-assist layer. | 07-24-2014 |
20140210021 | METHOD AND APPARATUS FOR AMELIORATING PERIPHERAL EDGE DAMAGE IN MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) DEVICE FERROMAGNETIC LAYERS - An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same. | 07-31-2014 |
20140211551 | MRAM SELF-REPAIR WITH BIST LOGIC - Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array. | 07-31-2014 |
20140219015 | SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL - A method includes creating a breakdown condition at a semiconductor transistor structure that includes an overlap region and a channel region. The breakdown condition is created by causing a first voltage difference between a gate of the semiconductor transistor structure and the overlap region to exceed a breakdown voltage of the semiconductor transistor structure while maintaining a second voltage difference between the gate and the channel region at less than the breakdown voltage. | 08-07-2014 |
20140222880 | METHOD AND APPARATUS FOR GENERATING RANDOM NUMBERS USING A PHYSICAL ENTROPY SOURCE - A method and apparatus for generating random binary sequences from a physical entropy source having a state A and a state B by detecting whether the physical entropy source is in the state A or in the state B, attempting to shift the state of the physical entropy source to the opposite state in a probabilistic manner with less than 100% certainty, and producing one of four outputs based on the detected state and the state of the physical entropy source before the attempted shift. The outputs are placed in first and second queues and extracted in pairs from each queue. Random binary bits are output based on the sequences extracted from each queue. | 08-07-2014 |
20140231940 | STT-MRAM DESIGN ENHANCED BY SWITCHING CURRENT INDUCED MAGNETIC FIELD - A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current. | 08-21-2014 |
20140254251 | MAGNETIC AUTOMATIC TEST EQUIPMENT (ATE) MEMORY TESTER DEVICE AND METHOD EMPLOYING TEMPERATURE CONTROL - In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature. | 09-11-2014 |
20140269031 | SYSTEM AND METHOD OF SENSING A MEMORY CELL - A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage. | 09-18-2014 |
20150019147 | METHOD AND DEVICE FOR ESTIMATING DAMAGE TO MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENTS - For first and second magnetic tunnel junction (MTJ) elements, a trend in a relationship between an electrical characteristic of the first and second MTJ elements and an area of the first and second MTJ elements may be determined. Damage to a sidewall of the first and second MTJ elements may be estimated from the trend. At least one operating parameter of an MTJ manufacturing apparatus may be modified based on an X or Y intercept a trend line. | 01-15-2015 |
20150036409 | SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL USING MAGNETIC TUNNEL JUNCTION CELLS - An apparatus includes a group of data cells and a reference cell coupled to the group of data cells. The reference cell includes four magnetic tunnel junction (MTJ) cells. | 02-05-2015 |
20150070979 | PHYSICALLY UNCLONABLE FUNCTION BASED ON PROGRAMMING VOLTAGE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage. | 03-12-2015 |
20150071430 | PHYSICALLY UNCLONABLE FUNCTION BASED ON THE INITIAL LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array. | 03-12-2015 |
20150071431 | PHYSICALLY UNCLONABLE FUNCTION BASED ON THE RANDOM LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY - One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state. | 03-12-2015 |
20150071432 | PHYSICALLY UNCLONABLE FUNCTION BASED ON RESISTIVITY OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY MAGNETIC TUNNEL JUNCTIONS - One feature pertains to least one physically unclonable function based on an array of magnetoresistive random-access memory (MRAM) cells. A challenge to the array of MRAM cells may identify some of the cells to be used for the physically unclonable function. Each MRAM cell may include a plurality of magnetic tunnel junctions (MTJs), where the MTJs may exhibit distinct resistances due to manufacturing or fabrication variations. A response to the challenge may be obtained for each cell by using the resistance(s) of one or both of the MTJs for a cell to obtain a value that serves as the response for that cell. The responses for a plurality of cells may be at least partially mapped to provide a unique identifier for the array. The responses generated from the array of cells may serve as a physically unclonable function that may be used to uniquely identify an electronic device. | 03-12-2015 |
20150074433 | PHYSICALLY UNCLONABLE FUNCTION BASED ON BREAKDOWN VOLTAGE OF METAL- INSULATOR-METAL DEVICE - One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage. | 03-12-2015 |