Seon Kwang
Seon Kwang Jeon, Ichon KR
Patent application number | Description | Published |
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20090121745 | DFLOP CIRCUIT FOR AN EXTERNALLY ASYNCHRONOUS-INTERNALLY CLOCKED SYSTEM - A DFLOP circuit for an EAIC system includes a resolver. The resolver includes a signal transmission controller that is activated under the control of an internal clock signal to receive and transmit an input signal, and a precharge unit that is activated in response to the internal clock signal to precharge an output node of the signal transmission controller. | 05-14-2009 |
20090121766 | EXTERNALLY ASYNCHRONOUS INTERNALLY CLOCKED SYSTEM - An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated. | 05-14-2009 |
Seon Kwang Jeon, Icheon-Si Gyeonggi-Do KR
Patent application number | Description | Published |
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20140014958 | SEMICONDUCTOR CHIP MODULE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip module includes a first semiconductor chip having first through-electrodes, a second semiconductor chip having second through-electrodes which are electrically connected with the first through-electrodes, first and second test pads, a first connection line which connects the first test pad with one second through-electrode, a second connection line which connects the second test pad with another second through-electrode, third connection lines which connect the remaining second through-electrodes into pairs, and are partially constituted by fuses, and a third semiconductor chip having fourth connection lines which electrically connect the first through-electrodes of the first semiconductor chip into pairs, wherein the first and second is through-electrodes are connected in series between the first test pad and the second test pad by the first connection line, the second connection line, the third connection lines, and the fourth connection lines. | 01-16-2014 |
Seon Kwang Jeon, Icheon KR
Patent application number | Description | Published |
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20150029805 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of first regions formed in a line-type and extending in a first direction, and a plurality of second regions and a plurality of third regions arranged between adjacent first regions in a zigzag manner. | 01-29-2015 |