Patent application number | Description | Published |
20080197860 | Configurable voltage regulator - A configurable semiconductor has a device characteristic that is controllable as a function of at least one external impedance. A measurement circuit measures an electrical characteristic of the at least one external impedance and determines a select value corresponding to the measured electrical characteristic. A first circuit controls the device characteristic as a function of the select value. | 08-21-2008 |
20080205103 | POWER FACTOR CONTROL SYSTEMS AND METHODS - A boost converter comprises an inductance that receives an input signal. A switch controls current supplied via the inductance to a load. A power factor control module comprises a mode control module that selects an operating mode of the boost converter and a switch control module that switches the switch at a frequency. The frequency is equal to a first frequency when the mode control module selects a continuous mode and equal to a second frequency when the mode control module selects a discontinuous mode. The first frequency is greater than the second frequency. | 08-28-2008 |
20080209240 | Pre-emptive power supply control system and method - A control system for controlling a power supply having an operating function. The power supply to supply an output current to an integrated circuit having at least one circuit block that is controllable by an enable signal or a clock signal. A receiver to receive the enable signal. A controller to determine a loading status of the at least one circuit block as a function of the enable signal or the clock signal and to control the output current of the power supply as a function of the loading status of the at least one circuit block such that the power supply preemptively changes the output current. | 08-28-2008 |
20080211706 | Capacitive digital to analog and analog to digital converters - A pipelined analog-to-digital converter (ADC) comprises a first stage that receives an input voltage signal and that comprises an analog-to-digital converter (ADC). The ADC includes an amplifier having an input and an output. N capacitances are connected in parallel and include first ends that selectively communicate with the input and second ends. N switches selectively connect the second ends of the N capacitances to the voltage input during a first phase, one of the second ends of the N capacitances to the output of the amplifier during a second phase, and others of the second ends of the N capacitances to one of a voltage reference and a reference potential during the second phase. A second stage communicates with the output the amplifier. | 09-04-2008 |
20080215914 | Self-reparable semiconductor and method thereof - A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually. | 09-04-2008 |
20080222357 | Low power computer with main and auxiliary processors - A processing device comprises a processor, low power nonvolatile memory that communicates with the processor, high power nonvolatile memory that communicates with the processor. The processing device manages data using a cache hierarchy comprising a high power (HP) nonvolatile memory level for data in the high power nonvolatile memory and a low power (LP) nonvolatile memory level for data in the low power nonvolatile memory. The LP nonvolatile memory level has a higher level in the cache hierarchy than the HP nonvolatile memory level. | 09-11-2008 |
20080222437 | Low power computer with main and auxiliary processors - An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode. | 09-11-2008 |
20080237649 | Integrated circuits and interconnect structure for integrated circuits - An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first plane-like metal layer and the N plane-like metal layers are located separate planes. First and second drain regions have a symmetric shape across at least one of horizontal and vertical centerlines. First and second gate regions have a first shape that surrounds the first and second drain regions, respectively. First and second source regions are arranged adjacent to and on one side of the first gate region, the second gate region and the connecting region. The first source region, the second source region, the first drain region and the second drain region communicate with at least two of the N plane-like metal layers. | 10-02-2008 |
20080258240 | Integrated circuits and interconnect structure for integrated circuits - An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with respective ones of the N plane-like metal layers, where M is an integer greater than one, wherein the first plane-like metal layer and the N plane-like metal layers are located in separate planes. A first drain region has a generally rectangular shape. First, second, third and fourth source regions have a generally rectangular shape and that are arranged adjacent to sides of the first drain region. The first drain region and the first, second, third and fourth source regions communicate with at least two of the N plane-like metal layers. A first gate region is arranged between the first, second, third and fourth source regions and the first drain region. First, second, third and fourth substrate contact regions are arranged adjacent to corners of the first drain region. | 10-23-2008 |
20080258241 | Integrated circuits and interconnect structure for integrated circuits - An integrated circuit includes N plane-like metal layers. A first plane-like metal layer includes M contact portions that communicate with the N plane-like metal layers, respectively. The first source region is arranged between first sides of the first and second drain regions and the second and third source regions are arranged adjacent to second sides of the first and second drain regions. A fourth source region is arranged adjacent to third sides of the first and second drain regions and a fifth source region is arranged adjacent to fourth sides of the first and second drain regions. First and second drain contacts are arranged in the first and second drain regions, respectively. At least two of the first, second, third, fourth and fifth source regions and the first and second drain regions communicate with at least two of the N plane-like metal layers. | 10-23-2008 |
20080258828 | Colpitts Oscillator - A Colpitts oscillator includes a tank circuit, a first transistor, and a first feedback circuit. The first transistor includes a first region, a second region, and a control region. The first region communicates with the tank circuit. The first feedback circuit communicates with the second region and the control region of the first transistor. | 10-23-2008 |
20080263267 | SYSTEM ON CHIP WITH RECONFIGURABLE SRAM - A system on chip comprises N components, where N is an integer greater than one, and a storage module. The storage module comprises a first memory, a control module, and a connection module. The first memory includes M blocks of static random access memory, where M is an integer greater than one. The control module generates a first assignment of the M blocks to the N components during a first period and generates a second assignment of the M blocks to the N components during a second period. The first and second assignments are different. The connection module dynamically connects the M blocks to the N components based on the first and second assignments. | 10-23-2008 |
20080263324 | DYNAMIC CORE SWITCHING - A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode. | 10-23-2008 |
20080266034 | LOW-NOISE FINE-FREQUENCY TUNING - Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing. | 10-30-2008 |
20080272848 | Nested transimpedance amplifier - A nested transimpedance amplifier (TIA) circuit comprises a zero-order TIA having an input and an output. A first operational amplifier (opamp) has an output and an input that communicates with said output of said zero-order TIA. A first power supply input applies a first voltage to the zero-order TIA. A second power supply input receives a second voltage. A charge pump module develops a third voltage based on the first voltage and the second voltage, wherein the third voltage is applied to the opamp. | 11-06-2008 |
20080272880 | DEVICE WITH IC, SOC OR SIP HAVING ONE OR MORE REMOTELY ENABLED MODULE AND METHODS FOR SELLING THE DEVICE - A device comprises an integrated circuit comprising N first circuit modules each having an enabled state, wherein N is an integer greater than zero and M second circuit modules each having a disabled state, wherein M is an integer greater than zero. A control module that outputs upgrade data including identification of the M second circuit modules for enabling the M second circuit modules, respectively, and that allows selection and enablement of at least one of the M second circuit modules by a purchaser based on payment of at least corresponding ones of M prices associated with said M second circuit modules. | 11-06-2008 |
20080288748 | Dynamic core switching - A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled. | 11-20-2008 |
20080297218 | VARIABLE CAPACITANCE WITH DELAY LOCK LOOP - An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A tunable circuit having variable capacitance is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals. | 12-04-2008 |
20080320321 | Computer with low-power secondary processor and secondary display - A computer having an active mode and an inactive mode includes a primary processor and a primary memory. A primary display is associated with the primary processor and the primary memory. The primary processor, the primary memory, and the primary display are operated when the computer is in the active mode and are powered down when the computer is in the inactive mode. A secondary processor dissipates less power than the primary processor. A secondary display communicates with the secondary processor. The secondary processor and the secondary display are powered up when the computer is in the inactive mode, and the secondary processor processes at least one of wireless network data and disk drive data when the computer is in each of the active mode and the inactive mode. | 12-25-2008 |
20090040079 | CALIBRATING REPLICA DIGITAL-TO-ANALOG CONVERTERS - A system includes a first digital-to-analog converter (DAC), a replica DAC, a control module, and a calibrating DAC. The first DAC receives a first input and generates a first analog output based on the first input. The replica DAC receives the first input and generates a replica analog output based on the first input. The control module generates a first control based on the first input. The calibrating DAC generates a calibration analog output based on the first control. The calibration analog output adjusts the replica analog output. | 02-12-2009 |
20090051432 | High-bandwidth high-gain amplifier - A pipelined analog to digital converter includes a first stage that receives an input voltage, that generates a first sampled digital value and a first residue voltage, and that includes a first amplifier that amplifies the first residue voltage and generates a first amplified residue voltage. A second stage receives the first amplified residue voltage, generates a second sampled digital value and a second residue voltage, and includes a second amplifier that amplifies the second residue voltage. At least one of the first amplifier and the second amplifier comprises a first transistor having a control terminal, a first terminal, and a second terminal, a second transistor having a control terminal, a first terminal, and a second terminal that communicates with the second terminal of the first transistor, a differential transimpedance amplifier and a differential output amplifier. | 02-26-2009 |
20090102556 | CLASS D AMPLIFIER - A Class D amplifier includes a ramp generator that generates a ramp signal and an inverted ramp signal. A signal generator generates first, second, third and fourth signals by comparing the ramp and inverted ramp signals to an input signal. A frequency of the ramp signal is approximately two orders of magnitude higher than a frequency of the input signal. The signal generator transitions from a first state to a second state of a first control signal after one of the first and second signals occurs, transitions from a first state to a second state of a second control signal after one of the third and fourth signals occurs, and transitions from the second state to the first state of one of the first and second control signals when the other of the first and second control signals transitions to the second state. An output stage includes first and second switches that are controlled based on the first and second control signals, respectively, and generates output current based on the first and second control signals. | 04-23-2009 |
20090140803 | AMPLIFIERS WITH COMPENSATION - An amplifier system includes a first amplifier stage having an input and an output. A second amplifier stage has an input and an output, the input of the second amplifier stage being connected to the output of the first amplifier stage. A transistor has a control terminal, a first terminal, and a second terminal, the first terminal of the transistor being coupled to the output of the first amplifier stage and the input of the second amplifier stage. A first capacitance has a first terminal and a second terminal, the first terminal of the first capacitance being connected to the input of the first amplifier stage, the second terminal of the first capacitance being connected to the second terminal of the transistor. A first current source to source current to amplifier system, the first current source being is connected to the output of the first amplifier stage. A second current source will sink current from the amplifier system. The second current source is connected to the second terminal of the first capacitance and the second terminal of the transistor. | 06-04-2009 |
20090153247 | HIGH-SPEED, MULTI-STAGE CLASS AB AMPLIFIERS - A multi-stage Class AB amplifier system comprises a first Class AB amplifier circuit that receives an input signal. A bias circuit receives an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit having an input that communicates with an output of the bias circuit and that generates an output signal. A common-mode feedback circuit generates a feedback signal to the first Class AB amplifier circuit based on the output signal. | 06-18-2009 |
20090167275 | VOLTAGE REGULATOR FEEDBACK PROTECTION METHOD AND APPARATUS - An integrated circuit includes an output terminal. A plurality of feedback terminals receives a feedback signal. A voltage regulator has a feedback input in communication with the plurality of feedback terminals to receive the feedback signal. The voltage regulator has a power output in communication with the output terminal. The voltage regulator is responsive to the feedback signal to generate the power output. | 07-02-2009 |
20090174374 | DYNAMIC MULTIPHASE OPERATION - An output regulator includes a plurality of switch arrays. A controller enables selected ones of the plurality of switch arrays in response to a sense signal. The sense signal is based on an output of the output regulator. The controller generates drive signals to control the selected ones of the plurality of switch arrays. The controller adjusts first selected pulses in an output phase of the selected ones of the plurality of switch arrays based on a first pulse width. The controller adjusts second selected pulses in the output phase of the selected ones of the plurality of switch arrays based on a second pulse width greater than or less than the first pulse width. | 07-09-2009 |
20090231174 | PIPELINED ANALOG-TO-DIGITAL CONVERTERS - An analog-to-digital converter including a first stage and a second stage. The first stage receives a first reference voltage and a first analog input voltage, generates a first digital signal by quantizing the first analog input voltage, and generates a first analog output voltage based on the first digital signal and the first analog input voltage. The second stage receives a second reference voltage and the first analog output voltage, in which the second reference voltage is lower than the first reference voltage. The second stage further generates a second digital signal by quantizing the first analog output voltage, and generates a second analog output voltage based on the second digital signal and the first analog output voltage. | 09-17-2009 |
20090237286 | FLASH ADC - An analog to digital converter (ADC) includes a resistance ladder including N resistances arranged in series. Connection nodes are arranged between adjacent ones of the N resistances and at each end of the resistance ladder. An input signal is received at a selected connection node of the connection nodes. N is an integer greater than one. A plurality of delay elements receive signals from corresponding ones of the connection nodes and apply predetermined delays to the signals to produce delayed signals. The predetermined delays are based on an electrical distance between the corresponding ones of the connection nodes and the selected connection node, respectively. A plurality of comparators include corresponding first input terminals that receive the delayed signals from respective ones of the plurality of delay elements. | 09-24-2009 |
20090250751 | MOS DEVICE WITH LOW ON-RESISTANCE - Some of the embodiments of the present disclosure provide a metal oxide semiconductor (MOS) device comprising a drain region, a gate region surrounding the drain region and formed in a loop around the drain region, a plurality of source regions arranged around the gate region, wherein each source region is situated across from a corresponding side of the drain region, and a plurality of bulk regions arranged around the gate region, wherein one or more of the plurality of source regions separate one or more of the plurality of bulk regions from the gate region. Other embodiments are also described and claimed. | 10-08-2009 |
20090273305 | CONTROL SYSTEM FOR FLUORESCENT LIGHT FIXTURE - A ballast module regulates power output to a fluorescent light. The ballast module includes a component. A temperature sensor senses temperature of the component. A control module adjusts power output to the fluorescent light based on the temperature of the component sensed by the temperature sensor. The control module adjusts power to the fluorescent light by reducing the power output to the fluorescent light or increasing the power output to the fluorescent light. | 11-05-2009 |
20090307437 | Multiport Memory Architecture, Devices and Systems Including the Same, and Methods of Using the Same - A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses. | 12-10-2009 |
20090327588 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A solid-state disk (SSD) controller includes a first integrated circuit (IC) that includes an interface module, a memory control module, and a wireless network interface module. The interface module externally interfaces the SSD controller to a computing device. The memory control module controls solid-state memory, receives data from the computing device via the interface module, and caches the data in the solid-state memory. The wireless network interface module communicates with the computing device via the interface module and allows the computing device to connect to a wireless network. | 12-31-2009 |
20100011159 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 01-14-2010 |
20100023705 | PROCESSOR ARCHITECTURE HAVING MULTI-PORTED MEMORY - A data processing system includes a multiport memory module including a plurality of first ports and a plurality of second ports. The data processing system includes a plurality of first buses and a plurality of second buses. A plurality of hardware acceleration modules configured to communicate with respective ones of the plurality of first ports via respective ones of the plurality of first buses. The data processing system includes a processor module. A random access memory (RAM) module configured to store data. The processor module and the RAM module communicate with the multiport memory module via respective ones of the plurality of second buses. A shared bus includes a first bus portion configured to communicate with the plurality of hardware acceleration modules at a first rate. A second bus portion configured to communicate with the processor module and the RAM module at a second rate that is different than the first rate. A bus bridge that communicates with the first bus portion and the second bus portion. | 01-28-2010 |
20100060327 | HIGH VOLTAGE HIGH SIDE TRANSISTOR DRIVER - A transistor driver includes a sender module configured to generate a power input signal. A converter module includes a transformer including a first side and a second side. The first side of the transformer is configured to receive the power input signal. A rectifier is connected to the second side of the transformer. The converter module is configured to generate an output signal at an output of the rectifier. A first receiver module is connected to each of the second side of the transformer and the output of the rectifier. The first receiver module is configured to transition a first transistor between an ON state and an OFF state based on a first signal received from the second side of the transformer. | 03-11-2010 |
20100072602 | STACKED INTEGRATED CIRCUIT PACKAGE USING A WINDOW SUBSTRATE - An integrated circuit (IC) package is disclosed. The IC package includes a first substrate having a first surface having first substrate bond pads, a second surface having second substrate bond pads, and an opening that extends from the first surface to the second surface. The IC package further includes a first IC having a first IC surface that includes first bond pads and that is directly attached to the second surface of the first substrate, and a second IC surface. The first bond pads are accessible through the opening. The IC package also includes a second IC having a third IC surface that is directly attached to the second IC surface, and a fourth IC surface that includes second bond pads. At least one of the first bond pads is connected to at least one of the first substrate bond pads using one or more bond wires. At least one of the second bond pads is connected to at least one of the second substrate bond pads using one or more bond wires. The opening has a first side and a second side. The first substrate bond pads are located adjacent to only the first side of the opening. | 03-25-2010 |
20100073083 | NESTED TRANSIMPEDANCE AMPLIFIER - A nested transimpedance amplifier circuit includes a first-order nested transimpedance amplifier having an input and an output. The first-order nested transimpedance amplifier is configured to be powered by a first voltage. A charge pump module is configured to receive the first voltage and a second voltage. The second voltage is different from the first voltage. The charge pump module generates a third voltage based on the first voltage and the second voltage. A first operational amplifier has an input and an output. The input of the first operational amplifier communicates with the output of the zero-order transimpedance amplifier, and the first operational amplifier is configured to be powered by the third voltage. | 03-25-2010 |
20100074310 | ACTIVE RESISTIVE SUMMER FOR A TRANSFORMER HYBRID - A system includes a transceiver configured to receive a composite signal. The composite signal is a composite of a transmit signal and a receive signal. A replica transmitter is configured to generate a replica transmit signal based on the transmit signal. A transmit canceller is configured to recover the receive signal at least in part by resistively summing the composite signal and the replica transmit signal. | 03-25-2010 |
20100117877 | CALIBRATING REPLICA DIGITAL-TO-ANALOG CONVERTERS - A system includes a first digital-to-analog converter (DAC), a replica DAC, a control module, and a calibrating DAC. The first DAC receives a first input and generates a first analog output based on the first input. The replica DAC receives the first input and generates a replica analog output based on the first input. The control module generates a first control based on the first input. The calibrating DAC generates a calibration analog output based on the first control. The calibration analog output adjusts the replica analog output. | 05-13-2010 |
20100127909 | COMMUNICATION DRIVER - A circuit includes T sets of digital to analog converters (DACs), each including N current sources and M delay elements. An output signal includes a sum of outputs of the N current sources. An input of a first one of the M delay elements and a control input of a first one of the N current sources receive a respective one of a plurality of decoded signals. T sets of first converters each have a feedback node, an output, and an input that communicates with the output signal of a respective one of the T sets of DACs. T second converters have inputs that communicate with respective ones of the feedback nodes of each of the T sets of first converters. A summer generates a difference signal that is based on the outputs of the T sets of first converters and outputs of the T second converters. | 05-27-2010 |
20100235660 | LOW POWER COMPUTER WITH MAIN AND AUXILIARY PROCESSORS - An architecture for a computer includes a primary processor that consumes power at a first rate, that is operated when the computer is in an high power mode and that is not powered when the computer is in a low power mode. A primary graphics processor communicates with the primary processor, is operated when the computer is in the high power mode and is not powered when the computer is in the low power mode. A secondary graphics processor communicates with a secondary processor. The secondary processor consumes power at a second rate that is less than the first rate. The secondary processor and the secondary graphics processor are operated when the computer is in the low power mode. | 09-16-2010 |
20100259908 | EXPOSED DIE PAD PACKAGE WITH POWER RING - A packaged semiconductor is disclosed. The packaged semiconductor comprises a conductive integral frame that includes an inner portion and a ring portion encircling the inner portion, a semiconductor die that is mounted to a first surface of the inner portion of the conductive frame, and a casing that supports the conductive frame and covers the semiconductor die. Sections of the conductive frame that connect the inner portion to the ring portion are removed after the casing is applied to the conductive frame. | 10-14-2010 |
20100264838 | LED LIGHTING DEVICE - Aspects of the disclosure provide light emitting diode (LED) lighting devices, and methods to drive the LED lighting devices. An LED lighting device includes a transformer having a primary winding on a receiving path to receive electric energy from an energy source and a secondary winding on a driving path. A terminal of the receiving path and a terminal of the driving path have a same voltage level, such as ground. Further, the LED lighting device includes a primary switch configured to switch on the receiving path to receive and store the electric energy in the transformer, and to switch off the receiving path to allow the driving path to deliver the stored electric energy. The LED lighting device also includes an LED array coupled to the driving path to emit light in response to the delivered electric energy. | 10-21-2010 |
20100277141 | DIGITAL LOW DROPOUT REGULATOR - A low dropout (LDO) regulator for generating an output voltage on an output from an input voltage of an input source. The LDO regulator including a switch module to generate the output voltage. The switch module including at least two parallel connected switches responsive to corresponding switch control signals to regulate a flow of energy from the input source to the output. Each of the switches having an on-state and an off-state. A digital controller to sense the output voltage and in response to generate the switch control signals such that the output voltage is regulated to a predetermined amplitude. | 11-04-2010 |
20100284158 | PACKAGING TECHNIQUES AND CONFIGURATIONS - One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural, support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate. | 11-11-2010 |
20100291881 | PUSH-PULL LOW-NOISE AMPLIFIER WITH AREA-EFFICIENT IMPLEMENTATION - An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric. | 11-18-2010 |
20100295620 | HIGH-SPEED, MULTI-STAGE CLASS AB AMPLIFIERS - A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit configured to receive an input signal. A bias circuit is configured to receive an output of the first Class AB amplifier circuit. A second Class AB amplifier circuit is in communication with the bias circuit. The second Class AB amplifier circuit is configured to generate an output signal. A current mirror circuit is arranged between the first Class AB amplifier circuit and the bias circuit. A common-mode feedback circuit is configured to generate a feedback signal based on the output signal. | 11-25-2010 |
20100305765 | APPARATUS, METHOD, AND COMPUTER PROGRAM FOR SPRINKLER CONTROL - A sprinkler system having a method and computer program comprises one or more sprinklers each comprising a sprinkler valve adapted to regulate an amount of fluid delivered by the sprinkler in response to a control signal; a master unit adapted to transmit digital data; and a sprinkler controller comprising a receiver adapted to receive a signal representing the digital data; a media access controller adapted to obtain the digital data from the signal; and a processor adapted to produce the control signal based on the digital data obtained by the media access controller; and an output circuit adapted to provide the control signal to the sprinklers. | 12-02-2010 |
20100321037 | CONFIGURABLE VOLTAGE REGULATOR - A configurable semiconductor includes N terminals adapted to be connected to at least one of T external impedances. N is an integer greater than zero and T is an integer greater than one. The T external impedances have impedance values within predetermined tolerances. A measurement circuit measures an impedance value of at least one of the T external impedances. A control circuit compares the measured impedance value to T ranges and selects a value of a device characteristic based on comparison. The value of the device characteristic selected by the control circuit is independent of the predetermined tolerances of the T external impedances. | 12-23-2010 |
20100329058 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line. | 12-30-2010 |
20110001565 | HIGH-SPEED, MULTI-STAGE CLASS AB AMPLIFIERS - A multi-stage Class AB amplifier system includes a first Class AB amplifier circuit and a second Class AB amplifier circuit. A current mirror circuit is in communication with the first Class AB amplifier circuit. A bias circuit is in communication with the current mirror circuit. A frequency compensation circuit is arranged between the bias circuit and the second Class AB amplifier circuit. A common-mode feedback circuit is in communication with the second Class AB amplifier circuit. The common-mode feedback circuit is configured to generate a feedback signal. | 01-06-2011 |
20110001571 | CRYSTAL OSCILLATOR EMULATOR - A crystal oscillator emulator integrated circuit includes a first temperature sensor configured to sense a first temperature of the crystal oscillator emulator integrated circuit. The memory is configured to (i) store calibration parameters and (ii) select at least one of the calibration parameters based on the first temperature. A semiconductor oscillator is configured to generate an output signal, wherein (i) the output signal has a frequency and an amplitude and (ii) the frequency is based on the at least one of the calibration parameters. An amplitude adjustment module is configured to (i) compare the amplitude to a predetermined amplitude and (ii) generate a control signal to adjust the amplitude based on the comparison. | 01-06-2011 |
20110001587 | DIE-TO-DIE ELECTRICAL ISOLATION IN A SEMICONDUCTOR PACKAGE - Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die. Other embodiments are also described and claimed. | 01-06-2011 |
20110003562 | TRANSCEIVER SYSTEM INCLUDING DUAL LOW-NOISE AMPLIFIERS BACKGROUND - A transceiver system includes a first receive path with a first antenna configured to receive first signals, a first configuration switch, a first low noise amplifier configured to amplify the first signals, a second configuration switch, and a receiver. The first receive path is selectively configured to supply the amplified first signals to the receiver via the first antenna, the first configuration switch, the first low noise amplifier, and the second configuration switch. A second receive path includes a second antenna configured to receive second signals, a second low noise amplifier configured to amplify the second signals, the second configuration switch, and the receiver. The second receive path (i) includes fewer configuration switches than the first receive path and (ii) is selectively configured to supply the amplified second signals to the receiver via the second antenna, the second low noise amplifier, and the second configuration switch. | 01-06-2011 |
20110006750 | LOW POWER AND HIGH ACCURACY BAND GAP VOLTAGE REFERENCE CIRCUIT - A band gap voltage reference circuit includes a first band gap circuit configured to generate a first band gap voltage potential. A second band gap circuit includes a variable resistance. The second band gap circuit is configured to output a second band gap voltage potential based on a value of the variable resistance. A calibration circuit is configured to adjust the variable resistance of the second band gap circuit based on the first band gap voltage potential and the second band gap voltage potential. The first band gap circuit is shut down in response to the second band gap voltage potential being within a predetermined range of the first band gap voltage potential. | 01-13-2011 |
20110018627 | NESTED TRANSIMPENDANCE AMPLIFIER - A nested transimpedance amplifier circuit includes a first-order nested transimpedance amplifier having an input and an output. The first-order nested transimpedance amplifier is configured to be powered by a first voltage. A charge pump module is configured to receive the first voltage and a second voltage. The second voltage is different from the first voltage. The charge pump module generates a third voltage based on the first voltage and the second voltage. A first operational amplifier has an input and an output. The input of the first operational amplifier communicates with the output of the zero-order transimpedance amplifier, and the first operational amplifier is configured to be powered by the third voltage. | 01-27-2011 |
20110026284 | Power Factor Control Systems and Methods - A boost converter comprises an inductance that receives an input signal. A switch controls current supplied by the inductance to a load. A power factor control module comprises a mode control module that selects an operating mode of the boost converter and a switch control module that switches the switch at a frequency. The frequency is equal to a first frequency when the mode control module selects a continuous mode and equal to a second frequency when the mode control module selects a discontinuous mode. The first frequency is greater than the second frequency. | 02-03-2011 |
20110029752 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing. | 02-03-2011 |
20110035545 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory system comprises first memory that includes memory cells. Content addressable memory (CAM) includes CAM memory cells, stores addresses of selected ones of the memory cells, stores data having the addresses in corresponding ones of the CAM memory cells and retrieves data having the addresses from corresponding ones of the CAM memory cells. An adaptive refresh module stores data from selected ones of the memory cells in the CAM memory cells to one of increase and maintain a time period between refreshing of the memory cells. | 02-10-2011 |
20110038184 | Isolated AC-DC Converter with Master Controller on Secondary Side and Slave Controller on Primary Side - An isolated alternating current (AC)-direct current (DC) converter is disclosed. The isolated AC-DC converter comprises a slave control circuit including a slave driver module configured to receive a command and to control coupling of the slave control circuit to a primary-side inductor of a transformer based on the command, a master control circuit coupled to a secondary-side inductor of the transformer, the master control circuit including a master control module configured to sense a feedback voltage across a load and to generate the command based on the feedback voltage and a reference voltage, and a coupler configured to communicate the command from the master control module to the slave driver module and to provide isolation between the master control module and the slave driver module. | 02-17-2011 |
20110109359 | Variable Capacitance with Delay Lock Loop - An integrated circuit includes a delay lock loop (DLL) circuit that generates incremental delay line signals and a delay line output signal based on a received clock signal. A pulse-width modulation (PWM) control module generates a PWM control signal. A variable capacitance circuit is controlled based on the delay line output signal, the PWM control signal, and one of the incremental delay line signals. | 05-12-2011 |
20110128062 | Low-Noise Fine-Frequency Tuning - Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing. | 06-02-2011 |
20110147919 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - Embodiments of the present disclosure provide window ball grid array semiconductor packages. A semiconductor package includes a substrate having (i) a first surface, (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate. The semiconductor package further includes a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps; one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; and a first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 06-23-2011 |
20110169621 | TIME UPDATING AND LOAD MANAGEMENT SYSTEMS - An electrical distribution system for distributing electrical power throughout a residence. The electrical distribution system includes a plurality of electrical distribution lines configured to distribute electrical power to one or more appliances; and an electrical panel in communication with (i) a utility company and (ii) the plurality of electrical distribution lines. The electrical panel is configured to receive the electrical power from the utility company, and distribute the electrical power onto the plurality of electrical distribution lines for consumption by the one or more appliances. The electrical panel is further configured to receive, from the utility company, time data indicating a current time of day, and provide, through the plurality of electrical distribution lines, the time data to each of the one or more appliances so that the one or more appliances can keep track of the current time of day. | 07-14-2011 |
20110175218 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 07-21-2011 |
20110204724 | Dual Output Direct Current (DC)-DC Regulator - An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output. | 08-25-2011 |
20110221530 | CLASS AB AMPLIFIERS - A class AB amplifier includes a first inductor having a first terminal in communication with a voltage source terminal. A first transistor has a drain terminal in communication with a second terminal of the first inductor. A second transistor has a source terminal in communication with a source terminal of the first transistor. A second inductor has a first terminal in communication with a drain terminal of the second transistor and a second terminal in communication with a reference potential. The drain terminals of the first transistor and the second transistor are capacitively coupled together. | 09-15-2011 |
20110238872 | Disk Drive System On Chip With Integrated Buffer Memory and Support for Host Memory Access - A circuit for a storage device that communicates with a host device comprises a first high speed interface. A storage controller communicates with the high speed interface. A buffer communicates with the storage controller. The storage device generates storage buffer data during operation. The storage controller is adapted to selectively store the storage buffer data in at least one of the buffer and/or in the host device via the high speed interface. A bridge chip for enterprise applications couples the circuit to an enterprise device. | 09-29-2011 |
20110261660 | Magnetic And Optical Rotating Storage Systems With Audio Monitoring - An integrated circuit for controlling a data storage device. The integrated circuit includes: a drive module configured to control operation of the data storage device, wherein the data storage device is of a particular quality; and an audio monitoring module in communication with the drive module, wherein the audio monitoring module is configured to analyze an audio signal generated by the data storage device while the drive module is controlling the operation of the data storage device. The particular quality of the data storage device is determinable based on the analysis of the audio signal. | 10-27-2011 |
20110298117 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed. | 12-08-2011 |
20120014196 | PROCESSOR INSTRUCTION CACHE WITH DUAL-READ MODES - A processor including a cache memory, a decoder, a precharge circuit, a control module, and an amplifier module. The decoder generates a first word line signal to access first instructions stored in a first word line, and (ii) generates a second word line signal to access second instructions stored in the first word line or a second word line. The precharge circuit (i) precharges first bit lines connected to the first word line prior to accessing each of the first and second instructions. The control module adjusts a rate of a clock signal from a first rate to a second rate. The amplifier module accesses the first instructions based on (i) the first word line signal and (ii) the clock signal at the first rate, and accesses the second instructions based on (i) the second word line signal and (ii) the clock signal at the second rate. | 01-19-2012 |
20120038467 | Power Control Device - A controllable light bulb comprises an electrical connector, a receiver module, an electronic switch, a translucent casing, and a light producing element. The electrical connector receives a power signal. The receiver module is powered by the power signal received via the electrical connector and determines control parameters based upon on/off modulation of the power signal. The receiver module generates a control signal based upon the control parameters while the power signal is on. The electronic switch outputs an output power signal and reduces the output power signal based on the control signal. The translucent casing encloses the light producing element. The light producing element receives the output power signal. | 02-16-2012 |
20120098127 | POWER/GROUND LAYOUT FOR CHIPS - Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip. | 04-26-2012 |
20120134187 | POWER FACTOR CONTROL SYSTEMS AND METHODS - A boost converter comprises an inductance that receives an input signal. A switch controls current supplied by the inductance to a load. A power factor control module comprises a mode control module that selects an operating mode of the boost converter and a switch control module that switches the switch at a frequency. The frequency is equal to a first frequency when the mode control module selects a continuous mode and equal to a second frequency when the mode control module selects a discontinuous mode. The first frequency is greater than the second frequency. | 05-31-2012 |
20120146551 | CONTROL SYSTEM FOR FLUORESCENT LIGHT FIXTURE - A circuit includes a component connected (i) to a rectifier, and (ii) between electrodes of a lamp. The electrodes include a first electrode and a second electrode. A control module is in communication with the rectifier and is configured to receive a temperature signal from a temperature sensor. The temperature signal is indicative of a temperature of the component. The control module is also configured to decrease current to the electrodes for a predetermined period when the temperature of the component is greater than a first predetermined temperature. The control module is further configured to increase the current to the electrodes when the predetermined period expires and independent of the temperature of the component. | 06-14-2012 |
20120161871 | CMOS Push-Pull Power Amplifier With Even-Harmonic Cancellation - A power amplifier includes a push-pull pair of transistors including a first transistor inductively coupled to a voltage source and coupled to a ground, and a second transistor inductively coupled to the ground and coupled to the voltage source. Gates of the first and the second transistors are AC inputs configured to receive an AC signal having a fundamental frequency. Drain regions of the first and the second transistors are, respectively, first and second output nodes. The power amplifier further includes a capacitor coupled between the first output node and the second output node and where the capacitor is configured as a pathway for cancellation of even harmonic signals of the fundamental frequency of the AC signal. | 06-28-2012 |
20120161879 | TECHNIQUES TO IMPROVE THE STRESS ISSUE IN CASCODE POWER AMPLIFIER DESIGN - An amplifier includes a first transistor, and a first inductor disposed between the first transistor and a voltage source. A first output node is between the first transistor and the first inductor. The amplifier further includes a second inductor disposed between the first transistor and ground. The amplifier further includes a second transistor, and a third inductor disposed between the second transistor and a ground. A second output node is between the second transistor and the third inductor. The amplifier further includes a fourth inductor disposed between the second transistor and the voltage source. The amplifier further includes a first capacitor disposed between the first output node and the second output node, and a second capacitor disposed between a first mid-node, which is between the first transistor and the first inductor, and a second mid-node, which is between the second transistor and fourth inductor. | 06-28-2012 |
20120161880 | TECHNIQUES ON INPUT TRANSFORMER TO PUSH THE OP1dB HIGHER IN POWER AMPLIFIER DESIGN - A power amplifier includes a first transistor and a first inductor disposed between the first transistor and a voltage source. A first node between the first transistor and the first inductor is an output node. The power amplifier further includes a second inductor disposed between the first transistor and ground The power amplifier further includes a third inductor coupled to a gate of the first transistor and configured as a first AC input. The power amplifier further includes a first phase conditioner inductively coupled to the second inductor and the third inductor and configured to set phases of AC signals across the first inductor and the second inductor in phase. The second inductor is configured to release energy into the first inductor to raise a voltage of the AC signal and raise a power output at the output node. | 06-28-2012 |
20120170617 | Frequency and Q-Factor Tunable Filters Using Frequency Translatable Impedance Structures - A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node. | 07-05-2012 |
20120192001 | COMPUTER WITH LOW-POWER SECONDARY PROCESSOR AND SECONDARY DISPLAY - A device operable in each of active and inactive modes includes first and second processors. The first processor performs, in accordance with a first power level, both wireless and non-wireless network processing. A second processor performs wireless network processing in accordance with a second power level. While the device is operating in the active mode: the first processor and the first display are powered up; the first display displays a result of the wireless network processing or the non-wireless network processing by the first processor; and the second processor and the second display are powered down. While the device is operating in the inactive mode: the first processor and the first display are powered down; the second processor and the second display are powered up; and the second display displays a result of the wireless network related processing by the second processor. | 07-26-2012 |
20120205812 | PATTERNS OF PASSIVATION MATERIAL ON BOND PADS AND METHODS OF MANUFACTURE THEREOF - A method includes forming a pad on an electronic component. The pad comprises conductive material. The method further includes providing passivation material on a surface of the conductive material and removing passivation material from the surface to expose portions of the conductive material to form a bond pad comprising conductive material and passivation material. | 08-16-2012 |
20120239908 | DUAL THREAD PROCESSOR - Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time. The processor causes data associated with the first processor thread to pass through the processor's pipeline during the first periods of processor time. A second counter is similarly configured. The processor can be configured to receive an input defining processor time to be allocated to one or more processor threads and to use the input to change one or more of the counters such that subsequent periods of processor times for the one or more processor threads are affected. | 09-20-2012 |
20120280803 | TWO WAY REMOTE CONTROL - A target device comprising a wireless interface that transmits configuration data to and receives commands from a remote control device. A control module that receives said commands and that adjusts operation of said target device based thereon; and a user input interface for locally adjusting operation of said target device. | 11-08-2012 |
20120286394 | METAL OXIDE METAL CAPACITOR STRUCTURES - A metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit including first opposing side walls, second opposing side walls, a cavity with first and second openings, and openings in the first opposing side walls. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. The inner conducting structure is arranged in the cavity of the outer conducting structure and includes a body, and conducting extensions that extend from the body through the openings in the first opposing side walls. Oxide is arranged between the outer conducting structure and the inner conducting structure. | 11-15-2012 |
20120313692 | SUPER-HIGH-VOLTAGE RESISTOR ON SILICON - An integrated circuit (IC) including a first layer of a conducting material; a second layer of an insulating material, where the second layer has a first side arranged adjacent to the first layer, and a second side; and a substrate arranged adjacent to the second side of the second layer. A first well arranged in the substrate. The first well is adjacent to the second side of the second layer. The substrate and the first well have opposite doping. | 12-13-2012 |
20120319621 | TRIAC DIMMING SYSTEMS FOR SOLID-STATE LOADS - A system includes a transformer. The transformer includes a first coil and a second coil. The first coil is configured to receive a first voltage based on an output of a switching circuit. The second coil is configured to generate a first current based on the first voltage to power a solid-state load. The system also includes a third coil. The third coil is configured to generate a second voltage based on the first voltage. | 12-20-2012 |
20120326234 | BALLAST RESISTOR FOR SUPER-HIGH-VOLTAGE DEVICES - An integrated circuit (IC) including a well region of the IC having a first doping level and a plurality of semiconductor regions implanted in the well region. Each of the plurality of semiconductor regions has a second doping level. The second doping level is greater than the first doping level. A plurality of polysilicon regions are arranged on the plurality of semiconductor regions. The polysilicon regions are respectively connected to the semiconductor regions. The plurality of semiconductor regions is a drain of a metal-oxide semiconductor field-effect transistor (MOSFET). | 12-27-2012 |
20120326282 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die. | 12-27-2012 |
20130031432 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal. | 01-31-2013 |
20130044555 | PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING - A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array. | 02-21-2013 |
20130057163 | REGULATOR FOR LED LIGHTING COLOR MIXING - A system includes a first light emitting diode configured to produce light of a first color and a second light emitting diode configured to produce light of a second color. A constant current circuit is configured to provide a first current, wherein (i) the first current is approximately constant, (ii) a first portion of the first current flows through the second light emitting diode, and (iii) a remaining portion of the first current flows through the first light emitting diode. A current regulating circuit is configured to control the first portion of the first current flowing through the second light emitting diode. The current regulating circuit is connected in series with the second light emitting diode, the constant current circuit, and a reference potential. The first light emitting diode is connected in series directly between the constant current circuit and the reference potential. | 03-07-2013 |
20130082359 | REMOVING CONDUCTIVE MATERIAL TO FORM CONDUCTIVE FEATURES IN A SUBSTRATE - Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate. | 04-04-2013 |
20130103899 | SYSTEM ON CHIP WITH RECONFIGURABLE SRAM - A system on chip includes electrical components and a first memory including memory blocks. A method of operating the system on chip includes generating an assignment of the memory blocks to the electrical components. The generating includes, initially, during a development phase of the system on chip, generating the assignment so that selected memory blocks of the memory blocks are assigned to first selected electrical components of the electrical components as emulated read-only memory. The generating includes, subsequently, during an operational phase of the system on chip, modifying the assignment so that one or more of the selected memory blocks are re-assigned to second selected electrical components of the electrical components as cache memory. The method also includes, according to the assignment, dynamically creating electrical connectivity between the memory blocks and the electrical components. | 04-25-2013 |
20130106638 | SCALABLE SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER | 05-02-2013 |
20130113568 | PUSH-PULL LOW-NOISE AMPLIFIER WITH AREA-EFFICIENT IMPLEMENTATION - An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric. | 05-09-2013 |
20130124918 | SELF-REPARABLE SEMICONDUCTOR AND METHOD THEREOF - A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals. | 05-16-2013 |
20130127051 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 05-23-2013 |
20130127550 | FREQUENCY SCALING OF VARIABLE SPEED SYSTEMS FOR FAST RESPONSE AND POWER REDUCTION - A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers. | 05-23-2013 |
20130154510 | CURRENT BALANCING CIRCUITS FOR LIGHT-EMITTING-DIODE-BASED ILLUMINATION SYSTEMS - A system including a first transistor, a second transistor, and a comparator. The first transistor is configured to supply a first current to a first load connected to a first terminal of the first transistor. The second transistor is configured to supply a second current to a second load connected to a first terminal of the second transistor, wherein the first current and the second current have a predetermined ratio. The comparator is configured to compare a voltage at the first terminal of the first transistor or a voltage at the first terminal of the second transistor to a reference voltage, and to adjust, based on the comparison, biasing of the first transistor and the second transistor to maintain the predetermined ratio between the first current and the second current. | 06-20-2013 |
20130154743 | CLASS AB AMPLIFIERS - An amplifier includes a first switch and a second switch each having a first terminal and a second terminal. The first terminals of the first and second switches respectively communicate with a first tank circuit and a second tank circuit. The second terminal of the second switch communicates with the second terminal of the first switch. A first capacitance having a first terminal connected directly to (i) the second terminal of the first switch and (ii) the second terminal of the second switch. A second terminal of the first capacitance is connected directly to a first input voltage of the amplifier. A first load is connected across (i) the first terminal of the first switch and (ii) the first terminal of the second switch. The amplifier generates a first output across the first load. | 06-20-2013 |
20130171775 | EXPOSED DIE PAD PACKAGE WITH POWER RING - A method of fabricating a packaged semiconductor includes forming a conductive frame as an integral piece of conductive material. The frame includes an inner portion and a ring portion encircling the inner portion. The ring portion includes a first ring portion encircling first and second sides of the inner portion, and a first bar portion located on a third side of the inner portion. The method includes mounting a semiconductor die to a first surface of the inner portion of the frame. The die is configured to receive power via the first ring portion. The method includes applying a casing, which covers the die, to the frame. The method includes, after the casing is applied to the frame, removing (i) sections of the frame that connect the inner portion to the ring portion, and (ii) sections of the frame that connect the first ring portion to the first bar portion. | 07-04-2013 |
20130212670 | Intelligent PHY with security detection for ethernet networks - A physical layer device includes memory, a memory control module, and a physical layer module. The memory control module is configured to control access to the memory. The physical layer module is configured to store packets in the memory via the memory control module. The physical layer module includes an interface configured to receive the packets from a network device via a network and an interface bus. The interface bus includes at least one of a control module and a regular expression module. The at least one of the control module and the regular expression module is configured to inspect the packets to determine a security level of the packets. A network interface is configured to, based on the security level, provide the packets to a device separate from the physical layer device. | 08-15-2013 |
20130215579 | PACKAGING TECHNIQUES AND CONFIGURATIONS - One embodiment of the present disclosure provides an apparatus comprising a flex circuit substrate having a core, a first solder mask and first traces disposed on the core on a first side of the flex circuit substrate, and a second solder mask and second traces disposed on the core on a second side of the flex circuit substrate. The first side is opposite to the second side. The apparatus further includes vias formed through the core to electrically couple the first traces to the second traces, and a stiffening structure coupled to the first side of the flex circuit substrate to increase structural rigidity of the flex circuit substrate. The stiffening structure provides structural support to allow attachment of an integrated circuit die to the first side of the flex circuit substrate. | 08-22-2013 |
20130219114 | COMBINED MOBILE DEVICE AND SOLID STATE DISK WITH A SHARED MEMORY ARCHITECTURE - A mobile device includes a system-on-chip (SOC) that includes a mobile device control module, a solid state disk (SSD) control module, and a random access memory (RAM) control module. The mobile device control module executes application programs for the mobile device. The solid-state disk (SSD) control module controls SSD operations. The RAM control module communicates with the mobile device control module and the SSD control module and stores both SSD-related data and mobile device-related data in a single RAM. | 08-22-2013 |
20130300507 | POWER AMPLIFIER WITH FEEDBACK IMPEDANCE FOR STABLE OUTPUT - An amplifier circuit amplifies a signal for wireless transmission. A feedback circuit, including a capacitor, is coupled to the amplifier circuit. Components of the feedback circuit are selected based on a feedback factor such that an input impedance to the amplifier circuit has a same impedance characteristic as a feedback circuit impedance of the feedback circuit. | 11-14-2013 |
20130339588 | System on Chip with Reconfigurable SRAM - A system on chip includes a random access memory, a read-only memory, and a processor. The processor is configured to, during a development phase of the system on chip, read program code from the random access memory and execute the program code. The program code is developed during the development phase until a completed version of the program code is reached. The processor is configured to, during an operational phase of the system on chip, (i) read the completed version from the read-only memory, (ii) execute the completed version, and (iii) cache data in the random access memory. The processor is configured to, during the operational phase and in response to an improvement to the completed version of the program code being developed, (i) read program code corresponding to the improvement from the random access memory, and (ii) read remaining portions of the completed version from the read-only memory. | 12-19-2013 |
20140021598 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - In an embodiment, there is provided a packaging arrangement comprising a substrate; a multi-memory die coupled to the substrate, wherein the multi-memory die comprises multiple individual memory dies, and each of the multiple individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies, and the multi-memory die is created by singulating the wafer of semiconductor material into memory dies, where at least one of the memory dies is the multi-memory die that includes the multiple individual memory dies that are still physically connected together; and a semiconductor die coupled to the multi-memory die and the substrate, wherein the semiconductor die is configured as a system on a chip, wherein at least one of the multi-memory die and the semiconductor die is attached to the substrate. | 01-23-2014 |
20140041916 | METHODS OF MAKING PACKAGES USING THIN CU FOIL SUPPORTED BY CARRIER CU FOIL - In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer. | 02-13-2014 |
20140042877 | Controlling Fan Motors Using Capacitive Sensing - A motor having a rotor, the rotor including a first metal plate having a first size and a second metal plate having a second size arranged on a first surface associated with the rotor. The first metal plate and the second metal plate are arranged adjacent to each other at a predetermined distance from an axis of rotation of the rotor. The first surface rotates perpendicularly about the axis in response to the rotor being rotated about the axis. A stator includes a third metal plate arranged on a second surface associated with the stator. The third metal plate is arranged on the second surface at the predetermined distance from the axis. The second surface is parallel to the first surface and faces the first surface. | 02-13-2014 |
20140044224 | FREQUENCY AND Q-FACTOR TUNABLE FILTERS USING FREQUENCY TRANSLATABLE IMPEDANCE STRUCTURES - A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node. | 02-13-2014 |
20140055217 | DIE-TO-DIE ELECTRICAL ISOLATION IN A SEMICONDUCTOR PACKAGE - Some of the embodiments of the present disclosure provide a semiconductor package comprising a first die; a second die; and an inductor arrangement configured to inductively couple the first die and the second die while maintaining electrical isolation between active circuit components of the first die and active circuit components of the second die. Other embodiments are also described and claimed. | 02-27-2014 |
20140077891 | CRYSTAL OSCILLATOR EMULATOR WITH EXTERNALLY SELECTABLE OPERATING CONFIGURATIONS - A crystal oscillator emulator having a plurality of predetermined operating configurations. The crystal oscillator emulator includes a measurement circuit configured to measure a value of an impedance connected to a select pin of the crystal oscillator emulator, wherein the impedance is external to the crystal oscillator emulator, and generate an output having a value corresponding to the value of the impedance. The storage circuit is configured to store a plurality of values corresponding to the plurality of predetermined operating configurations and select one of the plurality of values based on the output of the measurement circuit. A controller is configured to set an output frequency of the crystal oscillator emulator based on the selected one of the plurality of values. | 03-20-2014 |
20140091714 | CURRENT LIMITING CIRCUIT AND METHOD FOR LED DRIVER - Aspects of the disclosure provide a circuit that includes a driver circuit and a current limiter circuit. The driver circuit is configured to drive a load with an output current when the load is coupled with the driver circuit. The current limiter circuit is configured to turn on a path to deplete a portion of the output current from the driver circuit in order to prevent a load current flowing through the load from exceeding a current limit. | 04-03-2014 |
20140106508 | STRUCTURES EMBEDDED WITHIN CORE MATERIAL AND METHODS OF MANUFACTURING THEREOF - Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die. | 04-17-2014 |
20140125417 | SYSTEMS AND METHODS FOR BOOSTING A RECEIVED AC SIGNAL USING A POWER AMPLIFIER INCLUDING PHASE CONDITIONERS - A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor. | 05-08-2014 |
20140159596 | PHOSPHOR AND LED PLACEMENT FOR WHITE LED-BASED LAMPS - A system including a base portion, which includes first and second sets of light emitting diodes (LEDs) to emit blue light having first and second wavelengths in first and second wavelength ranges in a spectrum of blue light, a glass layer arranged at a second predetermined distance from the base portion, and a plurality of coatings of first and second phosphors having a predetermined length arranged in an alternating pattern on a surface of the glass layer facing toward the LEDs. The LEDs of the first and second sets are arranged on the base portion in an alternating pattern and are separated from each other by a first predetermined distance. Centers of the coatings of the first and second phosphors respectively align with centers of corresponding LEDs in the first and second sets. | 06-12-2014 |
20140159600 | LED-BASED LAMP WITH USER-SELECTABLE COLOR TEMPERATURE - A lamp including a first set of light emitting diodes configured to generate first light, a second set of light emitting diodes configured to generate second light, and a third set of light emitting diodes configured to generate third light. The first light, the second light, and the third light combine to produce white light. A first switch is located at a base portion of the lamp. The state of the first switch corresponds to a color temperature of the white light. A color temperature adjustment module is configured to vary outputs of the first, second, and third sets of light emitting diodes in accordance with the color temperature of the white light selected by a user using the first switch. | 06-12-2014 |
20140160725 | LIGHT EMITTING DIODES GENERATING WHITE LIGHT - A system including a first set of light emitting diodes, a second set of light emitting diodes, and a control module. The first set of light emitting diodes is configured to emit blue light having first wavelengths in a first wavelength range in a spectrum of blue light. The first set of light emitting diodes includes a green phosphor configured to convert the blue light having the first wavelengths to green light. The second set of light emitting diodes is configured to emit blue light having second wavelengths in a second wavelength range in the spectrum of blue light. The second set of light emitting diodes includes a red phosphor configured to convert the blue light having the second wavelengths to red light. The first wavelength range is less than the second wavelength range. The control module is configured to control currents through the first set of light emitting diodes and the second set of light emitting diodes. | 06-12-2014 |
20140184156 | SYSTEM AND METHOD FOR CHARGING BATTERIES OF VEHICLES AND RETURNING CHARGE FROM BATTERIES TO UTILITY COMPANIES - A monitoring module monitors a charge level of a battery in a vehicle. A network interface module transmits a first set of charging parameters for charging the battery to a utility company and receives a reply and a charge return request from the utility company for returning charge from the battery to the utility company. The first set of charging parameters includes the charge level of the battery and a first time of the day for charging the battery. The reply includes a second time of the day for charging the battery. A control module generates a first signal based on the reply and the first set of charging parameters, and a second signal based on the charge return request and charge return parameters. A charging module charges the battery based on the first signal. A charge retrieval module returns the charge based on the second signal. | 07-03-2014 |
20140203874 | POWER AMPLIFIERS WITH PUSH-PULL TRANSISTORS, CAPACITIVE COUPLING FOR HARMONIC CANCELLATION, AND INDUCTIVE COUPLING TO PROVIDE DIFFERENTIAL OUTPUT SIGNALS - A differential power amplifier including a push-pull pair of transistors, a capacitance, a first inductance, and a second inductance. The push-pull pair of transistors includes first and second transistors. The first transistor includes control and output terminals. The second transistor includes input and control terminals. The control terminals of the first and second transistors collectively receive a differential input signal. The output and input terminals collectively provide a differential output signal. The capacitance is connected to the output and input terminals. The first capacitance cancels first harmonics at the output terminal of the first transistor with second harmonics at the input terminal of the second transistor. The first transistor and the first inductance are connected in series between a voltage source and a reference terminal. The second transistor and the second inductance are connected in series between the voltage source and the reference terminal. | 07-24-2014 |
20140204640 | METHOD AND APPARATUS FOR CHANGING A FREQUENCY OF A SWITCH PRIOR TO A LEVEL OF CURRENT RECEIVED FROM AN INDUCTOR DECREASING TO A PREDETERMINED LEVEL - A controller including a switch, a first module, a second module, and a control module. The switch receives current from an inductor and bypasses a portion of the current from being received by a load. The switch is cycled between a first state and a second state at a frequency. The first module, for a first cycle of the switch, determines a first amount of time the switch is in the first state. The second module, based on the first amount of time, determines a second amount of time for a level of the current to decrease to a predetermined level. The second amount of time begins during the first cycle and when the switch transitions from the first state to the second state. The control module, based on the second amount of time and prior to the current decreasing to the predetermined level, changes the frequency of the switch. | 07-24-2014 |
20140206141 | METHODS AND ARRANGEMENTS RELATING TO SEMICONDUCTOR PACKAGES INCLUDING MULTI-MEMORY DIES - Embodiments provide a method comprising providing a multi-memory die that comprises multiple individual memory dies. Each of the individual memory dies is defined as an individual memory die within a wafer of semiconductor material during production of memory dies. The multi-memory die is created by singulating the wafer of semiconductor material into memory dies where at least one of the memory dies is a multi-memory die that includes multiple individual memory dies that are still physically connected together. The method further comprises coupling a semiconductor die to the multi-memory die. | 07-24-2014 |
20140215164 | Multiport Memory Architecture - The present disclosure describes techniques and apparatuses for multiport memory architecture. In some aspects serial data is received from a data port and converted to n-bit-wide words of data. The n-bit-wide words of data are then buffered as a k-word-long block of parallel data into a line of a multiline buffer as a block of k*n bits of data. The block of k*n bits of data is then transmitted to a multiport memory via a write bus effective to write the block of k*n bits of data to the multiport memory. | 07-31-2014 |
20140237171 | SOLID-STATE DISK WITH WIRELESS FUNCTIONALITY - A system including an interface module to interface a solid-state disk controller to a computing device. A memory control module exchanges data with the computing device via the interface module and caches the data in a solid-state memory controlled by the solid-state disk controller. A network interface module communicates with the computing device via the interface module and interfaces the computing device to a wireless network. A crossbar module has a master bus (Mbus) interface bridged to an advanced high-performance bus (AHB). A memory communicates with one or more of the network interface module and the crossbar module via one or more of the Mbus interface and the AHB. In response to data being cached from the computing device to the solid-sate memory or data cached in the solid-state memory being output to the computing device, the network interface module buffers data received from the wireless network in the memory. | 08-21-2014 |
20140239485 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 08-28-2014 |
20140240046 | SYSTEMS AND METHODS FOR OPERATING A POWER AMPLIFIER - A power amplifier configured to receive an AC input signal and output, based on the AC input signal, an output voltage via a first output voltage terminal and a second output voltage terminal. The power amplifier includes a first transistor and a second transistor connected in a push-pull configuration, a first inductor, a second inductor, and a first capacitor. The first output voltage terminal is located between the first inductor and the first transistor. The second output voltage terminal is located between the second transistor and ground. The first capacitor is configured to provide a first circuit path between the first output voltage terminal and the second output voltage terminal. The first circuit path functions as a short circuit for even harmonics of a fundamental frequency of the AC input signal but does not function as a short circuit for the fundamental frequency of the AC input signal. | 08-28-2014 |
20140253238 | CLASS AB AMPLIFIERS - An amplifier including first, second, third, and fourth switches, each having first and second terminals. The first terminal of each switch communicates with a respective load. The second terminal of the first switch communicates with the second terminal of the second switch. The second terminal of the third switch communicates with the second terminal of the fourth switch. A first terminal of a first capacitance communicates with the second terminals of the first and second switches. A first terminal of a second capacitance communicates with the second terminals of the third and fourth switches. A first inductance communicates with second terminals of the first and second capacitances. | 09-11-2014 |
20140289575 | SYSTEMS AND METHODS FOR TESTING PAGES OF DATA STORED IN A MEMORY MODULE - A memory module including a first memory, a second memory, a test module, and a control module. The first memory is configured to store pages of data to be tested for errors. The second memory is configured to store addresses for the pages of data and store copies of the pages of data. The test module is configured to perform testing on the pages of data stored in the first memory. The control module is configured to, prior to the testing being performed by the test module on the pages of data stored in the first memory, cause the second memory to store the addresses and the copies of the pages of data stored in the first memory and, subsequent to the testing being performed by the test module, store the copies of the pages of data to the first memory based on the addresses stored in the second memory. | 09-25-2014 |
20140334201 | SNUBBER CIRCUIT TO INCREASE EFFICIENCY OF POWER CONVERTERS - A system including a converter and a snubber circuit. The converter converts an alternating current voltage into a direct current voltage and outputs the direct current voltage across an inductance and a switch connected in series. The inductance has a center tap connected to a node, which is connected to a load. In response to the switch being turned on, a first current flows through the inductance and the switch. In response to the switch being turned off, a second current flows from the node to the load. The snubber circuit is connected across the node and a junction of the inductance and the switch. In response to the switch being turned off, the snubber circuit receives a third current from the junction, and supplies a first portion of the third current to the node. The second current and the first portion of the third current flow through the load. | 11-13-2014 |
20140347894 | CURRENT SHAPING FOR DIMMABLE LED - Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC. | 11-27-2014 |
20150015158 | APPARATUSES FOR BLEEDING CURRENT FROM A TRANSFORMER OF A SOLID-STATE LIGHT EMITTING DIODE - A system configured to provide current to power a solid-state light emitting diode in accordance with a dimming level, wherein the dimming level corresponds to an amount of light provided from the solid-state light emitting diode. The system includes a transformer and a switch. The transformer includes a coil. The transformer is configured to receive a first current. The coil is configured to, based on the first current, output a second current to power the solid-state light emitting diode. The switch is configured to, based on a dimming level that corresponds to the amount of light provided from the solid-state light emitting diode of the system, bleed a portion of the second current out of the coil to a ground reference in order to divert the portion of the second current from being supplied to the solid-state light emitting diode. | 01-15-2015 |
20150022117 | CURRENT BALANCING CIRCUITS FOR LIGHT-EMITTING-DIODE-BASED ILLUMINATION SYSTEMS - A system including a plurality of switches and a comparator. The plurality of switches is configured to respectively supply a plurality of currents via respective terminals to a plurality of sets of light emitting diodes. The sets of light emitting diodes are configured to respectively output light having wavelengths in a plurality of wavelength ranges in a spectrum of blue light. The comparator is configured to compare a reference voltage to a voltage at one of the terminals of one of the plurality of switches connected to one of the sets of light emitting diodes, and to adjust, based on the comparison, biasing of the plurality of switches to maintain a predetermined ratio of the plurality of currents. | 01-22-2015 |
20150024590 | REMOVING CONDUCTIVE MATERIAL TO FORM CONDUCTIVE FEATURES IN A SUBSTRATE - Apparatuses having, and methods for forming, conductive features are described. A hole is formed in a substrate and a conductive material is deposited in the hole. A part of the conductive material that occupies a first lengthwise portion of the hole is removed, and a conductive feature that occupies a second lengthwise portion of the hole remains in the substrate. | 01-22-2015 |
20150035160 | PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY - Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. | 02-05-2015 |
20150076687 | PACKAGING DRAM AND SOC IN AN IC PACKAGE - An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate. | 03-19-2015 |
20150078047 | CURRENT SHAPING FOR DIMMABLE LED - Aspects of the disclosure provide a circuit that includes a detector and a controller. The detector is configured to detect a firing start by a triode for alternating current (TRIAC) in a power supply. The controller is configured to control a switch in connection with a magnetic component in response to the firing start to shape a profile of a current pulled from the power supply to satisfy a latch current requirement and a hold current requirement of the TRIAC. | 03-19-2015 |