Patent application number | Description | Published |
20090201074 | Method and Circuit for Implementing Efuse Sense Amplifier Verification - A method and circuit for implementing Efuse sense amplifier verification, and a design structure on which the subject circuit resides are provided. A first predefined resistor value is sensed relative to a reference resistor. A second predefined resistor value is sensed relative to a reference resistor. Responsive to identifying a respective sense amplifier output resulting from the sensing steps of an unblown eFuse and a blown eFuse, valid operation of the sense amplifier is identified. | 08-13-2009 |
20090201756 | Method and Circuit for Implementing Enhanced Efuse Sense Circuit - A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline. | 08-13-2009 |
20090212850 | Method and Circuit for Implementing Efuse Resistance Screening - A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse. | 08-27-2009 |
20100067319 | Implementing Precise Resistance Measurement for 2D Array Efuse Bit Cell Using Differential Sense Amplifier, Balanced Bitlines, and Programmable Reference Resistor - A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse. | 03-18-2010 |
Patent application number | Description | Published |
20090109723 | Quad SRAM Based One Time Programmable Memory - A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. | 04-30-2009 |
20090109724 | Differential Latch-Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 04-30-2009 |
20090237974 | Programmable memory cell - A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage. | 09-24-2009 |
20090237975 | One-time programmable memory cell - A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse. | 09-24-2009 |
20100014340 | Quad SRAM Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 01-21-2010 |
20110255327 | METHOD AND SYSTEM FOR SPLIT THRESHOLD VOLTAGE PROGRAMMABLE BITCELLS - Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage. | 10-20-2011 |
20120195091 | Method and System for Split Threshold Voltage Programmable Bitcells - A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device | 08-02-2012 |
20130307116 | Method and System for Split Threshold Voltage Programmable Bitcells - A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping. | 11-21-2013 |
20140183656 | Method and System for Split Threshold Voltage Programmable Bitcells - A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping. | 07-03-2014 |
20140376300 | DIFFERENTIAL BIT CELL - A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path. | 12-25-2014 |
Patent application number | Description | Published |
20090090730 | Transparent, portable secure container for consumer products not legally purchased by minors - A transparent, portable secure container is configured to accommodate a standard retail package for a consumer product not legally purchased by minors. The container comprises a plurality of panels, a hinge and a lock. Some of the panels are joined to form the container, such that the container conforms to outside dimensions of the standard retail package. One of the panels is coupled to the container via the hinge to form a door. The lock secures the container by locking the door in a closed position. The panels are formed of a lightweight, durable structural material, such that the container is portable. At least one of the panels is transparent, such that the container provides an interior view when the door is in the closed position. | 04-09-2009 |
20100157528 | Secure transparent enclosure for communication device - An enclosure comprises first and second sections formed of a transparent material, a plurality of wall sections, a plurality of vent holes, a hinge, a cable access and a lock. The wall sections are joined to the first section to form the enclosure. The vent holes are formed in the wall sections to provide thermal flow through the enclosure. The hinge connects the second section to one of the plurality of wall sections to form a door in the enclosure. The cable access is located to allow authorized power and data connections within the enclosure when the door is in an open position, and sized to prevent unauthorized data connections within the enclosure when the door is in a closed position. The lock secures the enclosure by locking the door in the closed position. | 06-24-2010 |
20100307939 | Rigid transparent tackle box with vertical storage for large-scale lures - A storage system comprises a bottom, a plurality of sides, a cover and a plurality of vertical dividers. The sides are fixed to the bottom and the cover is located to have open and closed positions with respect to the sides, opposite the bottom. The vertical dividers are arranged in first and second transverse orientations between the sides, forming vertical storage units for hanging lures. A plurality of ventilation and drainage holes are formed in the bottom panel, and the top and at least two of the sides are transparent to visible light. Each of the bottom, sides, and cover is formed of an impact-resistant thermoplastic having a thickness of at least 4 mm, such that the cover supports a weight of at least 220 lbs when in the closed position. | 12-09-2010 |