Patent application number | Description | Published |
20090027976 | Threshold device for a memory array - A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations. | 01-29-2009 |
20090303772 | Two-Terminal Reversibly Switchable Memory Device - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 12-10-2009 |
20100157658 | Conductive metal oxide structures in non-volatile re-writable memory devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 06-24-2010 |
20100157710 | Array Operation Using A Schottky Diode As a Non-Ohmic Isolation Device - A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 06-24-2010 |
20100159641 | Memory cell formation using ion implant isolated conductive metal oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 06-24-2010 |
20110149634 | Non-volatile memory device ion barrier - An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile. | 06-23-2011 |
20110149636 | Ion barrier cap - An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile. | 06-23-2011 |
20110291067 | Threshold Device For A Memory Array - A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations. | 12-01-2011 |
20110315943 | Memory Device Using A Dual Layer Conductive Metal Oxide Structure - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 12-29-2011 |
20110315948 | Memory Device Using Ion Implant Isolated Conductive Metal Oxide - Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnO | 12-29-2011 |
20120020143 | Array Operation Using A Schottky Diode As A Non Ohmic Selection Device - A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 01-26-2012 |
20120026780 | Conductive Metal Oxide Structures In Non Volatile Re Writable Memory Devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 02-02-2012 |
20120037879 | NON VOLATILE MEMORY DEVICE ION BARRIER - An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile. | 02-16-2012 |
20120043521 | Conductive Metal Oxide Structures In Non Volatile Re Writable Memory Devices - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 02-23-2012 |
20120087174 | Two Terminal Re Writeable Non Volatile Ion Transport Memory Device - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 04-12-2012 |
20120262981 | DATA RETENTION STRUCTURE FOR NON-VOLATILE MEMORY - A data retention structure in a memory element that stores data as a plurality of conductivity profiles is disclosed. The memory element can be used in a variety of electrical systems and includes a conductive oxide layer, an ion impeding layer, and an electrolytic tunnel barrier layer. A write voltage applied across the memory element causes a portion of the mobile ions to move from the conductive oxide layer, through the ion impeding layer, and into the electrolytic tunnel barrier layer thereby changing a conductivity of the memory element, or the write voltage causes a quantity of the mobile ions to move from the electrolytic tunnel barrier layer, through the ion impeding layer, and back into the conductive oxide layer. The ion impeding layer is operative to substantially stop mobile ion movement when a voltage that is less than the write voltage is applied across the memory element. | 10-18-2012 |
20120286232 | ARRAY OPERATION USING A SCHOTTKY DIODE AS A NON-OHMIC SELECTION DEVICE - A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 11-15-2012 |
20120300535 | NON-VOLATILE MEMORY DEVICE ION BARRIER - An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile. | 11-29-2012 |
20130214233 | CONDUCTIVE METAL OXIDE STRUCTURES IN NON VOLATILE RE WRITABLE MEMORY DEVICES - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 08-22-2013 |
20140014893 | ARRAY OPERATION USING A SCHOTTKY DIODE AS A NON-OHMIC SELECTION DEVICE - A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied. | 01-16-2014 |
20140367629 | CONDUCTIVE METAL OXIDE STRUCTURES IN NON VOLATILE RE WRITABLE MEMORY DEVICES - A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). | 12-18-2014 |
20150029780 | TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 01-29-2015 |
20150380642 | TWO-TERMINAL REVERSIBLY SWITCHABLE MEMORY DEVICE - A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion. | 12-31-2015 |
Patent application number | Description | Published |
20090248739 | System and Method to Support Runtime Model Extension in an Object Relational Mapping (ORM) System - A system and method to support runtime model extension in an Object Relational Mapping (ORM) System. The system includes a relational data storage subsystem for storing and retrieving objects in form of relational data, a tuple storage subsystem for storing and retrieving objects in form of tuple, and a dispatcher/assembler for storing and retrieving original part and extended part of the object respectively into/from the relational data storage subsystem and the tuple storage subsystem. Thus, model extension can be carried out dynamically in the runtime of the ORM system without modifying schema and migrating data in the relational database. | 10-01-2009 |
20110047554 | DECENTRALIZED LOAD DISTRIBUTION TO REDUCE POWER AND/OR COOLING COSTS IN AN EVENT-DRIVEN SYSTEM - A computer-implemented method, computer program product and computer readable storage medium directed to decentralized load placement in an event-driven system so as to minimize energy and cooling related costs. Included are receiving a data flow to be processed by a plurality of tasks at a plurality of nodes in the event-driven system having stateful and stateless event processing components, wherein the plurality of tasks are selected from the group consisting of hierarchical tasks (a task that is dependent on the output of another task), nonhierarchical tasks (a task that is not dependent on the output of another task) and mixtures thereof. Nodes are considered for quiescing whose current tasks can migrate to other nodes while meeting load distribution and energy efficiency parameters and the expected duration of the quiesce provides benefits commensurate with the costs of quiesce and later restart. Additionally, tasks are considered for migrating to neighbor nodes to distribute the system load of processing the tasks and reduce cooling costs. | 02-24-2011 |
20110047555 | DECENTRALIZED LOAD DISTRIBUTION IN AN EVENT-DRIVEN SYSTEM - A computer-implemented method, computer program product and computer readable storage medium directed to decentralized load distribution in an event-driven system. Included are receiving a data flow to be processed by a plurality of tasks at a plurality of nodes in the event-driven system having stateful and stateless event processing components, wherein the plurality of tasks are selected from the group consisting of hierarchical tasks (a task that is dependent on the output of another task), nonhierarchical tasks (a task that is not dependent on the output of another task) and mixtures thereof. Tasks are considered for migration to distribute the system load of processing tasks. The target node, to which the at least one target task is migrated, is chosen wherein the target node meets predetermined criteria in terms of load distribution quality. The computer-implemented method, computer program product and computer readable storage medium of the present invention may also include migrating tasks to target nodes to reduce cooling costs and selecting at least one node to go into quiescent mode. | 02-24-2011 |
20130254778 | DECENTRALIZED LOAD DISTRIBUTION TO REDUCE POWER AND/OR COOLING COSTS IN AN EVENT-DRIVEN SYSTEM - A computer program product and computer readable storage medium directed to decentralized load placement in an event-driven system so as to minimize energy and cooling related costs. Included are receiving a data flow to be processed by a plurality of tasks at a plurality of nodes in the event-driven system having stateful and stateless event processing components, wherein the plurality of tasks are selected from the group consisting of hierarchical tasks (a task that is dependent on the output of another task), nonhierarchical tasks (a task that is not dependent on the output of another task) and mixtures thereof. Nodes are considered for quiescing whose current tasks can migrate to other nodes while meeting load distribution and energy efficiency parameters and the expected duration of the quiesce provides benefits commensurate with the costs of quiesce and later restart. | 09-26-2013 |