Patent application number | Description | Published |
20100106920 | DATA LOCATION OBFUSCATION - Programs running on an open architecture, such as a personal computer, are vulnerable to inspection and modification. This is a concern as the program may include or provide access to valuable information. As a defense, the actual location of data can be hidden throughout execution of the program by way of periodic location reordering and pointer scrambling, among other things. These techniques serve to complicate static data flow analysis and dynamic data tracking thereby at least deterring program tampering. | 04-29-2010 |
20100107245 | TAMPER-TOLERANT PROGRAMS - Tamper-tolerant programs enable correct and continued execution despite attacks. Programs can be transformed into tamper-tolerant versions that correct effects of tampering in response to detection thereof Tamper-tolerant programs can execute alone or in conjunction with tamper resistance/prevention mechanisms such as obfuscation and encryption/decryption, among other things. In fact, the same and/or similar mechanisms can be employed to protect tamper tolerance functionality. | 04-29-2010 |
20130198115 | CLUSTERING CROWDSOURCED DATA TO CREATE AND APPLY DATA INPUT MODELS - The collection and clustering of data input characteristics from a plurality of computing devices is provided. The clustered data input characteristics define user groups to which users are assigned. Input models such as language models and touch models are created for, and distributed to, each of the user groups based on the data input characteristics of the users assigned thereto. For example, an input model may be selected for a computing device based on a current context of the computing device. The selected input model is applied to the computing device during the current context to alter the interpretation of input received from the user via the computing device. | 08-01-2013 |
Patent application number | Description | Published |
20100164638 | METHOD AND CIRCUIT FOR CANCELLING OUT COMPARATOR-DELAY IN THE RELAXATION OSCILLATOR - A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay through the comparator. The duplicate integrator includes current sources and a capacitor matching and switched in tandem with those within the relaxation oscillator, plus an additional current source, and is selectively switched into connection with the comparator input. By canceling the comparator propagation delay, the oscillator output frequency can be stably controlled through selection of resistive and capacitive values, using cheaper technology and tolerating large temperature, voltage and process variations. | 07-01-2010 |
20100166036 | System and method for remote temperature sensing - An apparatus and method are disclosed for temperature measurement that includes performing a first ΔVbe measurement of a first temperature of a diode circuit comprising a transistor and, subsequently, performing a first Vbe measurement of a second temperature of the diode circuit. A temperature difference is calculated between the second temperature and the first temperature. If the temperature difference is not greater than a predetermined amount, a second Vbe measurement of a third temperature of the diode circuit is subsequently performed. If the temperature difference is greater than the predetermined amount, a second ΔVbe measurement of the second temperature of the diode circuit is performed. | 07-01-2010 |
20110148620 | TEST MODE CIRCUITRY FOR A PROGRAMMABLE TAMPER DETECTION CIRCUIT - An integrated circuit includes an output pad, an alarm output pad, and a test mode output pad. A first multi-bit register is programmable to store programmable data such as data that identifies a customer for whom the integrated circuit has been manufactured. A second multi-bit register is programmable to store customer specified threshold data. A first circuit selectively couples the first and second multi-bit registers to the output pad. The first circuit is operable responsive to the integrated circuit being placed into a test mode to perform parallel-to-serial conversion of either the customer identification data stored in the first multi-bit register or the customer specified threshold data stored in the second multi-bit register and drive the converted data for output through the output pad. The integrated circuit further includes a tamper detection circuit operable responsive to the customer specified threshold data to generate a tamper alarm signal. A second circuit selectively couples the tamper alarm signal to the alarm output pad and test mode output pad depending on whether the integrated circuit is in a test mode. More specifically, the second circuit operates to drive the alarm output pad with the tamper alarm signal when the integrated circuit is not in test mode and drive the test mode output pad with the tamper alarm signal when the integrated circuit is in test mode (with the alarm output pad driven to a known state). | 06-23-2011 |
20130188808 | Method and Apparatus for Circuit with Low IC Power Dissipation and High Dynamic Range - An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost gain control element coupled to the selected volume detector; the analog output signal amplifier; and the digital volume amplifier; wherein the boost gain control element is configured to: keep a gain of a path of the digital volume amplifier and the analog output signal amplifier substantially constant, wherein the boost gain control element can adjust both: a) a gain of the digital volume control; and b) a gain of the analog output signal amplifier; to keep the gain of the path of the digital volume amplifier and the analog output signal substantially constant and equal to the selected output volume. | 07-25-2013 |