Patent application number | Description | Published |
20090150602 | MEMORY POWER CONTROL - In a memory device to store information, the device includes a memory core to store information, a memory controller to control storage and retrieval of the information, and a regulator coupled to the memory controller and the memory core, wherein the regulator is operable to adjust an internal voltage to the memory core in response to commands from the memory controller. | 06-11-2009 |
20090282321 | Optional Memory Error Checking - A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the controller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device. | 11-12-2009 |
20100115178 | System and Method for Hierarchical Wear Leveling in Storage Devices - Systems and methods for reducing problems and disadvantages associated with wear leveling in storage devices are disclosed. A method may include maintaining module usage data associated with each of a plurality of storage device modules communicatively coupled to a channel. The method may also include maintaining device usage data associated with each of the plurality of storage devices associated with the storage device module for each of the plurality of storage device modules. The method may additionally include determining a particular storage device module of the plurality of storage device modules to which to store data associated with a write request based at least on the module usage data. The method may further include determining a particular storage device of the particular storage device module to which to store data associated with a write request based at least on the device usage data associated with the particular storage device module. | 05-06-2010 |
20100306440 | SYSTEM AND METHOD FOR SERIAL INTERFACE TOPOLOGIES - A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface. | 12-02-2010 |
20110131432 | System and Method for Reducing Power Consumption of Memory - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable. | 06-02-2011 |
20110296098 | System and Method for Reducing Power Consumption of Memory - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents. | 12-01-2011 |
20120254506 | SYSTEM AND METHOD FOR PERFORMING SYSTEM MEMORY SAVE IN TIERED/CACHED STORAGE - In accordance with the present disclosure, a system and method for performing a system memory save in tiered or cached storage during transition to a decreased power state is disclosed. As disclosed herein, the system incorporating aspects of the present invention may include a flash or other nonvolatile memory such as a solid-state drive, volatile memory, and at least one alternate storage media. Upon transition to a decreased power state, at least some of the data in the solid-state drive, for example, may be transferred to the at least one alternate storage media. After the SSD data is transferred, data stored in volatile system memory, such as a system context, may be transferred to the SSD memory. With the system context saved in SSD memory, power to the volatile system memory may be turned off. | 10-04-2012 |
20130054949 | MEMORY COMPATIBILITY SYSTEM AND METHOD - An apparatus including a first connector configured to fit into a first socket in a processing system, the first connector and first socket conforming to a first standard, a second socket configured to accept a memory module therein, the second socket and the memory module conforming to a second standard, a memory buffer module communicatively coupled to the first connector and the second socket, the memory buffer module configured to receive signals associated with the first standard from the first connector and output signals associated with the second standard to the second socket, and a virtualization module communicatively coupled to the memory buffer module, the first connector, and the second socket, the virtualization module configured to receive first initialization data associated with the second standard from the second socket and output second initialization data associated with the first standard to the processing system. | 02-28-2013 |
20130111308 | SYSTEM AND METHOD FOR SELECTIVE ERROR CHECKING | 05-02-2013 |
20130151767 | MEMORY CONTROLLER-INDEPENDENT MEMORY MIRRORING - A method of memory controller-independent memory mirroring includes providing a mirroring association between a first memory segment and a second memory segment that is independent of a memory controller. A memory buffer receives data from the memory controller that is directed to a first memory location in the first memory segment. The memory buffer writes the data, independent of the memory controller, to both the first memory segment and the second memory segment according to the mirroring association. The memory buffer receives a plurality of read commands from the memory controller that are directed to the first memory location in the first memory segment and, in response, reads data from an alternating one of the first memory segment and the second memory segment and stores both first data from the first memory segment and second data from the second memory segment. | 06-13-2013 |
20130191674 | POWER INPUT UTILIZATION SYSTEM - A power input utilization system includes a plurality of components and a plurality of power input connectors. A power utilization engine is coupled between the plurality of power input connectors and the plurality of components. The detect a power input to the plurality of power input connectors and determine a power input characteristic for the power input. The power utilization engine is also operable to use the power input characteristic to determine a plurality of operation characteristics for the plurality of components. The power utilization engine is also operable to operate the plurality of components using on the power input and the plurality of operation characteristics. | 07-25-2013 |
20130232331 | INFORMATION HANDLING SYSTEM PERFORMANCE OPTIMIZATION SYSTEM - A performance optimization system includes a plurality of system components. A monitoring plug-in and a configuration plug-in are coupled to each of the plurality of system components. A monitoring engine receives monitoring information for each of the plurality of system components from their respective monitoring plug-in. A configuration engine sends configuration setting information to each of the plurality of system components through their respective configuration plug-ins. A performance optimization engine receives the monitoring information from the monitoring engine, determines a policy associated with the monitoring information and, in response, retrieves configuration setting information that is associated with the policy and sends the configuration setting information to the configuration engine in order to change the configuration of at least one of the plurality of system components. | 09-05-2013 |
20130254474 | SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION OF MEMORY - Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable. | 09-26-2013 |
20130254506 | MEMORY CONTROLLER-INDEPENDENT MEMORY SPARING - An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations. | 09-26-2013 |
20140129759 | LOW POWER WRITE JOURNALING STORAGE SYSTEM - A low power write journaling storage system may be part of an information handling system that includes a system processor and a system memory that is coupled to the system processor. The low power write journaling storage system is coupled to the system processor and includes a non-volatile solid state memory system. A first processing element in the low power write journaling storage system is operable, while the storage system is in a storage system first mode, to journal write commands in the non-volatile solid state memory system. A second processing element in the low power write journaling storage system is operable, while the storage system is in a storage system second mode that may cause the low power write journaling storage system to consume more power than when in the storage system first mode, to execute the write commands journaled in the non-volatile solid state memory system. | 05-08-2014 |
20140149833 | SYSTEM AND METHOD FOR SELECTIVE ERROR CHECKING - A method of selectively enabling error checking in an information handling system, including receiving information indicating that data associated with a first memory portion in a system memory should be subject to error checking during transmission between the memory controller and the system memory and indicating that data associated with a second memory portion in the system memory should be free of error checking during transmission between the memory controller and the system memory, receiving a memory access request directed to one of the first and second memory portions, transmitting data between the memory controller and the system memory in response to the memory access request, and selectively performing an error checking technique on the transmitted data based on the information. | 05-29-2014 |
Patent application number | Description | Published |
20090083581 | Methods and Systems for Managing Response Data in an Information Handling System - Methods for managing response data within an information handling system (IHS), where the method includes the step of obtaining response data from at least one component in the IHS, the response data generated in response to receiving a command. The method also includes accumulating the response data from the at least one component to compute a total response time. | 03-26-2009 |
20090240903 | Methods and Apparatus for Translating a System Address - A method for translating a system address includes providing a first system address to a firmware and retrieving a first translation data corresponding to a memory configuration from storage. The first system address is translated into a first physical location utilizing the first translation data, and the first physical location is outputted. | 09-24-2009 |
20100185816 | Multiple Cache Line Size - A mechanism which allows pages of flash memory to be read directly into cache. The mechanism enables different cache line sizes for different cache levels in a cache hierarchy, and optionally, multiple line size support, simultaneously or as an initialization option, in the highest level (largest/slowest) cache. Such a mechanism improves performance and reduces cost for some applications. | 07-22-2010 |
20100293367 | System and Method for Optimizing Performance of an Information Handling System Component - Systems and methods for optimizing performance of an information handling system component communicatively coupled to the information handling system are disclosed. An information handling system may include a data gathering module and an operating condition controller module. The data gathering module may be configured to retrieve an operating condition characterization value from the component. That operating condition characterization value may be substantially based on a predetermined characteristic of the component. The operating condition controller module may be configured to modify an operating condition of the component based at least on the retrieved operating condition characterization value. | 11-18-2010 |
20110078369 | Systems and Methods for Using a Page Table in an Information Handling System Comprising a Semiconductor Storage Device - Systems and methods for using a page table in an information handling system including a semiconductor storage device are disclosed. A page table in an information handling system may be provided. The information handling system may include a memory, and the memory may include a semiconductor storage device. NonDRAM tag data may be stored in the page table. The nonDRAM tag data may indicate one or more attributes of one or more pages in the semiconductor storage device. | 03-31-2011 |
20110082987 | Systems and Methods for Power State Transitioning in an Information Handling System - Systems and methods for power state transitioning in an information handling system having a volatile memory and a nonvolatile memory are disclosed. Dirty data in the volatile memory may be identified. The dirty data may include data that has not been stored in the nonvolatile memory. Dirty data may be written from the volatile memory to the nonvolatile memory. Transitioning to a reduced power state may be in response to a trigger event. Transitioning from the reduced power state may be in response to a wake signal. Data may be copied from the nonvolatile memory to the volatile memory. An operating system may be waked to a restored state. | 04-07-2011 |
20120017052 | Information Handling System Universal Memory Wear Leveling System and Method - An information handling system universal memory architecture assigns memory blocks to information handling system functions, such as a persistent storage function and a working storage function, that have different relative rates of writes of information. The blocks are periodically analyzed for remaining memory life to reassign blocks to functions that result in wear leveling across the blocks. For example, blocks having relatively low life remaining that are assigned to functions having a relatively high number of writes have their function switched with blocks that have a relatively high life remaining that are assigned to functions having a relatively low number of writes. In addition, wear leveling performed within a block ensures even wear of the memory cells within the block. | 01-19-2012 |
20120110380 | INFORMATION HANDLING SYSTEM FORCED ACTION COMMUNICATED OVER AN OPTICAL INTERFACE - A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal. | 05-03-2012 |
20120110381 | INFORMATION HANDLING SYSTEM FORCED ACTION COMMUNICATED OVER AN OPTICAL INTERFACE - A forced power down signal issues from an I/O device to an information handling system through an optical interconnect if the information handling system fails to power down in response to a normal power down message. A 100% duty cycle signal issues from an optical interface at the I/O device and is detected by an optical interface of the information handling system, which issues a command to force a power down of the information handling system in response to the forced power down signal. | 05-03-2012 |
20140156909 | Systems and Methods for Dynamic Optimization of Flash Cache in Storage Devices - In various embodiments, a storage device includes a magnetic media, a cache memory, and a drive controller. In embodiments, the drive controller is configured to establish a portion of the cache memory as an archival zone having a cache policy to maximize write hits. The drive controller is further configured to pre-erase the archival zone, direct writes from a host to the archival zone, and flush writes from the archival zone to the magnetic media. In embodiments, the drive controller is configured to establish a portion of the cache memory as a retrieval zone having a cache policy to maximize read hits. The drive controller is further configured to pre-fetch data from the magnetic media to the retrieval zone, transfer data from the retrieval zone to a host upon request by the host, and transfer read ahead data to the retrieval zone to replace data transferred to the host. | 06-05-2014 |
20150026418 | SYSTEM AND METHOD FOR INCREASED CAPACITY AND SCALABILITY OF A MEMORY TOPOLOGY - A system and method for serial interface topologies is disclosed. A serial interface topology includes a replication device configured to receive control information from a controller interface. The replication device is configured to transmit two or more copies of substantially replicated control information to a device control interface. A data interface is configured to provide differential, point-to-point communication of data with the device controller interface. | 01-22-2015 |
20150039659 | DATA LOCATION MANAGEMENT AGENT USING REMOTE STORAGE - Methods and systems for offloading data to a remote storage resource from a local storage resource on an information handling system may involve using a data location management agent and an offload mapping. The data location management agent may detect requests for access to files stored on a file system and may offload files to the remote storage resource to maintain a specified available capacity of the local storage resource, based on at least in part on the offload mapping. The data location management agent may classify certain files as pinned files that are excluded from offloading. | 02-05-2015 |