Santhanakrishnan
Badrinarayanan Santhanakrishnan, Bangalore IN
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20100021128 | FAST FORWARD MECHANISM FOR DIGITAL VIDEO - Methods and systems for fast forward mechanism for digital video processed by a digital video player are disclosed. In one embodiment, a method for fast forwarding digital video includes receiving an encoded digital video stream having at least one I frame, at least one P frame, and at least one B frame, determining a set of frames for displaying on a display unit of the digital video player based on a data size of each frame present in the encoded digital video stream, decoding each one of the at least one I frame and the at least one P frame, decoding each one of the at least one B frame only if the each one of the at least one B frame belongs to the set of frames, and forwarding the decoded frames of the set of frames for the displaying on the display unit. | 01-28-2010 |
Geeyarpuram N. Santhanakrishnan, Portland, OR US
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20100161907 | POSTING WEAKLY ORDERED TRANSACTIONS - A processor may comprise a core area, a control unit, an uncore area. The core area may comprise multiple processing cores and line-fill buffers. A first processing core of the core area may store a first weakly ordered transaction in a first line-fill buffer. The firs processing core may offload the first weakly ordered transaction to the extended buffer space provisioned in the uncore area after receiving a request from the uncore area. The first processing core may then de-allocate the first line-fill buffer after the first weakly ordered transaction is offloaded to the extended buffer space. The uncore may then post the first weakly ordered transaction to a memory or a memory system. The control unit may track the first weakly ordered transaction to ensure that the first weakly ordered transaction is posted to the memory or the system. | 06-24-2010 |
20100332927 | GENERIC DEBUG EXTERNAL CONNECTION (GDXC) FOR HIGH INTEGRATION INTEGRATED CIRCUITS - A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools. | 12-30-2010 |
Geeyarpuram N. Santhanakrishnan, Mercer Island, WA US
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20130151782 | Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module - In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed. | 06-13-2013 |
20150143051 | Providing Common Caching Agent For Core And Integrated Input/Output (IO) Module - In one embodiment, the present invention includes a multicore processor having a plurality of cores, a shared cache memory, an integrated input/output (IIO) module to interface between the multicore processor and at least one IO device coupled to the multicore processor, and a caching agent to perform cache coherency operations for the plurality of cores and the IIO module. Other embodiments are described and claimed. | 05-21-2015 |
20150269104 | RING PROTOCOL FOR LOW LATENCY INTERCONNECT SWITCH - Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's. | 09-24-2015 |
Lakshmi Santhanakrishnan, Carmel, IN US
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20140035722 | SYSTEMS AND METHODS FOR CONTROLLING ELECTRONICALLY OPERABLE ACCESS DEVICES USING WI-FI AND RADIO FREQUENCY TECHNOLOGY - Systems and methods are disclosed for controlling access devices including WI-FI and dual radio communications between an access control database and one or more access devices in a facility. The systems and methods allow real time communications between the database and the access devices utilizing existing communications WI-FI infrastructure in the facility while minimizing loss of battery life of the access devices by employing the radio network to target all or a portion of the access devices for communications when needed. | 02-06-2014 |
Lakshmi Santhanakrishnan, Indianapolis, IN US
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20160037454 | SYSTEMS AND METHODS FOR CONTROLLING ELECTRONICALLY OPERABLE ACCESS DEVICES USING WI-FI AND RADIO FREQUENCY TECHNOLOGY - Systems and methods are disclosed for controlling access devices including WI-FI and dual radio communications between an access control database and one or more access devices in a facility. The systems and methods allow real time communications between the database and the access devices utilizing existing communications WI-FI infrastructure in the facility while minimizing loss of battery life of the access devices by employing the radio network to target all or a portion of the access devices for communications when needed. | 02-04-2016 |
Manisekaran Santhanakrishnan, Tiruvallur IN
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20110268570 | SYSTEM AND METHOD FOR CONTROLLING WIND TURBINE BLADES - A wind turbine system is presented. The wind turbine system includes a blade comprising an airfoil and a sensing device disposed on a surface of the airfoil, wherein the sensing device generates signals that are representative of pressure deflection on the surface of the airfoil. The wind turbine system further comprises a processing subsystem that receives location details of the sensing device and a transfer function corresponding to the airfoil, determines a location of a stagnation point on the surface of the airfoil based upon the signals and the location details, and determine an angle of attack (AOA) on the surface of the airfoil based upon the location of the stagnation point and the transfer function. | 11-03-2011 |
Manisekaran Santhanakrishnan, Bangalore IN
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20120163969 | TURBINE INCLUDING EXHAUST HOOD - A turbine includes an inner casing, a rotor extending in a longitudinal direction, and rows of buckets transversely disposed on the rotor. A bearing cone covering a portion of the rotor and a flow guide extending from the inner casing define an annular passage for flow of exhaust gases. Exhaust gas movement is facilitated by a guide cap having a streamlined surface and situated in a downstream direction of the flow guide, a tip leakage flow injection channel to inject exhaust gases at the inner surface of the flow guide, an incline of the casing of the turbine surrounding the last stage buckets relative to the longitudinal axis, or use of a first portion of the annular passage with a substantially constant surface area and a second portion of the annular passage with a progressively increasing surface area. | 06-28-2012 |
Prarthna Santhanakrishnan, Austin, TX US
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20140281393 | REORDER-BUFFER-BASED STATIC CHECKPOINTING FOR RENAME TABLE REBUILDING - Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a static mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB. | 09-18-2014 |
20140281414 | REORDER-BUFFER-BASED DYNAMIC CHECKPOINTING FOR RENAME TABLE REBUILDING - Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a dynamic mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB. | 09-18-2014 |
Radhika Santhanakrishnan, Bangalore IN
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20130275585 | SYSTEM AND METHOD FOR PERFORMANCE MEASUREMENT OF NETWORKED ENTERPRISE APPLICATIONS - A method for measuring performance of a networked application is provided. The method enables retrieving performance measurement data from an application database. The data relates to one or more transactions executed via the networked application. The method further enables reconstructing request and response messages using the retrieved data. The messages are reconstructed based on at least one of: web based and socket based calls related to one or more captured transactions. Further, the method enables determining one or more performance measurement metrics based on data obtained by communicating with one or more servers using the reconstructed messages. | 10-17-2013 |
Radhika Santhanakrishnan, Karnataka IN
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20140298302 | METHOD AND SYSTEM FOR DETECTING MEMORY LEAKS IN A PROGRAM - A method and a system have been disclosed for detecting one or more memory leaks in a program. The method includes receiving the program code. After receiving the program, the program is tokenized automatically in a predefined format. The predefined format may correspond to a format which is up-loadable to a database. Thereafter, the tokenized program code is analyzed to determine control flows in the program by using a memory leak pattern. The memory leak pattern is an incorrect control flow between the combination of memory allocation and memory de-allocation functions. After analyzing the tokenized program, the memory leaks are identified based on the determined control flows in the program. The memory leaks are identified during the development phase of the program code. Subsequently, the memory leaks are fixed by a programmer. | 10-02-2014 |
Ramesh Santhanakrishnan, Fremont, CA US
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20120144014 | DIRECTING DATA FLOWS IN DATA CENTERS WITH CLUSTERING SERVICES - Techniques are provided for implementing clustering services in a virtual data center or other virtualized infrastructure in a manner that allows packets to be directed to a particular service engine of a service engine cluster. | 06-07-2012 |
20140089486 | DIRECTING DATA FLOWS IN DATA CENTERS WITH CLUSTERING SERVICES - Techniques are provided for implementing clustering services in a virtual data center or other virtualized infrastructure in a manner that allows packets to be directed to a particular service engine of a service engine cluster. | 03-27-2014 |
Soundarapandian Santhanakrishnan, Madurai IN
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20140263214 | LASER-ASSISTED MACHINING (LAM) OF HARD TISSUES AND BONES - An apparatus and method for laser-assisted machining (LAM) of bone without raising the temperature of the surrounding bone is discussed. The method of LAM of bone involves determining a target bone needing to be machined an then scanning a high power density laser beam along the bone at a machining rate that produces low-heat affected zones (HAZ) on the target bone. The process and apparatus is advantageous over conventional technologies because it provides a chemically clean, coherent, and monochromatic beam to the region to be machined. | 09-18-2014 |
Thankappan Santhanakrishnan, Kerala IN
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20100321698 | METHOD AND APPARATUS FOR THE SIMULTANEOUS GENERATION AND DETECTION OF OPTICAL DIFFRACTION INTERFERENCE PATTERN ON A DETECTOR - The present invention provides for a novel method and apparatus for the simultaneous generation and detection of optical diffraction interference pattern on a photo detector. The monitoring method and apparatus disclosed herein comprises of a (any) continuous wave coherent collimated beam of light (or a laser) falling on an (any) optically reflective coating on the surface of the body with inherent vibrations, or with manifest vibrations induced from another source through any medium where the said light is reflected, and then received on the surface of a (any) photo detector in such a way that the received light falls partially on the active sensing area, and partially on the outer perimeter of the active sensing area. | 12-23-2010 |