Patent application number | Description | Published |
20110292725 | FLASH MEMORY DEVICE AND SYSTEM WITH PROGRAM SEQUENCER, AND PROGRAMMING METHOD - A programming method for a nonvolatile memory device includes performing a LSB programming operation programming all LSB logical pages, and thereafter performing a MSB programming operation programming all MSB logical pages, wherein during the LSB programming operation a selected MLC is programmed to a negative intermediate program state. A program sequence for the LSB and MSB programming operations may be sequential or non-sequential in relation to an order arranged of word lines. | 12-01-2011 |
20120020153 | Nonvolatile Memory Devices with Highly Reliable Programming Capability and Methods of Operating Same - Programming methods of a non-volatile memory device by which a programming error is less likely to occur. A programming method may involve applying a precharge voltage to a program inhibit cell at a different time according to the threshold voltage of the program inhibit cell. A programming method may involve applying a different level of precharge voltage to a program inhibit cell according to the threshold voltage of the program inhibit cell. | 01-26-2012 |
20120044771 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES FOR PERFORMING THE METHOD - A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation. | 02-23-2012 |
20120239861 | NONVOLATILE MEMORY DEVICES WITH PAGE FLAGS, METHODS OF OPERATION AND MEMORY SYSTEMS INCLUDING SAME - A method programming multi-bit data to multi-level non-volatile memory cells (MLC) includes; programming a first page of data to the MLC, programming a first page flag to an initial first flag state in response in the programming of the first page, programming a second page of data to the MLC, in response to programming the second page, determining whether the first page has been programmed and if the first page has been programmed, programming the first page flag to a final first flag state different from the initial first flag state in response to programming of the second page, and if the first page has not been programmed, inhibiting programming of the first page flag during programming of the second page. | 09-20-2012 |
20120307561 | NON-VOLATILE MEMORY DEVICE AND METHOD CONTROLLING DUMMY WORD LINE VOLTAGE ACCORDING TO LOCATION OF SELECTED WORD LINE - A non-volatile memory device includes access circuitry that selects a word line during an operation, applies a selected word line voltage to the selected word line, applies a non-selected word line voltage to non-selected word lines among the word lines, and applies a dummy word line voltage to the dummy word line. The dummy word line voltage is a first dummy word line voltage when the selected word line is not adjacent to the dummy word line and a second dummy word line voltage different from the first dummy word line voltage when the selected word line is adjacent to the dummy word line. | 12-06-2012 |
20130083607 | METHOD OF READING MEMORY CELLS WITH DIFFERENT THRESHOLD VOLTAGES WITHOUT VARIATION OF WORD LINE VOLTAGE AND NONVOLATILE MEMORY DEVICE USING THE SAME - A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells. | 04-04-2013 |
20130117500 | MEMORY SYSTEM AND MEMORY MANAGING METHOD THEREOF - A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value. | 05-09-2013 |
20130117620 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device. | 05-09-2013 |
20130229217 | DYNAMIC LATCH AND DATA OUTPUT DEVICE COMPRISING SAME - A dynamic latch comprises a floating node, a storage node, a write transistor connected to the floating node and the storage node and configured to write data of the floating node to the storage node, and a read transistor connected to the floating node and configured to read the data of the storage node. | 09-05-2013 |
20130250678 | PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION - A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node. | 09-26-2013 |
20130336058 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches. | 12-19-2013 |
20130336071 | NONVOLATILE MEMORY DEVICE AND METHOD OF IMPROVING A PROGRAM EFFICIENCY THEREOF - A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation. | 12-19-2013 |
20140056078 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE AND APPARATUSES FOR PERFORMING THE METHOD - A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation. | 02-27-2014 |
20140334233 | METHOD OF READING MEMORY CELLS WITH DIFFERENT THRESHOLD VOLTAGES WITHOUT VARIATION OF WORD LINE VOLTAGE AND NONVOLATILE MEMORY DEVICE USING THE SAME - A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells. | 11-13-2014 |